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Signals index

J
 java_vm_err : trap : wire
 java_vm_err_c : trap : wire
 jmp_e : ibuf_ctl : input
Connects down to:ibuf_ctl_slice:ibuf_ctl_0:jmp_e , ibuf_ctl_slice:ibuf_ctl_1:jmp_e , ibuf_ctl_slice:ibuf_ctl_2:jmp_e , ibuf_ctl_slice:ibuf_ctl_3:jmp_e , ibuf_ctl_slice:ibuf_ctl_4:jmp_e , ibuf_ctl_slice:ibuf_ctl_5:jmp_e , ibuf_ctl_slice:ibuf_ctl_6:jmp_e , ibuf_ctl_slice:ibuf_ctl_7:jmp_e , ibuf_ctl_slice:ibuf_ctl_8:jmp_e , ibuf_ctl_slice:ibuf_ctl_9:jmp_e , ibuf_ctl_slice:ibuf_ctl_10:jmp_e , ibuf_ctl_slice:ibuf_ctl_11:jmp_e , ibuf_ctl_slice:ibuf_ctl_12:jmp_e , ibuf_ctl_slice:ibuf_ctl_13:jmp_e , ibuf_ctl_slice:ibuf_ctl_14:jmp_e , ibuf_ctl_slice:ibuf_ctl_15:jmp_e , ff_sr:squash_vld_reg:din 
Connects up to:icctl:ibuf_ctl:iu_brtaken_e 
 jmp_e : ibuf_ctl_slice : input
Connects down to:mj_s_ff_snre_d:valid_flop:in , mj_s_ff_snre_d:dirty_flop:in 
Connects up to:ibuf_ctl:ibuf_ctl_0:jmp_e , ibuf_ctl:ibuf_ctl_1:jmp_e , ibuf_ctl:ibuf_ctl_2:jmp_e , ibuf_ctl:ibuf_ctl_3:jmp_e , ibuf_ctl:ibuf_ctl_4:jmp_e , ibuf_ctl:ibuf_ctl_5:jmp_e , ibuf_ctl:ibuf_ctl_6:jmp_e , ibuf_ctl:ibuf_ctl_7:jmp_e , ibuf_ctl:ibuf_ctl_8:jmp_e , ibuf_ctl:ibuf_ctl_9:jmp_e , ibuf_ctl:ibuf_ctl_10:jmp_e , ibuf_ctl:ibuf_ctl_11:jmp_e , ibuf_ctl:ibuf_ctl_12:jmp_e , ibuf_ctl:ibuf_ctl_13:jmp_e , ibuf_ctl:ibuf_ctl_14:jmp_e , ibuf_ctl:ibuf_ctl_15:jmp_e 
 jmp_e : ic_cntl : wire
 jmp_pc : ibuffer : input
Connects down to:mj_s_ff_snr_d_32:jmp_pc_d1_reg:din 
Connects up to:icu_dpath:ibuffer:icu_addr_d1 
 jmp_pc_d1 : ibuffer : wire
Connects down to:mj_s_ff_snr_d_32:jmp_pc_d1_reg:out , mux2_32:pc_mux:in1 
 jsr : ex_ctl : wire
Connects down to:ff_sre:jsr_e_flop:din 
 jsr_e : ex_ctl : wire
Connects down to:ff_sre:jsr_e_flop:out 
 jsr_w : ex_ctl : wire
Connects down to:ff_sre:jsr_w_e_flop:din 
 jsr_w_e : ex_ctl : wire
Connects down to:ff_sre:jsr_w_e_flop:out 
K
 kill_data_vld : pipe_cntl : wire
Connects down to:ff_sr:kill_dv_reg:out 
 kill_inst_d : iu : wire
Connects down to:ifu:ifu:kill_vld_d , pipe:pipe:kill_inst_d 
 kill_inst_d : pipe : output
Connects down to:pipe_cntl:pipe_cntl:kill_inst_d 
Connects up to:iu:pipe:kill_inst_d 
 kill_inst_d : pipe_cntl : output
Connects up to:pipe:pipe_cntl:kill_inst_d 
 kill_inst_e : branch_logic : input
Connects up to:ex_ctl:branch_logic:kill_inst_e 
 kill_inst_e : cpu : wire
Connects down to:iu:iu:kill_inst_e , DCU_MODULE:dcu:kill_inst_e 
 kill_inst_e : dcctl : input
Connects down to:dc_dec:dc_dec:kill_inst_e 
Connects up to:dcu_nocache:dcctl:kill_inst_e , dcu:dcctl:kill_inst_e 
 kill_inst_e : dcu : input
Connects down to:dcctl:dcctl:kill_inst_e 
 kill_inst_e : dcu_nocache : input
Connects down to:dcctl:dcctl:kill_inst_e 
 kill_inst_e : dc_dec : input
Connects up to:dcctl:dc_dec:kill_inst_e 
 kill_inst_e : ex : input
Connects down to:ex_ctl:ex_ctl:kill_inst_e , imdr:ex_imdr:kill_inst_e 
Connects up to:iu:ex:kill_inst_e_int 
 kill_inst_e : ex_ctl : input
Connects down to:branch_logic:branch_logic:kill_inst_e 
Connects up to:ex:ex_ctl:kill_inst_e 
 kill_inst_e : imdr : input
Connects down to:imdr_ctrl:imdr_ctrl_0:kill_inst_e 
Connects up to:ex:ex_imdr:kill_inst_e 
 kill_inst_e : imdr_ctrl : input
Connects up to:imdr:imdr_ctrl_0:kill_inst_e 
 kill_inst_e : iu : output wire
Connects down to:pipe:pipe:kill_inst_e 
Connects up to:cpu:iu:kill_inst_e 
 kill_inst_e : pipe : output
Connects down to:pipe_cntl:pipe_cntl:kill_inst_e 
Connects up to:iu:pipe:kill_inst_e 
 kill_inst_e : pipe_cntl : output
Connects up to:pipe:pipe_cntl:kill_inst_e 
 kill_inst_e_int : iu : wire
Connects down to:ex:ex:kill_inst_e , pipe:pipe:kill_inst_e_int 
 kill_inst_e_int : pipe : output
Connects down to:pipe_cntl:pipe_cntl:kill_inst_e_int 
Connects up to:iu:pipe:kill_inst_e_int 
 kill_inst_e_int : pipe_cntl : output
Connects up to:pipe:pipe_cntl:kill_inst_e_int 
 kill_powerdown : hold_logic : input
Connects up to:iu:hold_logic:kill_powerdown 
 kill_powerdown : iu : wire
Connects down to:trap:trap:kill_powerdown , hold_logic:hold_logic:kill_powerdown 
 kill_powerdown : trap : output
Connects up to:iu:trap:kill_powerdown 
 kill_vld_d : ifu : input
Connects down to:ff_sre:flop_gr_1:din , ff_sre:flop_gr_1:enable , ff_sre:flop_gr_2:din , ff_sre:flop_gr_2:enable , ff_sre:flop_gr_3:din , ff_sre:flop_gr_3:enable , ff_sre:flop_gr_4:din , ff_sre:flop_gr_4:enable , ff_sre:flop_gr_5:din , ff_sre:flop_gr_5:enable , ff_sre:flop_gr_6:din , ff_sre:flop_gr_6:enable , ff_sre:flop_gr_7:din , ff_sre:flop_gr_7:enable , ff_sre:flop_gr_8:din , ff_sre:flop_gr_8:enable , ff_sre:flop_gr_9:din , ff_sre:flop_gr_9:enable , ff_sre:flop_fold:din , ff_sre:flop_fold:enable , ff_sre:flop_no_fold:din , ff_sre:flop_no_fold:enable , ff_sre:flop_valid_rs1:enable , ff_sre:flop_help_rs1:din , ff_sre:flop_help_rs1:enable , ff_sre:flop_lv_rs1:din , ff_sre:flop_lv_rs1:enable , ff_sre:flop_lv_acc_rs1:din , ff_sre:flop_lv_acc_rs1:enable , ff_sre_8:flop_type_rs1:din , ff_sre_8:flop_type_rs1:enable , ff_sre:flop_rev_ops:din , ff_sre:flop_rev_ops:enable , ff_sre:flop_st_op:din , ff_sre:flop_st_op:enable , ff_sre:flop_optop:din , ff_sre:flop_optop:enable , ff_sre:flop_vld_rs2:enable , ff_sre:flop_lv_rs2:din , ff_sre:flop_lv_rs2:enable , ff_sre:flop_lvars_acc_rs2:din , ff_sre:flop_lvars_acc_rs2:enable , ff_sre:flop_vld_op_rcu:enable , ff_sre:flop_vld_op_ucode:enable , ff_sre:flop_vld_op_gen:enable , ff_sre:flop_vld_rsd:enable , ff_sre:flop_drty_inst:din , ff_sre:flop_drty_inst:enable , ff_sre:flop_putfield:din , ff_sre:flop_putfield:enable , ff_sre_3:flop_inst_fold_r:din , ff_sre_3:flop_inst_fold_r:enable 
Connects up to:iu:ifu:kill_inst_d 
L
 l : prils_round_dec : wire
 l : round_dec : wire
 l0md : incmod : wire
Connects down to:inc_decode:incdec:l0md , mj_s_mux4_d_32:l0:sel 
 l0md : inc_decode : output wire
Connects down to:mj_s_ff_snre_d_2:l0md_ff:out 
Connects up to:incmod:incdec:l0md 
 l0md_rom : inc_l0md_rom : output reg
Connects up to:inc_decode:i9:l0md_rom0 , inc_decode:i10:l0md_rom1 
 l0md_rom0 : inc_decode : wire
Connects down to:inc_l0md_rom:i9:l0md_rom , mj_s_mux3_d_2:l0md_mux:in0 
 l0md_rom1 : inc_decode : wire
Connects down to:inc_l0md_rom:i10:l0md_rom , mj_s_mux3_d_2:l0md_mux:in1 
 l0out : incmod : wire
Connects down to:mj_s_mux4_d_32:l0:mx_out , cla_adder_32:looadd:in2 
 l1md : incmod : wire
Connects down to:inc_decode:incdec:l1md , mj_s_mux4_d_32:l1:sel 
 l1md : inc_decode : output wire
Connects down to:mj_s_ff_snre_d_2:l1md_ff:out 
Connects up to:incmod:incdec:l1md 
 l1md_rom : inc_l1md_rom : output reg
Connects up to:inc_decode:i7:l1md_rom0 , inc_decode:i8:l1md_rom1 
 l1md_rom0 : inc_decode : wire
Connects down to:inc_l1md_rom:i7:l1md_rom , mj_s_mux3_d_2:l1md_mux:in0 
 l1md_rom1 : inc_decode : wire
Connects down to:inc_l1md_rom:i8:l1md_rom , mj_s_mux3_d_2:l1md_mux:in1 
 l1out : incmod : wire
Connects down to:mj_s_mux4_d_32:l1:mx_out , cla_adder_32:looadd:in1 
 l2d : ex_ctl : wire
 l2d : rs1_dec : reg
 l2f : ex_ctl : wire
 l2f : rs1_dec : reg
 l2i : ex_ctl : wire
 la0_hit : ex : wire
Connects down to:ex_ctl:ex_ctl:la0_hit , ex_regs:ex_regs:la0_hit 
 la0_hit : ex_ctl : input
Connects up to:ex:ex_ctl:la0_hit 
 la0_hit : ex_regs : output
Connects down to:comp_eq_32:la0_cmp:eq 
Connects up to:ex:ex_regs:la0_hit 
 la0_null_c : ex_ctl : wire
 la0_null_e : ex : wire
Connects down to:ex_ctl:ex_ctl:la0_null_e , ex_regs:ex_regs:la0_null_e 
 la0_null_e : ex_ctl : input
Connects up to:ex:ex_ctl:la0_null_e 
 la0_null_e : ex_regs : output
Connects down to:compare_zero_32:la0_null_cmp:out 
Connects up to:ex:ex_regs:la0_null_e 
 la0_objref_sel : ex_regs : wire
Connects down to:mux2_30:la0_reg_din_mux:sel 
 la0_reg_din : ex_regs : wire
Connects down to:ff_sre_30:lockaddr0_reg:din , mux2_30:la0_reg_din_mux:out 
 la0_reg_we : ex_regs : wire
Connects down to:ff_sre_30:lockaddr0_reg:enable 
 la0_w_reg_din : ex_regs : wire
 la1_hit : ex : wire
Connects down to:ex_ctl:ex_ctl:la1_hit , ex_regs:ex_regs:la1_hit 
 la1_hit : ex_ctl : input
Connects up to:ex:ex_ctl:la1_hit 
 la1_hit : ex_regs : output
Connects down to:comp_eq_32:la1_cmp:eq 
Connects up to:ex:ex_regs:la1_hit 
 la1_null_c : ex_ctl : wire
 la1_null_e : ex : wire
Connects down to:ex_ctl:ex_ctl:la1_null_e , ex_regs:ex_regs:la1_null_e 
 la1_null_e : ex_ctl : input
Connects up to:ex:ex_ctl:la1_null_e 
 la1_null_e : ex_regs : output
Connects down to:compare_zero_32:la1_null_cmp:out 
Connects up to:ex:ex_regs:la1_null_e 
 la1_objref_sel : ex_regs : wire
Connects down to:mux2_30:la1_reg_din_mux:sel 
 la1_reg_din : ex_regs : wire
Connects down to:ff_sre_30:lockaddr1_reg:din , mux2_30:la1_reg_din_mux:out 
 la1_reg_we : ex_regs : wire
Connects down to:ff_sre_30:lockaddr1_reg:enable 
 la1_w_reg_din : ex_regs : wire
 ladd : ex_ctl : wire
 ladd : rs1_dec : reg
 laload : ex_ctl : wire
 land : ex_ctl : wire
 land : rs1_dec : reg
 laovf : mult_add : wire
Connects down to:mj_s_ff_snre_d_6:muhold:din , spdec:spdecode:laovf 
 laovf : spdec : input
Connects up to:mult_add:spdecode:laovf 
 lastore : ex_ctl : wire
 last_ack : bus_monitor : reg
 last_cyc : dcudp_cntl : wire
 last_fill_cyc : dcctl : wire
Connects down to:dcudp_cntl:dcudp_cntl:last_fill_cyc , miss_cntl:miss_cntl:last_fill_cyc 
 last_fill_cyc : dcudp_cntl : input
Connects up to:dcctl:dcudp_cntl:last_fill_cyc 
 last_fill_cyc : miss_cntl : output
Connects up to:dcctl:miss_cntl:last_fill_cyc 
 latch_addr_c : dcctl : output
Connects down to:dcudp_cntl:dcudp_cntl:latch_addr_c 
Connects up to:dcu_nocache:dcctl:latch_addr_c , dcu:dcctl:latch_addr_c 
 latch_addr_c : dcu : wire
Connects down to:dcctl:dcctl:latch_addr_c , dcu_dpath:dcu_dpath:latch_addr_c 
 latch_addr_c : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:latch_addr_c 
 latch_addr_c : dcu_dpath : input
Connects down to:ff_se_32:dcu_addr_c_reg:enable , ff_se_32:dcu_data_reg:enable 
Connects up to:dcu_nocache:dcu_dpath:latch_addr_c , dcu:dcu_dpath:latch_addr_c 
 latch_addr_c : dcu_nocache : wire
Connects down to:dcctl:dcctl:latch_addr_c , dcu_dpath:dcu_dpath:latch_addr_c 
 latch_biu_addr : icctl : output
Connects down to:ic_cntl:ic_cntl:latch_biu_addr 
Connects up to:icu_nocache:icctl:latch_biu_addr , icu:icctl:latch_biu_addr 
 latch_biu_addr : icu : wire
Connects down to:icctl:icctl:latch_biu_addr , icu_dpath:icu_dpath:latch_biu_addr 
 latch_biu_addr : icu_dpath : input
Connects down to:ff_sre_32:biu_addr_reg:enable 
Connects up to:icu_nocache:icu_dpath:latch_biu_addr , icu:icu_dpath:latch_biu_addr 
 latch_biu_addr : icu_nocache : wire
Connects down to:icctl:icctl:latch_biu_addr , icu_dpath:icu_dpath:latch_biu_addr 
 latch_biu_addr : ic_cntl : output
Connects up to:icctl:ic_cntl:latch_biu_addr 
 latch_cf_addr : dcctl : output
Connects down to:dcudp_cntl:dcudp_cntl:latch_cf_addr 
Connects up to:dcu_nocache:dcctl:latch_cf_addr , dcu:dcctl:latch_cf_addr 
 latch_cf_addr : dcu : wire
Connects down to:dcctl:dcctl:latch_cf_addr , dcu_dpath:dcu_dpath:latch_cf_addr 
 latch_cf_addr : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:latch_cf_addr 
 latch_cf_addr : dcu_dpath : input
Connects down to:ff_se_32:cf_addr_reg:enable 
Connects up to:dcu_nocache:dcu_dpath:latch_cf_addr , dcu:dcu_dpath:latch_cf_addr 
 latch_cf_addr : dcu_nocache : wire
Connects down to:dcctl:dcctl:latch_cf_addr , dcu_dpath:dcu_dpath:latch_cf_addr 
 latch_wb_addr : dcctl : output
Connects down to:dcudp_cntl:dcudp_cntl:latch_wb_addr 
Connects up to:dcu_nocache:dcctl:latch_wb_addr , dcu:dcctl:latch_wb_addr 
 latch_wb_addr : dcu : wire
Connects down to:dcctl:dcctl:latch_wb_addr , dcu_dpath:dcu_dpath:latch_wb_addr 
 latch_wb_addr : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:latch_wb_addr 
 latch_wb_addr : dcu_dpath : input
Connects down to:ff_se_32:wb_addr_reg:enable 
Connects up to:dcu_nocache:dcu_dpath:latch_wb_addr , dcu:dcu_dpath:latch_wb_addr 
 latch_wb_addr : dcu_nocache : wire
Connects down to:dcctl:dcctl:latch_wb_addr , dcu_dpath:dcu_dpath:latch_wb_addr 
 latch_wr_data : dcctl : output
Connects down to:dcudp_cntl:dcudp_cntl:latch_wr_data 
Connects up to:dcu_nocache:dcctl:latch_wr_data , dcu:dcctl:latch_wr_data 
 latch_wr_data : dcu : wire
Connects down to:dcctl:dcctl:latch_wr_data , dcu_dpath:dcu_dpath:latch_wr_data 
 latch_wr_data : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:latch_wr_data 
 latch_wr_data : dcu_dpath : input
Connects down to:ff_se_32:write_miss_reg:enable 
Connects up to:dcu_nocache:dcu_dpath:latch_wr_data , dcu:dcu_dpath:latch_wr_data 
 latch_wr_data : dcu_nocache : wire
Connects down to:dcctl:dcctl:latch_wr_data , dcu_dpath:dcu_dpath:latch_wr_data 
 lbit : spdec : wire
 lc0_cacheon_din : ex_regs : wire
Connects down to:ff_sre:lockcount0_cacheon_reg:din , mux2:lc0_cacheon_din_mux:out 
 lc0_count_din : ex_regs : wire
Connects down to:ff_se_8:lockcount0_count_reg:din , mux4_8:lc0_din_mux:out 
 lc0_count_reg_we : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_count_reg_we , ex_regs:ex_regs:lc0_count_reg_we 
 lc0_count_reg_we : ex_ctl : output
Connects up to:ex:ex_ctl:lc0_count_reg_we 
 lc0_count_reg_we : ex_regs : input
Connects down to:ff_se_8:lockcount0_count_reg:enable 
Connects up to:ex:ex_regs:lc0_count_reg_we 
 lc0_co_bit : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_co_bit , ex_regs:ex_regs:lc0_co_bit 
 lc0_co_bit : ex_ctl : input
Connects up to:ex:ex_ctl:lc0_co_bit 
 lc0_co_bit : ex_regs : output
Connects up to:ex:ex_regs:lc0_co_bit 
 lc0_co_reg_en : ex_regs : wire
Connects down to:ff_sre:lockcount0_cacheon_reg:enable 
 lc0_co_reset_l : ex_regs : wire
Connects down to:ff_sre:lockcount0_cacheon_reg:reset_l 
 lc0_din_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_din_mux_sel , ex_regs:ex_regs:lc0_din_mux_sel 
 lc0_din_mux_sel : ex_ctl : output
Connects up to:ex:ex_ctl:lc0_din_mux_sel 
 lc0_din_mux_sel : ex_regs : input
Connects down to:mux4_8:lc0_din_mux:sel 
Connects up to:ex:ex_regs:lc0_din_mux_sel 
 lc0_eq_0 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_eq_0 , ex_regs:ex_regs:lc0_eq_0 
 lc0_eq_0 : ex_ctl : input
Connects up to:ex:ex_ctl:lc0_eq_0 
 lc0_eq_0 : ex_regs : output
Connects down to:cmp_eq_8:lc0_cmp:eq 
Connects up to:ex:ex_regs:lc0_eq_0 
 lc0_eq_255 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_eq_255 , ex_regs:ex_regs:lc0_eq_255 
 lc0_eq_255 : ex_ctl : input
Connects up to:ex:ex_ctl:lc0_eq_255 
 lc0_eq_255 : ex_regs : output
Connects down to:cla_adder_8:lc0_p1_adder:cout 
Connects up to:ex:ex_regs:lc0_eq_255 
 lc0_m1 : ex_regs : wire
Connects down to:cla_adder_8:lc0_m1_adder:sum , cmp_eq_8:lc0_m1_cmp:in1 , mux4_8:lc0_din_mux:in1 
 lc0_m1_adder_cout : ex_regs : wire
Connects down to:cla_adder_8:lc0_m1_adder:cout 
 lc0_m1_eq_0 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc0_m1_eq_0 , ex_regs:ex_regs:lc0_m1_eq_0 
 lc0_m1_eq_0 : ex_ctl : input
Connects up to:ex:ex_ctl:lc0_m1_eq_0 
 lc0_m1_eq_0 : ex_regs : output
Connects down to:cmp_eq_8:lc0_m1_cmp:eq 
Connects up to:ex:ex_regs:lc0_m1_eq_0 
 lc0_one_sel : ex_regs : wire
 lc0_p1 : ex_regs : wire
Connects down to:cla_adder_8:lc0_p1_adder:sum , mux4_8:lc0_din_mux:in2 
 lc0_w_reg_din : ex_regs : wire
 lc1_cacheon_din : ex_regs : wire
Connects down to:ff_sre:lockcount1_cacheon_reg:din , mux2:lc1_cacheon_din_mux:out 
 lc1_count_din : ex_regs : wire
Connects down to:ff_se_8:lockcount1_count_reg:din , mux4_8:lc1_din_mux:out 
 lc1_count_reg_we : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_count_reg_we , ex_regs:ex_regs:lc1_count_reg_we 
 lc1_count_reg_we : ex_ctl : output
Connects up to:ex:ex_ctl:lc1_count_reg_we 
 lc1_count_reg_we : ex_regs : input
Connects down to:ff_se_8:lockcount1_count_reg:enable 
Connects up to:ex:ex_regs:lc1_count_reg_we 
 lc1_co_bit : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_co_bit , ex_regs:ex_regs:lc1_co_bit 
 lc1_co_bit : ex_ctl : input
Connects up to:ex:ex_ctl:lc1_co_bit 
 lc1_co_bit : ex_regs : output
Connects up to:ex:ex_regs:lc1_co_bit 
 lc1_co_reg_en : ex_regs : wire
Connects down to:ff_sre:lockcount1_cacheon_reg:enable 
 lc1_co_reset_l : ex_regs : wire
Connects down to:ff_sre:lockcount1_cacheon_reg:reset_l 
 lc1_din_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_din_mux_sel , ex_regs:ex_regs:lc1_din_mux_sel 
 lc1_din_mux_sel : ex_ctl : output
Connects up to:ex:ex_ctl:lc1_din_mux_sel 
 lc1_din_mux_sel : ex_regs : input
Connects down to:mux4_8:lc1_din_mux:sel 
Connects up to:ex:ex_regs:lc1_din_mux_sel 
 lc1_eq_0 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_eq_0 , ex_regs:ex_regs:lc1_eq_0 
 lc1_eq_0 : ex_ctl : input
Connects up to:ex:ex_ctl:lc1_eq_0 
 lc1_eq_0 : ex_regs : output
Connects down to:cmp_eq_8:lc1_cmp:eq 
Connects up to:ex:ex_regs:lc1_eq_0 
 lc1_eq_255 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_eq_255 , ex_regs:ex_regs:lc1_eq_255 
 lc1_eq_255 : ex_ctl : input
Connects up to:ex:ex_ctl:lc1_eq_255 
 lc1_eq_255 : ex_regs : output
Connects down to:cla_adder_8:lc1_p1_adder:cout 
Connects up to:ex:ex_regs:lc1_eq_255 
 lc1_m1 : ex_regs : wire
Connects down to:cla_adder_8:lc1_m1_adder:sum , cmp_eq_8:lc1_m1_cmp:in1 , mux4_8:lc1_din_mux:in1 
 lc1_m1_adder_cout : ex_regs : wire
Connects down to:cla_adder_8:lc1_m1_adder:cout 
 lc1_m1_eq_0 : ex : wire
Connects down to:ex_ctl:ex_ctl:lc1_m1_eq_0 , ex_regs:ex_regs:lc1_m1_eq_0 
 lc1_m1_eq_0 : ex_ctl : input
Connects up to:ex:ex_ctl:lc1_m1_eq_0 
 lc1_m1_eq_0 : ex_regs : output
Connects down to:cmp_eq_8:lc1_m1_cmp:eq 
Connects up to:ex:ex_regs:lc1_m1_eq_0 
 lc1_one_sel : ex_regs : wire
 lc1_p1 : ex_regs : wire
Connects down to:cla_adder_8:lc1_p1_adder:sum , mux4_8:lc1_din_mux:in2 
 lc1_w_reg_din : ex_regs : wire
 lcmp : ex_ctl : wire
Connects down to:ff_sre:lcmp_reg:din 
 lcmp : rs1_dec : reg
 lcmp_e : ex_ctl : wire
Connects down to:ff_sre:lcmp_reg:out , ff_sre:first_gt_reg:din , ff_sre:first_eq_reg:din , ff_sre:first_lt_reg:din 
 lconst_0 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:lconst_0_rs1 , rcu_ctl:decode_opcode_rs2:lconst_0_rs2 
 lconst_0 : ex_ctl : wire
 lconst_0 : rs1_dec : reg
 lconst_0_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:lconst_0 
 lconst_0_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:lconst_0 
 lconst_1 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:lconst_1_rs1 , rcu_ctl:decode_opcode_rs2:lconst_1_rs2 
 lconst_1 : ex_ctl : wire
 lconst_1 : rs1_dec : reg
 lconst_1_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:lconst_1 
 lconst_1_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:lconst_1 
 ldc : ex_ctl : wire
 ldc2_w : ex_ctl : wire
 ldc2_w_quick : ex_ctl : wire
 ldc_quick : ex_ctl : wire
 ldc_w : ex_ctl : wire
 ldc_w_quick : ex_ctl : wire
 ldiv : ex_ctl : wire
 ldst_half_word_c : ex_ctl : wire
Connects down to:ff_sre:ldst_half_word_c_flop:out 
 ldst_half_word_e : ex_ctl : wire
Connects down to:ff_sre:ldst_half_word_e_flop:out , ff_sre:ldst_half_word_c_flop:din 
 ldst_half_word_r : ex_ctl : wire
Connects down to:ff_sre:ldst_half_word_e_flop:din 
 ldst_word_c : ex_ctl : wire
Connects down to:ff_sre:ldst_word_c_flop:out 
 ldst_word_e : ex_ctl : wire
Connects down to:ff_sre:ldst_word_e_flop:out , ff_sre:ldst_word_c_flop:din 
 ldst_word_r : ex_ctl : wire
Connects down to:ff_sre:ldst_word_e_flop:din 
 lduse_bypass : ex : input
Connects down to:ex_ctl:ex_ctl:lduse_bypass 
Connects up to:iu:ex:lduse_bypass 
 lduse_bypass : ex_ctl : input
Connects up to:ex:ex_ctl:lduse_bypass 
 lduse_bypass : iu : wire
Connects down to:ex:ex:lduse_bypass , pipe:pipe:lduse_bypass 
 lduse_bypass : pipe : output
Connects down to:pipe_cntl:pipe_cntl:lduse_bypass 
Connects up to:iu:pipe:lduse_bypass 
 lduse_bypass : pipe_cntl : output
Connects up to:pipe:pipe_cntl:lduse_bypass 
 lduse_byp_vld : pipe_cntl : wire
 lduse_hold : hold_logic : input
Connects up to:iu:hold_logic:lduse_hold 
 lduse_hold : iu : wire
Connects down to:pipe:pipe:lduse_hold , hold_logic:hold_logic:lduse_hold 
 lduse_hold : pipe : output
Connects down to:pipe_cntl:pipe_cntl:lduse_hold 
Connects up to:iu:pipe:lduse_hold 
 lduse_hold : pipe_cntl : output
Connects up to:pipe:pipe_cntl:lduse_hold 
 lduse_state : pipe_cntl : wire
Connects down to:ff_sr_3:lduse_state_reg:out 
 ld_a_oprd0 : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:ld_a_oprd0 , imdr_ctrl:imdr_ctrl_0:ld_a_oprd0 
 ld_a_oprd0 : imdr_ctrl : output
Connects up to:imdr:imdr_ctrl_0:ld_a_oprd0 
 ld_a_oprd0 : imdr_dpath : input
Connects down to:zero_det:zero_det_0:ld_a_oprd0 
Connects up to:imdr:imdr_dpath_0:ld_a_oprd0 
 ld_a_oprd0 : zero_det : input
Connects up to:imdr_dpath:zero_det_0:ld_a_oprd0 
 ld_by_index : rs1_dec : reg
 ld_b_oprd0 : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:ld_b_oprd0 , imdr_ctrl:imdr_ctrl_0:ld_b_oprd0 
 ld_b_oprd0 : imdr_ctrl : output
Connects up to:imdr:imdr_ctrl_0:ld_b_oprd0 
 ld_b_oprd0 : imdr_dpath : input
Connects down to:zero_det:zero_det_0:ld_b_oprd0 
Connects up to:imdr:imdr_dpath_0:ld_b_oprd0 
 ld_b_oprd0 : zero_det : input
Connects up to:imdr_dpath:zero_det_0:ld_b_oprd0 
 ld_ch_index : rs1_dec : reg
 ld_leading0 : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:ld_leading0 , imdr_ctrl:imdr_ctrl_0:ld_leading0 
 ld_leading0 : imdr_ctrl : output
Connects up to:imdr:imdr_ctrl_0:ld_leading0 
 ld_leading0 : imdr_dpath : input
Connects down to:zero_det:zero_det_0:ld_leading0 
Connects up to:imdr:imdr_dpath_0:ld_leading0 
 ld_leading0 : zero_det : input
Connects up to:imdr_dpath:zero_det_0:ld_leading0 
 ld_sh_index : rs1_dec : reg
 ld_sign : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:ld_sign , imdr_ctrl:imdr_ctrl_0:ld_sign 
 ld_sign : imdr_ctrl : output
Connects up to:imdr:imdr_ctrl_0:ld_sign 
 ld_sign : imdr_dpath : input
Connects down to:sign_bit:sign_bit_0:ld_sign 
Connects up to:imdr:imdr_dpath_0:ld_sign 
 ld_sign : sign_bit : input
Connects up to:imdr_dpath:sign_bit_0:ld_sign 
 ld_st_c : dc_dec : wire
 ld_st_e : dc_dec : wire
 ld_ub_index : rs1_dec : reg
 ld_wd_index : rs1_dec : reg
 le : branch_dec : input
Connects down to:mj_s_mux4_d:m0:in3 
Connects up to:code_seq_cntl:branchd:le 
 le : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:le 
Connects up to:fpu:cs:le 
 le : code_seq_cntl : input
Connects down to:branch_dec:branchd:le 
Connects up to:code_seq:p_code_seq_cntl:le 
 le : comp_le_32 : output
Connects up to:rcu_dpath:comp_flush1:iu_smu_flush_le 
 le : exple_dec : output reg
Connects up to:exponent_cntl:expcomp:le 
 le : exponent : output wire
Connects down to:exponent_cntl:p_exponent_cntl:le 
Connects up to:fpu:exp:le 
 le : exponent_cntl : output
Connects down to:exple_dec:expcomp:le 
Connects up to:exponent:p_exponent_cntl:le 
 le : fpu : wire
Connects down to:exponent:exp:le , code_seq:cs:le 
 leadbit : mult_array : wire
Connects down to:signgen:signgeneration:leadbit , highlow:highlowsel:s28 
 leadbit : signgen : output
Connects up to:mult_array:signgeneration:leadbit 
 leading0 : zero_det : wire
Connects down to:ff_s_4:ff_s_4_0:din 
 leading0_r : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:leading0_r , imdr_ctrl:imdr_ctrl_0:leading0_r 
 leading0_r : imdr_ctrl : input
Connects up to:imdr:imdr_ctrl_0:leading0_r 
 leading0_r : imdr_dpath : output
Connects down to:zero_det:zero_det_0:leading0_r 
Connects up to:imdr:imdr_dpath_0:leading0_r 
 leading0_r : zero_det : output wire
Connects down to:ff_s_4:ff_s_4_0:out 
Connects up to:imdr_dpath:zero_det_0:leading0_r 
 len : ic_len_decoder : output reg
Connects up to:icu_dpath:opcode_len_encode_0:encode_oplen , icu_dpath:opcode_len_encode_1:encode_oplen , icu_dpath:opcode_len_encode_2:encode_oplen , icu_dpath:opcode_len_encode_3:encode_oplen , icu_dpath:opcode_len_encode_4:encode_oplen , icu_dpath:opcode_len_encode_5:encode_oplen , icu_dpath:opcode_len_encode_6:encode_oplen , icu_dpath:opcode_len_encode_7:encode_oplen 
 len0 : ex_len_dec : output
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 len1 : ex_len_dec : output reg
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 len2 : ex_len_dec : output reg
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 len3 : ex_len_dec : output reg
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 len4 : ex_len_dec : output reg
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 len5 : ex_len_dec : output reg
Connects up to:ifu:ex_len_dec:ex_len_first_inst 
 lenable : mj_s_ff_se_d : input
Connects up to:mj_s_ff_se_d_3:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d_3:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d_3:mj_s_ff_se_d_2:lenable , mj_s_ff_se_d_4:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d_4:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d_4:mj_s_ff_se_d_2:lenable , mj_s_ff_se_d_4:mj_s_ff_se_d_3:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_2:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_3:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_4:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_5:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_6:lenable , mj_s_ff_se_d_8:mj_s_ff_se_d_7:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_0:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_1:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_2:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_3:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_4:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_5:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_6:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_7:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_8:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_9:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_10:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_11:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_12:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_13:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_14:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_15:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_16:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_17:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_18:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_19:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_20:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_21:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_22:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_23:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_24:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_25:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_26:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_27:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_28:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_29:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_30:lenable , mj_s_ff_se_d_32:mj_s_ff_s_d_31:lenable , ff_se:mj_s_ff_se_d_0:enable 
 lenable : mj_s_ff_se_d_3 : input
Connects down to:mj_s_ff_se_d:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d:mj_s_ff_se_d_2:lenable 
 lenable : mj_s_ff_se_d_32 : input
Connects down to:mj_s_ff_se_d:mj_s_ff_s_d_0:lenable , mj_s_ff_se_d:mj_s_ff_s_d_1:lenable , mj_s_ff_se_d:mj_s_ff_s_d_2:lenable , mj_s_ff_se_d:mj_s_ff_s_d_3:lenable , mj_s_ff_se_d:mj_s_ff_s_d_4:lenable , mj_s_ff_se_d:mj_s_ff_s_d_5:lenable , mj_s_ff_se_d:mj_s_ff_s_d_6:lenable , mj_s_ff_se_d:mj_s_ff_s_d_7:lenable , mj_s_ff_se_d:mj_s_ff_s_d_8:lenable , mj_s_ff_se_d:mj_s_ff_s_d_9:lenable , mj_s_ff_se_d:mj_s_ff_s_d_10:lenable , mj_s_ff_se_d:mj_s_ff_s_d_11:lenable , mj_s_ff_se_d:mj_s_ff_s_d_12:lenable , mj_s_ff_se_d:mj_s_ff_s_d_13:lenable , mj_s_ff_se_d:mj_s_ff_s_d_14:lenable , mj_s_ff_se_d:mj_s_ff_s_d_15:lenable , mj_s_ff_se_d:mj_s_ff_s_d_16:lenable , mj_s_ff_se_d:mj_s_ff_s_d_17:lenable , mj_s_ff_se_d:mj_s_ff_s_d_18:lenable , mj_s_ff_se_d:mj_s_ff_s_d_19:lenable , mj_s_ff_se_d:mj_s_ff_s_d_20:lenable , mj_s_ff_se_d:mj_s_ff_s_d_21:lenable , mj_s_ff_se_d:mj_s_ff_s_d_22:lenable , mj_s_ff_se_d:mj_s_ff_s_d_23:lenable , mj_s_ff_se_d:mj_s_ff_s_d_24:lenable , mj_s_ff_se_d:mj_s_ff_s_d_25:lenable , mj_s_ff_se_d:mj_s_ff_s_d_26:lenable , mj_s_ff_se_d:mj_s_ff_s_d_27:lenable , mj_s_ff_se_d:mj_s_ff_s_d_28:lenable , mj_s_ff_se_d:mj_s_ff_s_d_29:lenable , mj_s_ff_se_d:mj_s_ff_s_d_30:lenable , mj_s_ff_se_d:mj_s_ff_s_d_31:lenable 
 lenable : mj_s_ff_se_d_4 : input
Connects down to:mj_s_ff_se_d:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d:mj_s_ff_se_d_2:lenable , mj_s_ff_se_d:mj_s_ff_se_d_3:lenable 
Connects up to:ibuf_slice:ibuf_len_flop:ibuf_en 
 lenable : mj_s_ff_se_d_8 : input
Connects down to:mj_s_ff_se_d:mj_s_ff_se_d_0:lenable , mj_s_ff_se_d:mj_s_ff_se_d_1:lenable , mj_s_ff_se_d:mj_s_ff_se_d_2:lenable , mj_s_ff_se_d:mj_s_ff_se_d_3:lenable , mj_s_ff_se_d:mj_s_ff_se_d_4:lenable , mj_s_ff_se_d:mj_s_ff_se_d_5:lenable , mj_s_ff_se_d:mj_s_ff_se_d_6:lenable , mj_s_ff_se_d:mj_s_ff_se_d_7:lenable 
Connects up to:ibuf_slice:ibuf_data_flop:ibuf_en 
 lenable : mj_s_ff_snre_d : input
Connects up to:ibuf_ctl_slice:valid_flop:ibuf_en , ibuf_ctl_slice:dirty_flop:ibuf_en , mj_s_ff_snre_d_12:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_12:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_16:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_18:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_2:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_2:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_3:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_3:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_3:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_4:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_4:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_4:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_4:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_6:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_7:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_8:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_23:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_28:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d_30:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d_32:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d_33:mj_s_ff_snre_d_32:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_32:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_33:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_34:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_35:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_36:lenable , mj_s_ff_snre_d_38:mj_s_ff_snre_d_37:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_32:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_33:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_34:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_35:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_36:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_37:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_38:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_39:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_40:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_41:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_42:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_43:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_44:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_45:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_46:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_47:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_48:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_49:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_50:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_51:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_52:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_53:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_54:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_55:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_56:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_57:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_58:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_59:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_60:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_61:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_62:lenable , mj_s_ff_snre_d_64:mj_s_ff_snre_d_63:lenable , mantissa_cntl:a2reg:fpuhold_l , nxsign:abs:fpuhold_l , nxsign:abs1:fpuhold_l , nxsign:ead:fpuhold_l , nxsign:absig:fpuhold_l , code_seq_dp:ff_opvalid:fpuhold_l , code_seq_dp:ff_valid:fpuhold_l , code_seq_dp:ff_valid_a:fpuhold_l , ff_sre:mj_s_ff_snre_d_0:enable 
 lenable : mj_s_ff_snre_d_12 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable 
 lenable : mj_s_ff_snre_d_16 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable 
Connects up to:exponent_dp:ff_excon:fpuhold_l , exponent_dp:aex:fpuhold_l , exponent_dp:bex:fpuhold_l , exponent_dp:sax:fpuhold_l 
 lenable : mj_s_ff_snre_d_18 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable 
Connects up to:multmod_dp:multdecout_moutselcntl:fpuhold_l 
 lenable : mj_s_ff_snre_d_2 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable 
Connects up to:inc_decode:t1mda_ff:fpuhold_l , inc_decode:t0md_ff:fpuhold_l , inc_decode:l0md_ff:fpuhold_l , inc_decode:l1md_ff:fpuhold_l , mult_array:ffextra6c:fpuhold_l , exptop_dec:mux1ad_ff:fpuhold_l , pri_dec:m1_ff:fpuhold_l 
 lenable : mj_s_ff_snre_d_23 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable 
 lenable : mj_s_ff_snre_d_28 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable 
Connects up to:mult_add:ffincsin:fpuhold_l , multmod_dp:ffsinlo:fpuhold_l , multmod_dp:ffcinlo:fpuhold_l , multmod_dp:ffsinhi:fpuhold_l , multmod_dp:ffcinhi:fpuhold_l 
 lenable : mj_s_ff_snre_d_3 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable 
Connects up to:rsadd_cntl:ff:fpuhold_l 
 lenable : mj_s_ff_snre_d_30 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_29:lenable 
 lenable : mj_s_ff_snre_d_32 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_31:lenable 
Connects up to:incmod:q0reg:fpuhold_l , incmod:q1reg:fpuhold_l , mantissa_dp:nta1:fpuhold_l , mantissa_dp:nta0:fpuhold_l , mantissa_dp:ntb1:fpuhold_l , mantissa_dp:ntb0:fpuhold_l , mantissa_dp:ff_r1out:fpuhold_l , mantissa_dp:ff_r0out:fpuhold_l 
 lenable : mj_s_ff_snre_d_33 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_32:lenable 
 lenable : mj_s_ff_snre_d_38 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_32:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_33:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_34:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_35:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_36:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_37:lenable 
 lenable : mj_s_ff_snre_d_4 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable 
Connects up to:code_seq_dp:link_mod:fpuhold_l 
 lenable : mj_s_ff_snre_d_6 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable 
Connects up to:mult_add:muhold:fpuhold_l , code_seq_cntl:conreg:fpuhold , multmod_dp:mult_state:fpuhold_l 
 lenable : mj_s_ff_snre_d_64 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_8:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_9:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_10:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_11:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_12:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_13:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_14:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_15:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_16:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_17:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_18:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_19:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_20:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_21:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_22:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_23:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_24:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_25:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_26:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_27:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_28:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_29:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_30:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_31:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_32:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_33:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_34:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_35:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_36:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_37:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_38:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_39:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_40:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_41:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_42:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_43:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_44:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_45:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_46:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_47:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_48:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_49:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_50:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_51:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_52:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_53:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_54:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_55:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_56:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_57:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_58:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_59:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_60:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_61:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_62:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_63:lenable 
Connects up to:code_seq_dp:mw:fpuhold_l 
 lenable : mj_s_ff_snre_d_7 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable 
Connects up to:mult_array:ffsavec0:fpuhold_l , mult_array:ffsaves0:fpuhold_l , mult_array:ffsaves1:fpuhold_l 
 lenable : mj_s_ff_snre_d_8 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_1:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_2:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_3:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_4:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_5:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_6:lenable , mj_s_ff_snre_d:mj_s_ff_snre_d_7:lenable 
Connects up to:fpu_dec:ff_fpstate:fpuhold , code_seq_dp:ffopcode:fpuhold_l 
 less : comp3_30 : wire
Connects down to:less_comp3:comparator:less 
 less : comp_ls_32 : output
Connects down to:cmp32_ks_lt:i_cmp32_ks_lt:a_ltn_b 
 less : less_comp3 : output
Connects up to:comp3_30:comparator:less 
 less_than_6 : monitor : wire
Connects down to:smu_monitor:smu_monitor:less_than_6 
 less_than_6 : smu_ctl : wire
 less_than_6 : smu_monitor : input
Connects up to:monitor:smu_monitor:less_than_6 , monitor:smu_monitor:smu , monitor:smu_monitor:smu_ctl 
 less_than_6_raw : smu_ctl : wire
Connects down to:comp3_30:six_entr_comp:result 
 level_1 : cmp16zero : wire
 level_1 : cmp19_e : wire
 level_1 : cmp20_e : wire
 level_1 : cmp32zero : wire
 level_1 : cmp32_e : wire
 level_2 : cmp16zero : wire
 level_2 : cmp19_e : wire
 level_2 : cmp20_e : wire
 level_2 : cmp32zero : wire
 level_2 : cmp32_e : wire
 lev_0 : shift_64 : wire
Connects down to:mx21_64_l:mx_0:mx_out , mx21_64_l:mx_1:in0 , mx21_64_l:mx_1:in1 
 lev_1 : shift_64 : wire
Connects down to:mx21_64_l:mx_1:mx_out , mx21_64_l:mx_2:in0 , mx21_64_l:mx_2:in1 
 lev_2 : shift_64 : wire
Connects down to:mx21_64_l:mx_2:mx_out , mx21_64_l:mx_3:in0 , mx21_64_l:mx_3:in1 
 lev_3 : shift_64 : wire
Connects down to:mx21_64_l:mx_3:mx_out , mx21_64_l:mx_4:in0 , mx21_64_l:mx_4:in1 
 lev_4 : shift_64 : wire
Connects down to:mx21_64_l:mx_4:mx_out , mx21_64_l:mx_5:in0 , mx21_64_l:mx_5:in1 
 lev_5 : shift_64 : wire
Connects down to:mx21_64_l:mx_5:mx_out , mx21_64_l:mx_6:in0 , mx21_64_l:mx_6:in1 
 lev_6 : shift_64 : wire
Connects down to:mx21_64_l:mx_6:mx_out , mx21_64_l:mx_7:in0 
 lin : mult_add : wire
Connects down to:mj_s_mux4_d_8:spmux_7_0:in2 , mj_s_mux4_d_8:spmux_7_0:in3 , spdec:spdecode:lin 
 lin : spdec : output reg
Connects up to:mult_add:spdecode:lin 
 link : code_seq_dp : wire
Connects down to:mj_s_mux4_d_8:mx_code_add_0:in3 , mj_s_mux2_d_4:linkmux_0:in0 , mj_s_mux2_d_4:linkmux_1:in0 , mj_s_mux3_d_4:linkmuxfinal:in2 , mj_s_ff_snre_d_4:link_mod:out 
 lload : ex_ctl : wire
 lload : rs1_dec : reg
 lload : rs2_dec : wire
 lload_0 : ex_ctl : wire
 lload_0 : rs1_dec : reg
 lload_0 : rs2_dec : wire
 lload_1 : ex_ctl : wire
 lload_1 : rs1_dec : reg
 lload_1 : rs2_dec : wire
 lload_2 : ex_ctl : wire
 lload_2 : rs1_dec : reg
 lload_2 : rs2_dec : wire
 lload_3 : ex_ctl : wire
 lload_3 : rs1_dec : reg
 lload_3 : rs2_dec : wire
 lmul : ex_ctl : wire
 lneg : ex_ctl : wire
Connects down to:ff_sre:adder_src2_mux_sel_reg:din 
 lneg : rs1_dec : reg
 lo : lsft31_63i_32o : input
Connects up to:lshift:f_dpcl_lshift:low 
 LO : mppartial : output
Connects up to:mpmux:mppart1:part1lo , mpmux:mppart2:part2lo , mpmux:mppart3:part3lo , mpmux:mppart4:part4lo , mpmux:mppart5:part5lo , mpmux:mppart6:part6lo 
 lo : rsft31_63i_32o : input
Connects up to:rshifter:fpu_dp_cells_rshift:low 
 lo : rsh16_33 : input
Connects down to:mx16_2:mx16_2_28:i15 , mx16_2:mx16_2_26:i15 , mx16_2:mx16_2_26:i14 , mx16_2:mx16_2_24:i15 , mx16_2:mx16_2_24:i14 , mx16_2:mx16_2_24:i13 , mx16_2:mx16_2_22:i15 , mx16_2:mx16_2_22:i14 , mx16_2:mx16_2_22:i13 , mx16_2:mx16_2_22:i12 , mx16_2:mx16_2_20:i15 , mx16_2:mx16_2_20:i14 , mx16_2:mx16_2_20:i13 , mx16_2:mx16_2_20:i12 , mx16_2:mx16_2_20:i11 , mx16_2:mx16_2_18:i15 , mx16_2:mx16_2_18:i14 , mx16_2:mx16_2_18:i13 , mx16_2:mx16_2_18:i12 , mx16_2:mx16_2_18:i11 , mx16_2:mx16_2_18:i10 , mx16_2:mx16_2_16:i15 , mx16_2:mx16_2_16:i14 , mx16_2:mx16_2_16:i13 , mx16_2:mx16_2_16:i12 , mx16_2:mx16_2_16:i11 , mx16_2:mx16_2_16:i10 , mx16_2:mx16_2_16:i9 , mx16_2:mx16_2_14:i15 , mx16_2:mx16_2_14:i14 , mx16_2:mx16_2_14:i13 , mx16_2:mx16_2_14:i12 , mx16_2:mx16_2_14:i11 , mx16_2:mx16_2_14:i10 , mx16_2:mx16_2_14:i9 , mx16_2:mx16_2_14:i8 , mx16_2:mx16_2_12:i15 , mx16_2:mx16_2_12:i14 , mx16_2:mx16_2_12:i13 , mx16_2:mx16_2_12:i12 , mx16_2:mx16_2_12:i11 , mx16_2:mx16_2_12:i10 , mx16_2:mx16_2_12:i9 , mx16_2:mx16_2_12:i8 , mx16_2:mx16_2_12:i7 , mx16_2:mx16_2_10:i15 , mx16_2:mx16_2_10:i14 , mx16_2:mx16_2_10:i13 , mx16_2:mx16_2_10:i12 , mx16_2:mx16_2_10:i11 , mx16_2:mx16_2_10:i10 , mx16_2:mx16_2_10:i9 , mx16_2:mx16_2_10:i8 , mx16_2:mx16_2_10:i7 , mx16_2:mx16_2_10:i6 , mx16_2:mx16_2_08:i15 , mx16_2:mx16_2_08:i14 , mx16_2:mx16_2_08:i13 , mx16_2:mx16_2_08:i12 , mx16_2:mx16_2_08:i11 , mx16_2:mx16_2_08:i10 , mx16_2:mx16_2_08:i9 , mx16_2:mx16_2_08:i8 , mx16_2:mx16_2_08:i7 , mx16_2:mx16_2_08:i6 , mx16_2:mx16_2_08:i5 , mx16_2:mx16_2_06:i15 , mx16_2:mx16_2_06:i14 , mx16_2:mx16_2_06:i13 , mx16_2:mx16_2_06:i12 , mx16_2:mx16_2_06:i11 , mx16_2:mx16_2_06:i10 , mx16_2:mx16_2_06:i9 , mx16_2:mx16_2_06:i8 , mx16_2:mx16_2_06:i7 , mx16_2:mx16_2_06:i6 , mx16_2:mx16_2_06:i5 , mx16_2:mx16_2_06:i4 , mx16_2:mx16_2_04:i15 , mx16_2:mx16_2_04:i14 , mx16_2:mx16_2_04:i13 , mx16_2:mx16_2_04:i12 , mx16_2:mx16_2_04:i11 , mx16_2:mx16_2_04:i10 , mx16_2:mx16_2_04:i9 , mx16_2:mx16_2_04:i8 , mx16_2:mx16_2_04:i7 , mx16_2:mx16_2_04:i6 , mx16_2:mx16_2_04:i5 , mx16_2:mx16_2_04:i4 , mx16_2:mx16_2_04:i3 , mx16_2:mx16_2_02:i15 , mx16_2:mx16_2_02:i14 , mx16_2:mx16_2_02:i13 , mx16_2:mx16_2_02:i12 , mx16_2:mx16_2_02:i11 , mx16_2:mx16_2_02:i10 , mx16_2:mx16_2_02:i9 , mx16_2:mx16_2_02:i8 , mx16_2:mx16_2_02:i7 , mx16_2:mx16_2_02:i6 , mx16_2:mx16_2_02:i5 , mx16_2:mx16_2_02:i4 , mx16_2:mx16_2_02:i3 , mx16_2:mx16_2_02:i2 , mx16_2:mx16_2_00:i15 , mx16_2:mx16_2_00:i14 , mx16_2:mx16_2_00:i13 , mx16_2:mx16_2_00:i12 , mx16_2:mx16_2_00:i11 , mx16_2:mx16_2_00:i10 , mx16_2:mx16_2_00:i9 , mx16_2:mx16_2_00:i8 , mx16_2:mx16_2_00:i7 , mx16_2:mx16_2_00:i6 , mx16_2:mx16_2_00:i5 , mx16_2:mx16_2_00:i4 , mx16_2:mx16_2_00:i3 , mx16_2:mx16_2_00:i2 , mx16_2:mx16_2_00:i1 
Connects up to:imdr_dpath:rsh16_33_b:rb 
 loadd : incmod : wire
Connects down to:mj_s_mux2_d_32:loadd_mux:mx_out , mj_s_mux4_d_32:a0incmux_0:in0 , mj_s_mux4_d_32:a0incmux_0:in1 , mj_s_mux4_d_32:a0incmux_1:in0 , mj_s_mux4_d_32:a0incmux_1:in1 
 loaddp : incmod : wire
Connects down to:cla_adder_32:looadd:sum , mj_s_mux2_d_32:loadd_mux:in0 
 loadd_cin : incmod : wire
Connects down to:inc_decode:incdec:loadd_cin , cla_adder_32:looadd:cin 
 loadd_cin : inc_decode : output
Connects up to:incmod:incdec:loadd_cin 
 load_buffer_mux_out : ex_dpath : wire
Connects down to:mux2_32:load_buffer_mux:out , ff_se_32:dcu_data_reg:din 
 load_buffer_mux_out_0 : ex : wire
Connects down to:ex_dpath:ex_dpath:load_buffer_mux_out_0 
 load_buffer_mux_out_0 : ex_dpath : output
Connects up to:ex:ex_dpath:load_buffer_mux_out_0 
 load_buffer_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:load_buffer_mux_sel , ex_dpath:ex_dpath:load_buffer_mux_sel 
 load_buffer_mux_sel : ex_ctl : output
Connects up to:ex:ex_ctl:load_buffer_mux_sel 
 load_buffer_mux_sel : ex_dpath : input
Connects down to:mux2_32:load_buffer_mux:sel 
Connects up to:ex:ex_dpath:load_buffer_mux_sel 
 load_buffer_reg_out : ex_dpath : wire
Connects down to:ff_se_32:load_buffer_reg:out , mux2_32:load_buffer_mux:in1 
 load_byte : ex_ctl : wire
 load_byte_index : ex_ctl : wire
 load_c : ex : output
Connects down to:ex_ctl:ex_ctl:all_load_c 
Connects up to:iu:ex:load_c 
 load_c : iu : wire
Connects down to:ex:ex:load_c , pipe:pipe:load_c 
 load_c : pipe : input
Connects down to:pipe_cntl:pipe_cntl:load_c 
Connects up to:iu:pipe:load_c 
 load_c : pipe_cntl : input
Connects up to:pipe:pipe_cntl:load_c 
 load_c : smu_ctl : wire
Connects down to:ff_sre:load_c_flop:out , ff_sr:load_w_flop:din 
 load_char : ex_ctl : wire
 load_char_index : ex_ctl : wire
 load_char_oe : ex_ctl : wire
 load_data_c : ex_dpath : wire
Connects down to:mux3_32:load_data_c_mux:out , ff_se_32:load_buffer_reg:din , mux2_32:load_buffer_mux:in0 
 load_data_c_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:load_data_c_mux_sel , ex_dpath:ex_dpath:load_data_c_mux_sel 
 load_data_c_mux_sel : ex_ctl : output
Connects down to:ff_sre_3:load_data_mux_sel_reg:out 
Connects up to:ex:ex_ctl:load_data_c_mux_sel 
 load_data_c_mux_sel : ex_dpath : input
Connects down to:mux3_32:load_data_c_mux:sel 
Connects up to:ex:ex_dpath:load_data_c_mux_sel 
 load_data_mux_sel_e : ex_ctl : wire
Connects down to:ff_sre_3:load_data_mux_sel_e_reg:out , ff_sre_3:load_data_mux_sel_reg:din 
 load_data_mux_sel_r : ex_ctl : wire
Connects down to:ff_sre_3:load_data_mux_sel_e_reg:din 
 load_short : ex_ctl : wire
 load_short_index : ex_ctl : wire
 load_short_oe : ex_ctl : wire
 load_store_c : ex_ctl : wire
Connects down to:ff_sre:load_store_c_reg:out 
 load_store_e : ex_ctl : wire
Connects down to:ff_sre:load_store_c_reg:din 
 load_ubyte : ex_ctl : wire
 load_ubyte_index : ex_ctl : wire
 load_use : pipe_cntl : wire
 load_w : monitor : wire
Connects down to:smu_monitor:smu_monitor:load_w 
 load_w : smu_ctl : wire
Connects down to:ff_sr:load_w_flop:out 
 load_w : smu_monitor : input
Connects up to:monitor:smu_monitor:smu , monitor:smu_monitor:load_w , monitor:smu_monitor:smu_ctl 
 load_word : ex_ctl : wire
 load_word_index : ex_ctl : wire
 load_word_oe : ex_ctl : wire
 localnegi : mult_array : wire
Connects down to:signgen:signgeneration:localnegi , addnegi:addnegi1:ai , tree34:treerow6:ai 
 localnegi : signgen : output
Connects up to:mult_array:signgeneration:localnegi 
 lock0_cache : ex : wire
Connects down to:ex_ctl:ex_ctl:lock0_cache , ex_regs:ex_regs:lock0_cache 
 lock0_cache : ex_ctl : output
Connects up to:ex:ex_ctl:lock0_cache 
 lock0_cache : ex_regs : input
Connects down to:mux2:lc0_cacheon_din_mux:sel , mux2:lc0_cacheon_din_mux:sel 
Connects up to:ex:ex_regs:lock0_cache 
 lock0_enter : ex_ctl : wire
 lock0_exit : ex_ctl : wire
 lock0_overflow : ex_ctl : wire
 lock0_release : ex_ctl : wire
 lock0_uncache : ex : wire
Connects down to:ex_ctl:ex_ctl:lock0_uncache , ex_regs:ex_regs:lock0_uncache 
 lock0_uncache : ex_ctl : output
Connects up to:ex:ex_ctl:lock0_uncache 
 lock0_uncache : ex_regs : input
Connects down to:ff_sre_30:lockaddr0_reg:reset_l 
Connects up to:ex:ex_regs:lock0_uncache 
 lock0_underflow : ex_ctl : wire
 lock1_cache : ex : wire
Connects down to:ex_ctl:ex_ctl:lock1_cache , ex_regs:ex_regs:lock1_cache 
 lock1_cache : ex_ctl : output
Connects up to:ex:ex_ctl:lock1_cache 
 lock1_cache : ex_regs : input
Connects down to:mux2:lc1_cacheon_din_mux:sel , mux2:lc1_cacheon_din_mux:sel 
Connects up to:ex:ex_regs:lock1_cache 
 lock1_enter : ex_ctl : wire
 lock1_exit : ex_ctl : wire
 lock1_overflow : ex_ctl : wire
 lock1_release : ex_ctl : wire
 lock1_uncache : ex : wire
Connects down to:ex_ctl:ex_ctl:lock1_uncache , ex_regs:ex_regs:lock1_uncache 
 lock1_uncache : ex_ctl : output
Connects up to:ex:ex_ctl:lock1_uncache 
 lock1_uncache : ex_regs : input
Connects down to:ff_sre_30:lockaddr1_reg:reset_l 
Connects up to:ex:ex_regs:lock1_uncache 
 lock1_underflow : ex_ctl : wire
 lockaddr0 : display_picoJavaII : reg
 lockaddr0_out : ex_regs : wire
Connects down to:ff_sre_30:lockaddr0_reg:out , mux21_32:reg_rd_mux:in10 , ff_s_32:lockaddr0_w_reg:din , compare_zero_32:la0_null_cmp:in , comp_eq_32:la0_cmp:in1 
 lockaddr0_w : ex_regs : wire
Connects down to:ff_s_32:lockaddr0_w_reg:out 
 lockaddr1 : display_picoJavaII : reg
 lockaddr1_out : ex_regs : wire
Connects down to:ff_sre_30:lockaddr1_reg:out , mux21_32:reg_rd_mux:in11 , ff_s_32:lockaddr1_w_reg:din , compare_zero_32:la1_null_cmp:in , comp_eq_32:la1_cmp:in1 
 lockaddr1_w : ex_regs : wire
Connects down to:ff_s_32:lockaddr1_w_reg:out 
 lockbit : ex_ctl : input
Connects up to:ex:ex_ctl:dcu_data_w 
 lockcount0 : display_picoJavaII : reg
 lockcount0_out : ex_regs : wire
Connects down to:ff_sre:lockcount0_cacheon_reg:out , ff_se:lockcount0_lockwant_reg:out , ff_se_8:lockcount0_count_reg:out , mux21_32:reg_rd_mux:in8 , ff_s_32:lockcount0_w_reg:din , cmp_eq_8:lc0_cmp:in1 , cla_adder_8:lc0_p1_adder:in1 , cla_adder_8:lc0_m1_adder:in1 
 lockcount0_w : ex_regs : wire
Connects down to:ff_s_32:lockcount0_w_reg:out 
 lockcount1 : display_picoJavaII : reg
 lockcount1_out : ex_regs : wire
Connects down to:ff_sre:lockcount1_cacheon_reg:out , ff_se:lockcount1_lockwant_reg:out , ff_se_8:lockcount1_count_reg:out , mux21_32:reg_rd_mux:in9 , ff_s_32:lockcount1_w_reg:din , cmp_eq_8:lc1_cmp:in1 , cla_adder_8:lc1_p1_adder:in1 , cla_adder_8:lc1_m1_adder:in1 
 lockcount1_w : ex_regs : wire
Connects down to:ff_s_32:lockcount1_w_reg:out 
 lockwant0 : ex : wire
Connects down to:ex_ctl:ex_ctl:lockwant0 , ex_regs:ex_regs:lockwant0 
 lockwant0 : ex_ctl : input
Connects up to:ex:ex_ctl:lockwant0 
 lockwant0 : ex_regs : output
Connects up to:ex:ex_regs:lockwant0 
 lockwant1 : ex : wire
Connects down to:ex_ctl:ex_ctl:lockwant1 , ex_regs:ex_regs:lockwant1 
 lockwant1 : ex_ctl : input
Connects up to:ex:ex_ctl:lockwant1 
 lockwant1 : ex_regs : output
Connects up to:ex:ex_regs:lockwant1 
 lock_count_overflow_e : ex : output
Connects down to:ex_ctl:ex_ctl:lock_count_overflow_e 
Connects up to:iu:ex:lock_trap_e 
 lock_count_overflow_e : ex_ctl : output
Connects up to:ex:ex_ctl:lock_count_overflow_e 
 lock_enter_miss_e : ex : output
Connects down to:ex_ctl:ex_ctl:lock_enter_miss_e 
Connects up to:iu:ex:lock_trap_e 
 lock_enter_miss_e : ex_ctl : output
Connects up to:ex:ex_ctl:lock_enter_miss_e 
 lock_enter_trap : trap : wire
 lock_enter_trap_c : trap : wire
 lock_exit_miss_e : ex : output
Connects down to:ex_ctl:ex_ctl:lock_exit_miss_e 
Connects up to:iu:ex:lock_trap_e 
 lock_exit_miss_e : ex_ctl : output
Connects up to:ex:ex_ctl:lock_exit_miss_e 
 lock_exit_trap : trap : wire
 lock_exit_trap_c : trap : wire
 lock_miss_valid : ex_ctl : wire
 lock_ov_trap : trap : wire
 lock_ov_trap_c : trap : wire
 lock_release_e : ex : output
Connects down to:ex_ctl:ex_ctl:lock_release_e 
Connects up to:iu:ex:lock_trap_e 
 lock_release_e : ex_ctl : output
Connects up to:ex:ex_ctl:lock_release_e 
 lock_release_trap : trap : wire
 lock_release_trap_c : trap : wire
 lock_trap_c : trap : wire
Connects down to:ff_sre_4:lock_trap_reg:out 
 lock_trap_e : iu : wire
Connects down to:ex:ex:lock_count_overflow_e , ex:ex:lock_enter_miss_e , ex:ex:lock_exit_miss_e , ex:ex:lock_release_e , trap:trap:lock_trap_e 
 lock_trap_e : trap : input
Connects down to:ff_sre_4:lock_trap_reg:din 
Connects up to:iu:trap:lock_trap_e 
 long_out : code_seq_cntl : wire
Connects down to:fpu_dec:fpud:long_out , mj_s_mux2_d_6:fpumux:in0 , mj_s_ff_snre_d_6:conreg:out 
 long_out : fpu_dec : input
Connects up to:code_seq_cntl:fpud:long_out 
 long_outp : code_seq_cntl : wire
Connects down to:opcode_dec:d8:long_outp , mj_s_mux2_d_6:fpumux:in1 
 long_outp : opcode_dec : output
Connects up to:code_seq_cntl:d8:long_outp 
 lookupswitch : ex_ctl : wire
 lor : ex_ctl : wire
 lor : rs1_dec : reg
 low : lshift : input
Connects down to:lsft31_63i_32o:f_dpcl_lshift:lo 
Connects up to:prils_dp:lsh:m0out 
 low : rshifter : input
Connects down to:rsft31_63i_32o:fpu_dp_cells_rshift:lo 
Connects up to:rsadd_dp:rshift1:r0out 
 lowcarry : div_decode : input
Connects up to:incmod:divdec:lowcarry 
 lowcarry : incmod : wire
Connects down to:div_decode:divdec:lowcarry , cla_adder_32:looadd:cout , mj_s_mux2_d_32:pmd_temp0_mux:sel , mj_s_mux2_d_32:pmd_temp2_mux:sel 
 low_mark : monitor : wire
Connects down to:smu_monitor:smu_monitor:low_mark 
 low_mark : smu : input
Connects down to:smu_ctl:smu_ctl:low_mark 
Connects up to:cpu:smu:iu_psr 
 low_mark : smu_ctl : input
Connects down to:comp30_6:fill_comp:operand2 
Connects up to:smu:smu_ctl:low_mark 
 low_mark : smu_monitor : input
Connects up to:monitor:smu_monitor:low_mark , monitor:smu_monitor:smu , monitor:smu_monitor:smu_ctl 
 low_we_ : iram : wire (used in @negedge)
 lo_sel : multmod_dp : wire
Connects down to:mj_s_ff_snre_d_18:multdecout_moutselcntl:out , mj_s_mux3_d_32:sinlo_mux:sel , mj_s_mux3_d_32:cinlo_mux:sel , mj_s_mux3_d:stimux:sel , mj_s_mux3_d:negselmux:sel , mj_s_mux3_d:acimux:sel , mj_s_mux3_d:ecimux:sel 
 lo_sel : mult_dec : reg
 lrem : ex_ctl : wire
 lreturn : ex_ctl : wire
 lru_bit : dcudp_cntl : wire
Connects down to:mux5:dcu_set_sel_mux:in4 
 lru_bit : wrbuf_cntl : input
Connects up to:dcctl:wrbuf_cntl:dtg_stat_out 
 ls : comp_gle_32 : output
Connects down to:cmp3s_32_leg:i_cmp3s_32_leg:a_ltn_b 
 lsa : lsft31_63i_32o : input
Connects up to:lshift:f_dpcl_lshift:shifta 
 lsdprec : prils : wire
Connects down to:prils_cntl:i_prils_cntl:lsdprec , prils_dp:i_prils_dp:lsdprec 
 lsdprec : prils_cntl : output
Connects up to:prils:i_prils_cntl:lsdprec 
 lsdprec : prils_dp : input
Connects down to:prils_round_dec:ls2:prec 
Connects up to:prils:i_prils_dp:lsdprec 
 lsf_out : lsft31_63i_32o : output
Connects up to:lshift:f_dpcl_lshift:out 
 lshl : ex_ctl : wire
 lshl : rs1_dec : reg
 lshr : ex_ctl : wire
 lshr : rs1_dec : reg
 lsout : fpu : wire
Connects down to:prils:prif:lsout , mantissa:man:lsout 
 lsout : mantissa : input
Connects down to:mantissa_dp:i_mantissa_dp:lsout 
Connects up to:fpu:man:lsout 
 lsout : mantissa_dp : input
Connects down to:mj_s_mux8_d_32:na1:in2 , mj_s_mux6_d_32:na0:in2 
Connects up to:mantissa:i_mantissa_dp:lsout 
 lsout : prils : output
Connects down to:prils_dp:i_prils_dp:lsout 
Connects up to:fpu:prif:lsout 
 lsout : prils_dp : output
Connects down to:mj_s_mux2_d_32:lsmux:mx_out 
Connects up to:prils:i_prils_dp:lsout 
 lsoutp : prils_dp : wire
Connects down to:lshift:lsh:out , prils_round_dec:ls2:in , mj_s_mux2_d_32:lsmux:in0 
 lsround : fpu : wire
Connects down to:rsadd:rsa:lsround , prils:prif:lsround 
 lsround : incin_dec : input
Connects up to:rsadd_cntl:id0:lsround 
 lsround : prils : output
Connects down to:prils_dp:i_prils_dp:lsround 
Connects up to:fpu:prif:lsround 
 lsround : prils_dp : output
Connects down to:prils_round_dec:ls2:roundout 
Connects up to:prils:i_prils_dp:lsround 
 lsround : rsadd : input
Connects down to:rsadd_cntl:p_rsadd_cntl:lsround 
Connects up to:fpu:rsa:lsround 
 lsround : rsadd_cntl : input
Connects down to:incin_dec:id0:lsround 
Connects up to:rsadd:p_rsadd_cntl:lsround 
 lstore : ex_ctl : wire
 lstore : rs1_dec : reg
 lstore : rsd_dec : wire
 lstore_0 : ex_ctl : wire
 lstore_0 : rs1_dec : reg
 lstore_1 : ex_ctl : wire
 lstore_1 : rs1_dec : reg
 lstore_1 : rsd_dec : wire
 lstore_2 : ex_ctl : wire
 lstore_2 : rs1_dec : reg
 lstore_2 : rsd_dec : wire
 lstore_3 : ex_ctl : wire
 lstore_3 : rs1_dec : reg
 lstore_3 : rsd_dec : wire
 lsub : ex_ctl : wire
 lsub : rs1_dec : reg
 lsw_in : shift_64 : input
Connects up to:ex_dpath:dpath_shifter:shifter_src2_mux_out 
 lt : cmp_32 : output
Connects down to:cmp_legs_32:i_cmp_32:lt 
Connects up to:ex_regs:oplim_cmp:oplim_lt , ex_dpath:dpath_cmp:cmp_lt_e 
 lt : cmp_legs_32 : output
Connects down to:mj_h_mux2_3:res_mux:mx_out 
Connects up to:cmp_32:i_cmp_32:lt 
 lt : comp_ge_32 : wire
Connects down to:cmp32_ks_lt:i_comp_ge_32:a_ltn_b 
 lt : ucmp_16 : output
Connects down to:cmp3s_32_leg:i_cmp3s_32_leg:a_gtn_b 
Connects up to:ex_regs:range2_h_cmp1:range2_h_cmp1_lt , ex_regs:range2_l_cmp1:range2_l_cmp1_lt , ex_regs:range1_h_cmp2:range1_h_cmp2_lt , ex_regs:range1_l_cmp2:range1_l_cmp2_lt , ex_regs:range2_h_cmp2:range2_h_cmp2_lt , ex_regs:range2_l_cmp2:range2_l_cmp2_lt , ex_regs:range1_h_cmp1:range1_h_cmp1_lt , ex_regs:range1_l_cmp1:range1_l_cmp1_lt 
 lt1 : cmp_legs_32 : wire
Connects down to:cmp3s_32_leg:comp_32_leg:a_ltn_b , mj_h_mux2_3:res_mux:in1 
 lushr : ex_ctl : wire
 lushr : rs1_dec : reg
 lv1 : cmp16_e : wire
 lv2 : cmp16_e : wire
 lv3 : cmp16_e : wire
 lvars : ifu : input
Connects down to:comp_gr_32:scache_miss_comp:in1 
Connects up to:iu:ifu:lvars 
 lvars : iu : wire
Connects down to:ex:ex:vars_out , ifu:ifu:lvars , rcu:rcu:iu_lvars 
 lvars : monitor : wire
Connects down to:ucode_monitor:ucode_monitor:vars 
 lvars_acc_rs1 : ifu : wire
Connects down to:mux2:mux_lvacc_rs1:out , ff_sre:flop_lv_acc_rs1:din 
 lvars_acc_rs1 : main_dec : output
Connects down to:rs1_dec:rs1_dec:lvars_acc_rs1 
Connects up to:ifu:main_dec:lvars_acc_rs1_int 
 lvars_acc_rs1 : rcu_ctl : input
Connects up to:rcu:rcu_ctl:lvars_acc_rs1_r 
 lvars_acc_rs1 : rs1_dec : output
Connects up to:main_dec:rs1_dec:lvars_acc_rs1 
 lvars_acc_rs1_int : ifu : wire
Connects down to:main_dec:main_dec:lvars_acc_rs1 , mux2:mux_lvacc_rs1:in0 , mux2:mux_lvacc_rs2:in1 
 lvars_acc_rs1_r : ifu : output
Connects down to:ff_sre:flop_lv_acc_rs1:out 
Connects up to:iu:ifu:lvars_acc_rs1_r 
 lvars_acc_rs1_r : iu : wire
Connects down to:ifu:ifu:lvars_acc_rs1_r , rcu:rcu:lvars_acc_rs1_r 
 lvars_acc_rs1_r : rcu : input
Connects down to:rcu_ctl:rcu_ctl:lvars_acc_rs1 
Connects up to:iu:rcu:lvars_acc_rs1_r 
 lvars_acc_rs2 : ifu : wire
Connects down to:mux2:mux_lvacc_rs2:out , ff_sre:flop_lvars_acc_rs2:din 
 lvars_acc_rs2 : main_dec : output
Connects down to:mux4:mux_lv_acc_rs2:out 
Connects up to:ifu:main_dec:lvars_acc_rs2_int1 
 lvars_acc_rs2 : rcu_ctl : input
Connects up to:rcu:rcu_ctl:lvars_acc_rs2_r 
 lvars_acc_rs2 : rs2_dec : output
Connects up to:main_dec:rs2_dec_len1:lvars_acc_rs2_len1 , main_dec:rs2_dec_len2:lvars_acc_rs2_len2 , main_dec:rs2_dec_len3:lvars_acc_rs2_len3 
 lvars_acc_rs2_int : ifu : wire
Connects down to:mux2:mux_lvacc_rs1:in1 , mux2:mux_lvacc_rs2:in0 
 lvars_acc_rs2_int1 : ifu : wire
Connects down to:main_dec:main_dec:lvars_acc_rs2 
 lvars_acc_rs2_len1 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len1:lvars_acc_rs2 , mux4:mux_lv_acc_rs2:in1 
 lvars_acc_rs2_len2 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len2:lvars_acc_rs2 , mux4:mux_lv_acc_rs2:in2 
 lvars_acc_rs2_len3 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len3:lvars_acc_rs2 , mux4:mux_lv_acc_rs2:in3 
 lvars_acc_rs2_r : ifu : output
Connects down to:ff_sre:flop_lvars_acc_rs2:out 
Connects up to:iu:ifu:lvars_acc_rs2_r 
 lvars_acc_rs2_r : iu : wire
Connects down to:ifu:ifu:lvars_acc_rs2_r , rcu:rcu:lvars_acc_rs2_r 
 lvars_acc_rs2_r : rcu : input
Connects down to:rcu_ctl:rcu_ctl:lvars_acc_rs2 
Connects up to:iu:rcu:lvars_acc_rs2_r 
 lvars_minus_offset_rs1 : rcu_dpath : wire
Connects down to:cla_adder_32:sub_lvars_offset_rs1:sum , dec_32:dec_lvars_sec_cyc:in , mux5_32:mux_scache_addr_rs1:in3 , mux5_32:mux_bypass_scache_addr_rs1:in3 
 lvars_minus_offset_rs2 : rcu_dpath : wire
Connects down to:cla_adder_32:sub_lvars_offset_rs2:sum , mux5_32:mux_scache_addr_rs2:in4 , mux5_32:mux_bypass_scache_addr_rs2:in4 
 lvars_minus_offset_rsd : rcu_dpath : wire
Connects down to:cla_adder_32:sub_lvars_offset_rsd:sum , dec_32:dec_lvars_sec_cyc_rsd:in , mux3_32:mux_dest_addr:in2 
 lvars_offset_int : rcu_dpath : wire
Connects down to:dec_32:dec_lvars_sec_cyc:out , ff_se_32:flop_lvars_sec_cyc:din 
 lvars_offset_int_rsd : rcu_dpath : wire
Connects down to:dec_32:dec_lvars_sec_cyc_rsd:out , ff_se_32:flop_lvars_sec_cyc_rsd:din 
 lvars_offset_sec_cyc : rcu_dpath : wire
Connects down to:ff_se_32:flop_lvars_sec_cyc:out , mux5_32:mux_scache_addr_rs1:in4 , mux5_32:mux_bypass_scache_addr_rs1:in4 
 lvars_offset_sec_cyc_rsd : rcu_dpath : wire
Connects down to:ff_se_32:flop_lvars_sec_cyc_rsd:out , mux3_32:mux_dest_addr:in1 
 lvl_0 : lsft31_63i_32o : wire
 lvl_0 : rsft31_63i_32o : wire
 lvl_1 : lsft31_63i_32o : wire
 lvl_1 : rsft31_63i_32o : wire
 lvl_2 : lsft31_63i_32o : wire
 lvl_2 : rsft31_63i_32o : wire
 lvl_3 : lsft31_63i_32o : wire
 lvl_3 : rsft31_63i_32o : wire
 lvl_4 : lsft31_63i_32o : wire
 lvl_4 : rsft31_63i_32o : wire
 lvl_5 : lsft31_63i_32o : wire
 lvl_5 : rsft31_63i_32o : wire
 lv_rs1 : ifu : wire
Connects down to:mux2:mux_lv_rs1:out , ff_sre:flop_lv_rs1:din 
 lv_rs1 : main_dec : output
Connects down to:rs1_dec:rs1_dec:lv_rs1 
Connects up to:ifu:main_dec:lv_rs1_int 
 lv_rs1 : rs1_dec : output
Connects up to:main_dec:rs1_dec:lv_rs1 
 lv_rs1_int : ifu : wire
Connects down to:main_dec:main_dec:lv_rs1 , mux2:mux_lv_rs1:in0 , mux2:mux_lv_rs2:in1 
 lv_rs1_r : ifu : output
Connects down to:ff_sre:flop_lv_rs1:out 
Connects up to:iu:ifu:lv_rs1_r 
 lv_rs1_r : iu : wire
Connects down to:ifu:ifu:lv_rs1_r , rcu:rcu:lv_rs1_r 
 lv_rs1_r : rcu : input
Connects down to:rcu_ctl:rcu_ctl:lv_rs1_r 
Connects up to:iu:rcu:lv_rs1_r 
 lv_rs1_r : rcu_ctl : input
Connects up to:rcu:rcu_ctl:lv_rs1_r 
 lv_rs2 : ifu : wire
Connects down to:mux2:mux_lv_rs2:out , ff_sre:flop_lv_rs2:din 
 lv_rs2 : main_dec : output
Connects down to:mux4:mux_lv_rs2:out 
Connects up to:ifu:main_dec:lv_rs2_int1 
 lv_rs2 : rs2_dec : output
Connects up to:main_dec:rs2_dec_len1:lv_rs2_len1 , main_dec:rs2_dec_len2:lv_rs2_len2 , main_dec:rs2_dec_len3:lv_rs2_len3 
 lv_rs2_int : ifu : wire
Connects down to:mux2:mux_lv_rs1:in1 , mux2:mux_lv_rs2:in0 
 lv_rs2_int1 : ifu : wire
Connects down to:main_dec:main_dec:lv_rs2 
 lv_rs2_len1 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len1:lv_rs2 , mux4:mux_lv_rs2:in1 
 lv_rs2_len2 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len2:lv_rs2 , mux4:mux_lv_rs2:in2 
 lv_rs2_len3 : main_dec : wire
Connects down to:rs2_dec:rs2_dec_len3:lv_rs2 , mux4:mux_lv_rs2:in3 
 lv_rs2_r : ifu : output
Connects down to:ff_sre:flop_lv_rs2:out 
Connects up to:iu:ifu:lv_rs2_r 
 lv_rs2_r : iu : wire
Connects down to:ifu:ifu:lv_rs2_r , rcu:rcu:lv_rs2_r 
 lv_rs2_r : rcu : input
Connects down to:rcu_ctl:rcu_ctl:lv_rs2_r 
Connects up to:iu:rcu:lv_rs2_r 
 lv_rs2_r : rcu_ctl : input
Connects up to:rcu:rcu_ctl:lv_rs2_r 
 lxor : ex_ctl : wire
 lxor : rs1_dec : reg
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