/****************************************************************
 ---------------------------------------------------------------
     Copyright 1999 Sun Microsystems, Inc., 901 San Antonio
     Road, Palo Alto, CA 94303, U.S.A.  All Rights Reserved.
     The contents of this file are subject to the current
     version of the Sun Community Source License, picoJava-II
     Core ("the License").  You may not use this file except
     in compliance with the License.  You may obtain a copy
     of the License by searching for "Sun Community Source
     License" on the World Wide Web at http://www.sun.com.
     See the License for the rights, obligations, and
     limitations governing use of the contents of this file.

     Sun, Sun Microsystems, the Sun logo, and all Sun-based
     trademarks and logos, Java, picoJava, and all Java-based
     trademarks and logos are trademarks or registered trademarks 
     of Sun Microsystems, Inc. in the United States and other
     countries.
 ----------------------------------------------------------------
******************************************************************/


module ex_ctl(

// Input from IU
	inst_valid,
	iu_smiss,	
	sc_dcache_req,
	lduse_bypass,
	first_cyc_r,
	first_cyc_e,
	second_cyc_r,
	hold_e,
	hold_c,
	iu_addr_e,
	zero_addr_e,
	iu_addr_c,
	reissue_c,
	kill_inst_e,
	iu_trap_r,
	iu_trap_c,
	iu_data_vld,
	icu_data_vld,
	sc_data_vld,
	rs1_bypass_mux_out,
	pj_resume,
	trap_in_progress,

// Output to IU
	ucode_busy_e,
	wr_optop_e,
	iu_sbase_we,
	ret_optop_update,
	iu_brtaken_e,
	branch_taken_e,
	priv_inst_r,
	illegal_op_r,
	mis_align_c,
	emulated_trap_r,
	opcode_1_op_c,
	soft_trap_r,
	fpu_op_r,
	async_error,
	mem_prot_error_c,
	data_brk1_c,
	data_brk2_c,
	inst_brk1_r,
	inst_brk2_r,
	lock_count_overflow_e,
	lock_enter_miss_e,
	lock_exit_miss_e,
	lock_release_e,
	null_ptr_exception_e,
	priv_powerdown_e,
	priv_reset_e,
	all_load_c,
	icu_diag_ld_c,
	zero_trap_e,
	iu_bypass_rs1_e,
	iu_bypass_rs2_e,

// Output to DCU and ICU
	iu_inst_e,
	iu_dcu_flush_e,
	iu_icu_flush_e, 
	iu_zero_e,
	iu_special_e,
	iu_d_diag_e,
	iu_i_diag_e,

// Input from IFU
	opcode_1_op_r,
	opcode_2_op_r,
	valid_op_r,

// Input from ucode
	ucode_done,
	ucode_reg_wr,
	ucode_reg_rd,
	ucode_dcu_req,
	alu_adder_fn,
	mem_adder_fn,

// Input from E stage
	cmp_gt_e,
	cmp_eq_e,
	cmp_lt_e,
	null_objref_e,
	carry_out_e,
	psr_cac,
	psr_ace,
	psr_dce,
	psr_ice,
	psr_fle,
	psr_su,
	psr_drt,
	brk12c_brkm2,
	brk12c_brkm1,
	brk12c_subk2,
	brk12c_srcbk2,
	brk12c_brken2,
	brk12c_subk1,
	brk12c_srcbk1,
	brk12c_brken1,
	smu_ld,
	smu_st,
	range1_l_cmp1_lt,
	range1_h_cmp1_gt,
	range1_h_cmp1_eq,
	range2_l_cmp1_lt,
	range2_h_cmp1_gt,
	range2_h_cmp1_eq,
	range1_l_cmp2_lt,
	range1_h_cmp2_gt,
	range1_h_cmp2_eq,
	range2_l_cmp2_lt,
	range2_h_cmp2_gt,
	range2_h_cmp2_eq,
	data_brk1_31_13_eq,
	data_brk1_11_4_eq,
	data_brk1_misc_eq,
	data_brk2_31_13_eq,
	data_brk2_11_4_eq,
	data_brk2_misc_eq,
	inst_brk1_31_13_eq,
	inst_brk1_11_4_eq,
	inst_brk1_misc_eq,
	inst_brk2_31_13_eq,
	inst_brk2_11_4_eq,
	inst_brk2_misc_eq,
	la0_hit,
	lc0_eq_255,
	lc0_eq_0,
	lc0_m1_eq_0,
	lockwant0,
	lc0_co_bit,
	la0_null_e,
	la1_hit,
	lc1_eq_255,
	lc1_eq_0,
	lc1_m1_eq_0,
	lockwant1,
	lc1_co_bit,
	la1_null_e,
	
/******************** monitor caching change  *****************/	
	lockbit,

// Output to ex_dpath and ex_regs
	
	lock0_cache,
	lock1_cache,
	lock0_uncache,
	lock1_uncache,
	carry_in_e,
	mul_e,
	div_e,
	rem_e,
	shift_dir_e,
	shift_sel,
	sign_e,
	shift_count_e,
	lc0_count_reg_we,
	lc1_count_reg_we,
	priv_update_optop,
	dcu_data_reg_we,

	bit_cvt_mux_sel,
	alu_out_mux_sel,
	adder2_src1_mux_sel,
	adder2_src2_mux_sel,
	iu_data_mux_sel,
	reg_rd_mux_sel,
	reg_wr_mux_sel,
	load_data_c_mux_sel,
	fpu_mux_sel,
	forward_w_sel_din,
	cmp_mux_sel,
	adder_src1_mux_sel,
	adder_src2_mux_sel,
	bit_mux_sel,
	cvt_mux_sel,
	shifter_src1_mux_sel,
	shifter_src2_mux_sel,
	shifter_word_sel,
	constant_mux_sel,
	iu_br_pc_mux_sel,
	offset_mux_sel,
	lc0_din_mux_sel,
	lc1_din_mux_sel,
	adder2_carry_in,
	wr_optop_mux_sel,
	load_buffer_mux_sel,
	monitorenter_e,

	      reset_l,
	      clk,
	      sm,
	      sin,
	      so
	      );

   // Input signals from IU
   input [2:0]  inst_valid;	// Valid bits for the pipe to keep
				// track of instructions 0=E, 1=C and 2=W
   input 	iu_smiss;	// Stack cache miss 
   input	lduse_bypass;	// Need to bypass data for lduse
   input 	sc_dcache_req;	// Stack cache miss request to DCU 
   input 	first_cyc_r;	// Signal for 1st cycle of long operations 
   input 	second_cyc_r;	// Signal for 2nd cycle of long operations   
   input 	hold_e;		// Signal to tell ex to hold in E stage	 
   input 	hold_c;		// Signal to tell ex to hold in C stage	 
   input 	reissue_c;	// Re-issue the same instruction
   input 	kill_inst_e;	// kill any dcu requests/priv writes
   input	iu_trap_r;	// Indicates a trap in R stage.building frame
   input	iu_trap_c;	// Indicates a trap occurred in C stage
   input 	iu_data_vld;	// DCU indicates valid data has been returned
   input	icu_data_vld;	// I$ diagnostic data is available.
   input 	sc_data_vld;	// Similar to above but it's caused by S$ miss
   input [30:28]iu_addr_e;	// Address bits 30-28 at E stage for NC and OE  
   input [29:28]zero_addr_e;	// Address bits 30-28 at E stage for NC and OE  
   input [1:0] 	iu_addr_c;	// Address bits 1-0 at C stage for alignment  
   input [7:0] 	opcode_1_op_r;	// 1st byte of the opcode
   input [7:0] 	opcode_2_op_r;	// 2nd byte of the opcode
   input 	valid_op_r;	// This indicates whether the opcode
				// is valid or not
   input [5:0] 	rs1_bypass_mux_out;	// To calculate shift_count_e
   input	pj_resume;	// PJ RESUME signal for break points
   input	trap_in_progress;	// Indicates trap status

   // Input from ucode
   input 	ucode_done;	// ucode is using all the muxes
   input [2:0] 	ucode_reg_wr;	// write ucode_porta to priv registers 
   input [2:0] 	ucode_reg_rd;	// Read priv registers to stack cache 
   input [1:0] 	ucode_dcu_req;	// Ucode dcu request 
   input [1:0] 	alu_adder_fn;	// Ucode using adder 
   input [1:0] 	mem_adder_fn;	// Ucode using mem adder 

   // Input from E stage
   input 	cmp_gt_e;		// GT output of dpath comparator
   input 	cmp_lt_e;		// LT output of dpath comparator
   input 	cmp_eq_e;		// EQ output of dpath comparator
   input 	null_objref_e;		// ucode_porta_mux_out (Rs1) == zero
   input 	carry_out_e;		// Carry output of dpath ALU adder
   input 	psr_cac;		// PSR.CAC bit
   input 	psr_ace;		// PSR.ACE bit
   input 	psr_dce;		// PSR.DCE bit
   input 	psr_ice;		// PSR.ICE bit
   input 	psr_fle;		// PSR.FLE bit
   input 	psr_su;			// PSR.SU  bit
   input 	psr_drt;		// PSR.DRT  bit
   input [6:0]	brk12c_brkm2;		// BRK12C.BRKM2 bits
   input [6:0]	brk12c_brkm1;		// BRK12C.BRKM1 bits
   input 	brk12c_subk2;		// BRK12C.SUBK2 bits
   input [1:0]	brk12c_srcbk2;		// BRK12C.SRCBK2 bits
   input 	brk12c_brken2;		// BRK12C.BRKEN2 bits
   input 	brk12c_subk1;		// BRK12C.SUBK1 bits
   input [1:0]	brk12c_srcbk1;		// BRK12C.SRCBK1 bits
   input 	brk12c_brken1;		// BRK12C.BRKEN1 bits
   input 	smu_ld;			// Input from cpu.v
   input 	smu_st;			// Input from cpu.v
   input 	range1_l_cmp1_lt;	// iu_addr_c < userrange1.userlow
   input 	range1_h_cmp1_gt;	// iu_addr_c > userrange1.userhigh
   input 	range1_h_cmp1_eq;	// iu_addr_c = userrange1.userhigh
   input 	range2_l_cmp1_lt;	// iu_addr_c < userrange2.userlow
   input 	range2_h_cmp1_gt;	// iu_addr_c > userrange2.userhigh
   input 	range2_h_cmp1_eq;	// iu_addr_c = userrange2.userhigh
   input 	range1_l_cmp2_lt;	// optop_c < userrange1.userlow
   input 	range1_h_cmp2_gt;	// optop_c > userrange1.userhigh
   input 	range1_h_cmp2_eq;	// optop_c = userrange1.userhigh
   input 	range2_l_cmp2_lt;	// optop_c < userrange2.userlow
   input 	range2_h_cmp2_gt;	// optop_c > userrange2.userhigh
   input 	range2_h_cmp2_eq;	// optop_c = userrange2.userhigh
   input 	data_brk1_31_13_eq;	// iu_addr_c[31:13] == brk1a[31:13]
   input 	data_brk1_11_4_eq;	// iu_addr_c[11:4]  == brk1a[11:4]
   input [4:0] 	data_brk1_misc_eq;	// iu_addr_c[12,3:0]== brk1a[12,3:0]
   input 	data_brk2_31_13_eq;	// iu_addr_c[31:13] == brk2a[31:13]
   input 	data_brk2_11_4_eq;	// iu_addr_c[11:4]  == brk2a[11:4]
   input [4:0] 	data_brk2_misc_eq;	// iu_addr_c[12,3:0]== brk2a[12,3:0]
   input 	inst_brk1_31_13_eq;	// pc_r[31:13] == brk1a[31:13]
   input 	inst_brk1_11_4_eq;	// pc_r[11:4]  == brk1a[11:4]
   input [4:0] 	inst_brk1_misc_eq;	// pc_r[12,3:0]== brk1a[12,3:0]
   input 	inst_brk2_31_13_eq;	// pc_r[31:13] == brk2a[31:13]
   input 	inst_brk2_11_4_eq;	// pc_r[11:4]  == brk2a[11:4]
   input [4:0] 	inst_brk2_misc_eq;	// pc_r[12,3:0]== brk2a[12,3:0]
   input 	la0_hit;		// 1 if lockaddr0 == objref in data_in
   input 	lc0_eq_255;		// 1 if lockcount0   == 255, 0 otherwise
   input 	lc0_eq_0;		// 1 if lockcount0   ==   0, 0 otherwise
   input 	lc0_m1_eq_0;		// 1 if lockcount0-1 ==   0, 0 otherwise
   input 	lockwant0;		// Bit 14 of lockcount0 register
   input 	lc0_co_bit;		// Bit 15 of lockcount0 register
   input        la0_null_e;		// 1 if lockaddr0 == 0, 0 otherwise
   input 	la1_hit;		// 1 if lockaddr1 == objref in data_in
   input 	lc1_eq_255;		// 1 if lockcount1   == 255, 0 otherwise
   input 	lc1_eq_0;		// 1 if lockcount1   ==   0, 0 otherwise
   input 	lc1_m1_eq_0;		// 1 if lockcount1-1 ==   0, 0 otherwise
   input 	lockwant1;		// Bit 14 of lockcount1 register
   input	lc1_co_bit;		// Bit 15 of lockcount0 register
   input        la1_null_e;		// 1 if lockaddr1 == 0, 0 otherwise
   input	lockbit;		// bit 0 of dcu_data_c	

  // Output from ex_decode.v
   output 	 illegal_op_r;		// Unused extended opcodes

   // Output signals to IU
   output	 ucode_busy_e;		// UCODE is busy
   output 	 wr_optop_e;		// Tell IU it is a write_optop
   output	 iu_sbase_we;		// Write enable signal to SMU, whenever there's 
					// wr_sbase  etc.
   output 	 ret_optop_update;	// Tell IU it is a write_optop due to return
   output 	 iu_brtaken_e;		// Tell IU if branch taken 
   output	 branch_taken_e;	// internal signal in IU
   output 	 priv_inst_r;		// Privileged instructions
   output 	 mis_align_c;		// Mis_aligned exception
   output 	 emulated_trap_r;	// Emulated trap
   output [7:0]  opcode_1_op_c;		// Opcode at C stage
   output 	 soft_trap_r;		// Soft_trap in R stage
   output 	 fpu_op_r;		// FPU opcode in R stage
   output 	 async_error;		// asynchronous_error due to smu access
   output 	 mem_prot_error_c;	// mem_protection_error  in C stage
   output 	 data_brk1_c;		// Data breakpoint1 exception in C stage
   output 	 data_brk2_c;		// Data breakpoint2 exception in C stage
   output 	 inst_brk1_r;		// Inst breakpoint1 exception in R stage
   output 	 inst_brk2_r;		// Inst breakpoint2 exception in R stage
   output 	 lock_count_overflow_e;	// LockCountOverFlowTrap in E stage
   output 	 lock_enter_miss_e;	// LockEnterMissTrap	 in E stage
   output 	 lock_exit_miss_e;	// LockExitMissTrap	 in E stage
   output 	 lock_release_e;	// LockReleaseTrap	 in E stage
   output 	 null_ptr_exception_e;	// runtime_NullPtrException in E stage
   output 	 priv_powerdown_e;	// prive_powerdown instruction in E stage 
   output 	 priv_reset_e;		// prive_reset instruction in E stage 
   output 	 all_load_c;		// There is a load in C stage
   output	 icu_diag_ld_c;		// ICU Diagnostic load in C stage
   output 	 zero_trap_e;		// Take zero_line e-trap in E stage 
   output 	 iu_bypass_rs1_e;	// RS1 need bypass 
   output 	 iu_bypass_rs2_e;	// RS2 need bypass 
   output	 first_cyc_e;		// First cycle in EStage for two cycle instn.

   // Output to DCU
   output [7:0]  iu_inst_e;		// [7] =  non allocating
					// [6] =  opposite endiannes
					// [5] =  signed
					// [4] =  noncacheable
					// [3] =  store
					// [2] =  load
					// [1:0] = size
   output 	 iu_zero_e;		// cache zero line 
   output	 iu_special_e;		// dcu related special inst in E
   output [3:0]  iu_d_diag_e;		// [3] =  Dcache RAm Write
					// [2] =  Dcache Ram Read
					// [1] =  DTag	Write
					// [0] =  Dtag	Read
   output [3:0]  iu_i_diag_e;		// [3] =  Icache RAm Write
					// [2] =  Icache Ram Read
					// [1] =  ITag	Write
					// [0] =  Itag	Read
   output [2:0]  iu_dcu_flush_e;	// Signal to DCU for cache_flush [2],
					// cache_index_flush [1] and 
					// cache_invaliddate [0] 

   // Output to ICU
   output 	 iu_icu_flush_e;	// Signal to ICU for cache_flush,
					// cache_index_flush and cache_invaliddate 

   // E stage control signals
   output	 lock0_cache;		// control signal to cache a lock in lock pair 0
   output	 lock1_cache;		// control signal to cache a lock in lock pair 1
   output	 lock0_uncache;		// control signal to uncache a lock in lock pair 0
   output	 lock1_uncache;		// control signal to uncache a lock in lock pair 1
   output 	 carry_in_e;		// carry_in bit to adder
   output 	 mul_e;			// IMDR:	 multiplication
   output 	 div_e;			// IMDR:	 division
   output 	 rem_e;			// IMDR:	 remainder
   output 	 shift_sel;		// Shifter:	 0: left, 1: right
   output 	 sign_e;		// Shifter & Converter: sign extension
   output [5:0]  shift_count_e;		// Shifter: # of bits to shift
   output 	 lc0_count_reg_we;	// Write enable of lockcount0_count_reg
					// in ex_regs
   output 	 lc1_count_reg_we;	// Write enable of lockcount1_count_reg
					// in ex_regs
   output 	 priv_update_optop;	// Indicates priv_update_optop in R
   output [1:0]	 dcu_data_reg_we;	// The load buffer register write enables


   output [1:0]  bit_cvt_mux_sel;	// 1: bit operator output
					// 0: converter output

   output [7:0]  alu_out_mux_sel;	// 7: constant_mux_out 
					// 6: imdr_data
					// 5: reg_rd_mux_out
					// 4: bit_cvt_mux_out
					// 3: shifter output
					// 2: adder output
					// 1: ucode_portc
					// 0: bypass
						 
   output  adder2_src1_mux_sel;	
						 
   output [3:0]  adder2_src2_mux_sel;	 // 0: ~u_m_adder_portb
   	 				 // 1: u_m_adder_portb
					 // 2: offset_e
					 // 3: zero
						 
   output [1:0]  iu_data_mux_sel;	 // 1: ucode_portc  
					 // 0: rs2_bypass_mux_out
						 
   output [20:0] reg_rd_mux_sel;	 // 20: 0x80000: SC_BOTTOM
					 // 19: 0x40000: HCR
					 // 18: 0x20000: VERSIONID
					 // 17: 0x10000: USERRANGE2
					 // 16: 0x08000: BRK12C
					 // 15: 0x04000: BRK2A
					 // 14: 0x02000: BRK1A
					 // 13: 0x01000: GC_CONFIG
					 // 12: 0x00800: USERRANGE1
					 // 11: 0x00400: LOCKADDR1
					 // 10: 0x00200: LOCKADDR0
					 // 9:	0x00100: LOCKCOUNT1
					 // 8:	0x00080: LOCKCOUNT0
					 // 7:	0x00040: TRAPBASE
					 // 6:	0x00020: PSR
					 // 5:	0x00010: CONST_POOL
					 // 4:	0x00008: OPLIM
					 // 3:	0x00004: OPTOP
					 // 2:	0x00002: FRAME
					 // 1:	0x00001: VARS
					 // 0:	0x00000: PC

   output [18:0]  reg_wr_mux_sel;	/* bit 18, 0x40000: SC_BOTTOM
					 * bit 17, 0x20000: USERRANGE2
					 * bit 16, 0x10000: BRK12C
					 * bit 15, 0x08000: BRK2A
					 * bit 14, 0x04000: BRK1A
					 * bit 13, 0x02000: GC_CONFIG
					 * bit 12, 0x01000: USERRANGE1
					 * bit 11, 0x00800: LOCKADDR1
					 * bit 10, 0x00400: LOCKADDR0
					 * bit  9, 0x00200: LOCKCOUNT1
					 * bit  8, 0x00100: LOCKCOUNT0
					 * bit  7, 0x00080: TRAPBASE
					 * bit  6, 0x00040: PSR
					 * bit  5, 0x00020: CONST_POOL
					 * bit  4, 0x00010: OPLIM
					 * bit  3, 0x00008: OPTOP
					 * bit  2, 0x00004: FRAME
					 * bit  1, 0x00002: VARS
					 * bit  0, 0x00001: PC
					 */
   output [2:0]  load_data_c_mux_sel;	// 2: icu_diag_data_c
					// 1: dcu_diag_data_c
					// 0: dcu_data


   output [1:0]  fpu_mux_sel;		// 1: fpu_data_e
					// 0: alu_out_e

   output [1:0]  forward_w_sel_din;// 1: output of dcu_hold register 
					// 0: alu_out_c_d1

   output [2:0]  cmp_mux_sel;		// 1: Rs1, zero
					// 0: ~Rs1, Rs2

   output [1:0]  adder_src1_mux_sel;	// 1: ~Rs1
					// 0: Rs1

   output [2:0]  adder_src2_mux_sel;	// 2: zero
					// 1: ~Rs2
					// 0: Rs2

   output [4:0]  bit_mux_sel;		// 4: rs1_bypass_mux_out with bit 31
					//    flipped to support fneg and dneg
					// 3: pc_r 
					// 2: xor
					// 1: and
					// 0: or

   output [4:0]  cvt_mux_sel;		// 4: i2s
					// 3: i2c
					// 2: i2b
					// 1: i2l
					// 0: sethi
   output 	 shift_dir_e;		// Shifter:	 0: left, 1: right

   output [4:0]  shifter_src1_mux_sel;	/* 16: rs2_bypass_mux_out_d1
					 *  8: {32{rs2_bypass_mux_out[31]}}
					 *  4: rs2_bypass_mux_out
					 *  2: rs1_bypass_mux_out
					 *  1: zero
					 */
   output [2:0]  shifter_src2_mux_sel;	/* 4: rs2_bypass_mux_out_d1
					 * 2: rs2_bypass_mux_out
					 * 1: zero
					 */
   output 	 shifter_word_sel;	// 1: MSW
					// 0: LSW

   output [2:0]  constant_mux_sel;	// 2:	1 -- gt
					// 1:	0 -- eq
					// 0: -1 -- lt

   output [2:0]  iu_br_pc_mux_sel;	// 2: ucode_porta_e
					// 1: pc_c
					// 0: adder2 output

   output [4:0]  offset_mux_sel;	/* 16: 32-bit offset for ld/st index
					 *  8: 16-bit offset for ld/st index
					 *  4:  8-bit offset for ld/st index
					 *  2: opcode_e (32-bit offset)
					 *  1: offset16 (16-bit offset)
					 */

   output [3:0]  lc0_din_mux_sel;	/* 4: lc0_p1
					 * 2: lc0_m1
					 * 1: data_in from priv_write_lockcount0
					 */
   output [3:0]  lc1_din_mux_sel;	/* 4: lc1_p1
					 * 2: lc1_m1
					 * 1: data_in from priv_write_lockcount1
					 */

   output	 adder2_carry_in;	// Carry input to the address adder

   output [1:0]  wr_optop_mux_sel;      // 1: vars_out
                                        // 0: ucode_porta_mux_out
   output [1:0]  load_buffer_mux_sel;	/* 2: load_buffer_reg_out (in state 2)
					 * 1: dcu_data_c (otherwise)
					 */

   // Miscellaneous global signals
   input 	 reset_l;
   input 	 clk;
   input 	 sm;			// Scan enable
   input 	 sin;			// Scan data input
   output 	 so;			// Scan data output

wire data_brk1_c_int, data_brk2_c_int;
wire nop,
  aconst_null,
  iconst_m1,
  iconst_0,
  iconst_1,
  iconst_2,
  iconst_3,
  iconst_4,
  iconst_5,
  lconst_0,
  lconst_1,
  fconst_0,
  fconst_1,
  fconst_2,
  dconst_0,
  dconst_1,
  bipush,
  sipush,
  ldc,
  ldc_w,
  ldc2_w,
  iload,
  lload,
  fload,
  dload,
  aload,
  iload_0,
  iload_1,
  iload_2,
  iload_3,
  lload_0,
  lload_1,
  lload_2,
  lload_3,
  fload_0,
  fload_1,
  fload_2,
  fload_3,
  dload_0,
  dload_1,
  dload_2,
  dload_3,
  aload_0,
  aload_1,
  aload_2,
  aload_3,
  iaload,
  laload,
  faload,
  daload,
  aaload,
  baload,
  caload,
  saload,
  istore,
  lstore,
  fstore,
  dstore,
  astore,
  istore_0,
  istore_1,
  istore_2,
  istore_3,
  lstore_0,
  lstore_1,
  lstore_2,
  lstore_3,
  fstore_0,
  fstore_1,
  fstore_2,
  fstore_3,
  dstore_0,
  dstore_1,
  dstore_2,
  dstore_3,
  astore_0,
  astore_1,
  astore_2,
  astore_3,
  aastore_quick,
  iastore,
  lastore,
  fastore,
  dastore,
  aastore,
  bastore,
  castore,
  sastore,
  pop,
  pop2,
  dup,
  dup_x1,
  dup_x2,
  dup2,
  dup2_x1,
  dup2_x2,
  swap,
  iadd,
  ladd,
  fadd,
  dadd,
  isub,
  lsub,
  fsub,
  dsub,
  imul,
  lmul,
  fmul,
  dmul,
  idiv,
  ldiv,
  fdiv,
  ddiv,
  irem,
  lrem,
  frem,
  drem,
  ineg,
  lneg,
  fneg,
  dneg,
  ishl,
  lshl,
  ishr,
  lshr,
  iushr,
  lushr,
  iand,
  land,
  ior,
  lor,
  ixor,
  lxor,
  iinc,
  i2l,
  i2f,
  i2d,
  l2i,
  l2f,
  l2d,
  f2i,
  f2l,
  f2d,
  d2i,
  d2l,
  d2f,
  int2byte,
  int2char,
  int2short,
  lcmp,
  fcmpl,
  fcmpg,
  dcmpl,
  dcmpg,
  ifeq,
  ifne,
  iflt,
  ifge,
  ifgt,
  ifle,
  if_icmpeq,
  if_icmpne,
  if_icmplt,
  if_icmpge,
  if_icmpgt,
  if_icmple,
  if_acmpeq,
  if_acmpne,
  goto,
  jsr,
  ret,
  tableswitch,
  lookupswitch,
  ireturn,
  lreturn,
  freturn,
  dreturn,
  areturn,
  return,
  getstatic,
  putstatic,
  getfield,
  putfield,
  invokevirtual,
  invokenonvirtual,
  invokestatic,
  invokeinterface,
  new,
  newarray,
  anewarray,
  arraylength,
  athrow,
  checkcast,
  instanceof,
  monitorenter,
  monitorexit,
  wide,
  multianewarray,
  ifnull,
  ifnonnull,
  goto_w,
  jsr_w,
  breakpoint,
  ldc_quick,
  ldc_w_quick,
  ldc2_w_quick,
  getfield_quick,
  putfield_quick,
  getfield2_quick,
  putfield2_quick,
  getstatic_quick,
  putstatic_quick,
  getstatic2_quick,
  putstatic2_quick,
  invokevirtual_quick,
  invokenonvirtual_quick,
  invokesuper_quick,
  invokestatic_quick,
  invokeinterface_quick,
  invokevirtualobject_quick,		// Not supported 
  invokeignored_quick,
  new_quick,
  anewarray_quick,
  multianewarray_quick,
  checkcast_quick,
  instanceof_quick,
  invokevirtual_quick_w,
  getfield_quick_w,
  putfield_quick_w,
  nonnull_quick,		// Not supported 
  agetfield_quick,
  aputfield_quick,
  agetstatic_quick,
  aputstatic_quick,
  aldc_quick,
  aldc_w_quick,
  exit_sync_method,
  sethi,
  load_word_index,
  load_short_index,
  load_char_index,
  load_byte_index,
  load_ubyte_index,
  store_word_index,
  nastore_word_index,
  store_short_index,
  store_byte_index,
  hardware ;

// Exented bytecodes
  wire	load_ubyte,
	load_byte,
	load_char,
	load_short,
	load_word,
	priv_ret_from_trap,
	priv_read_dcache_tag,
	priv_read_dcache_data,
	load_char_oe,
	load_short_oe,
	load_word_oe,
	return0,
	priv_read_icache_tag,
	priv_read_icache_data,
	ncload_ubyte,
	ncload_byte,
	ncload_char,
	ncload_short,
	ncload_word,
	iucmp,
	priv_powerdown,
	cache_invalidate,
	ncload_char_oe,
	ncload_short_oe,
	ncload_word_oe,
	return1,
	cache_flush,
	cache_index_flush,
	store_byte,
	store_short,
	store_word,
	soft_trap,
	priv_write_dcache_tag,
	priv_write_dcache_data,
	store_short_oe,
	store_word_oe,
	return2,
	priv_write_icache_tag,
	priv_write_icache_data,
	ncstore_byte,
	ncstore_short,
	ncstore_word,
	priv_reset,
	get_current_class,
	ncstore_short_oe,
	ncstore_word_oe,
	call,
	zero_line,
	read_pc,
	read_vars,
	read_frame,
	read_optop,
	priv_read_oplim,
	read_const_pool,
	priv_read_psr,
	priv_read_trapbase,
	priv_read_lockcount0,	
	priv_read_lockcount1,	
	priv_read_lockaddr0,
	priv_read_lockaddr1,
	priv_read_userrange1,
	priv_read_gc_config,
	priv_read_brk1a,
	priv_read_brk2a,
	priv_read_brk12c,
	priv_read_userrange2,
	priv_read_versionid,
	priv_read_hcr,
	priv_read_sc_bottom,
	read_global0,
	read_global1,
	read_global2,
	read_global3,
	write_pc,
	write_vars,
	write_frame,
	write_optop,
	priv_write_oplim,
	write_const_pool,
	priv_write_psr,
	priv_write_trapbase,
	priv_write_lockcount0,	
	priv_write_lockcount1,	
	priv_write_lockaddr0,
	priv_write_lockaddr1,
	priv_write_userrange1,
	priv_write_gc_config,
	priv_write_brk1a,
	priv_write_brk2a,
	priv_write_brk12c,
	priv_write_userrange2,
	priv_write_sc_bottom,
	write_global0,
	write_global1,
	write_global2,
	write_global3;

  wire	[255:0]		decodeout_1;	// Decode signals from JVM opcode[7:0]
  wire	[255:0]		decodeout_2;	// Decode signals from exented opcode[7:0]

  // R stage control signals
  wire monitorenter_r, monitorexit_r, carry_in_r;
  wire monitorenter_raw_e, monitorexit_raw_e, carry_in_raw_e;
  wire mul_r, div_r, rem_r, shift_sel_r, sign_r; 
  wire mul_raw_e, div_raw_e, rem_raw_e, shift_sel_raw; 
  wire sign_raw_e; 
  wire priv_reset_raw_e, priv_powerdown_raw_e;
  wire [1:0] bit_cvt_mux_sel_r;
  wire [7:0] alu_out_mux_sel_r; 
  wire [7:0] alu_out_mux_sel_raw_e; 
  wire adder2_src1_mux_sel_r;
  wire [1:0] iu_data_mux_sel_r;
  wire [4:0] offset_mux_sel_r;
  wire [20:0] reg_rd_mux_sel_r;
  wire [20:0] reg_rd_mux_sel_raw_e;
  wire [18:0] reg_wr_mux_sel_r;
  wire [18:0] reg_wr_mux_sel_raw_e;
  wire [18:0] reg_wr1_mux_sel;		/* reg_wr_mux_sel before qualified with
					 * inst_valid[0] and ~iu_trap_c
					 */
  wire [2:0] load_data_mux_sel_r;
  wire [2:0] load_data_mux_sel_e;
  wire [2:0] cmp_mux_sel_r;
  wire [1:0] adder_src1_mux_sel_r;
  wire [1:0] adder_src1_mux_sel_raw_e;
  wire       adder_src2_mux_sel_r;
  wire [4:0] bit_mux_sel_r;
  wire [4:0] cvt_mux_sel_r;  
  wire shift_dir_r, shift_dir_raw_e;
  wire [4:0] shifter_src1_mux_sel_r;
  wire [2:0] shifter_src2_mux_sel_r;
  wire all_load_c_raw, all_load_e;  // There is a load in W stage
  wire ucode_busy_r;
  wire[4:0] branch_qual;
  wire shifter_word_sel_r;
  wire ucode_busy_c;
  wire invalid_op_r;
  wire iu_bypass_rs1_r, iu_bypass_rs2_r;
  wire iu_bypass_rs1, iu_bypass_rs2;
  wire [1:0] forward_data_w_mux_sel_c;

  // Ucode signals
  wire	ucode_rd_psr_e;			// ucode_reg_rd[2:0] = 0x1
  wire	ucode_rd_vars_e;		// ucode_reg_rd[2:0] = 0x2
  wire	ucode_rd_frame_e;		// ucode_reg_rd[2:0] = 0x3
  wire	ucode_rd_const_p_e;		// ucode_reg_rd[2:0] = 0x4
  wire	ucode_rd_port_c_e;		// ucode_reg_rd[2:0] = 0x5
  wire	ucode_rd_dcache_e;		// ucode_reg_rd[2:0] = 0x6
  wire	ucode_rd_dcache_c;		// ucode_reg_rd[2:0] = 0x6 in C stage
  wire	ucode_rd_part_dcache_e;		// ucode_reg_rd[2:0] = 0x7
  wire	ucode_rd_part_dcache_c;		// ucode_reg_rd[2:0] = 0x7 in C stage
  wire	ucode_wr_pc_e;			// ucode_reg_wr[2:0] = 0x1
  wire	ucode_wr_vars_e;		// ucode_reg_wr[2:0] = 0x2
  wire	ucode_wr_frame_e;		// ucode_reg_wr[2:0] = 0x3
  wire	ucode_wr_const_p_e;		// ucode_reg_wr[2:0] = 0x4
  wire	ucode_wr_optop_e;		// ucode_reg_wr[2:0] = 0x5
  wire	ucode_wr_vars_optop_e;		// ucode_reg_wr[2:0] = 0x6
  wire	ucode_wr_psr_e;			// ucode_reg_wr[2:0] = 0x7

  // R stage control signals to IU 
  wire ucode_op_r;		// ucode opcodes
  wire [7:0] opcode_1_op_e;	// Opcode in E stage
  wire illegal_op_raw_r;	// Illegal instruction in R stage 

  // R stage control signals to DCU and IU
  wire wr_optop_r;		// Tell IU that OPTOP will be written 
  wire wr_optop_raw_e;		 
  wire [7:0] iu_inst_r;		
  wire data_brk1_e, data_brk2_e;
  wire [7:0] iu_inst_raw_e;		
  wire [7:0] iu_inst_raw;		
  wire [7:0] ucode_inst_e;		
  wire array_load_e;
  wire [1:0] iu_inst_e_mux_sel;
  wire iu_icu_flush_r;
  wire iu_icu_flush_raw_e;
  wire [2:0] iu_dcu_flush_r;
  wire [2:0] iu_dcu_flush_raw_e;
  wire iu_zero_r, iu_zero_raw_e;
  wire [3:0] iu_d_diag_r;
  wire [3:0] iu_i_diag_r;
  wire [3:0] iu_d_diag_raw_e;
  wire [3:0] iu_i_diag_raw_e;

  // E stage instruction signals
  wire ifeq_e, if_icmpeq_e, if_acmpeq_e, ifge_e, if_icmpge_e, ifle_e,ucode_st_e;
  wire if_icmple_e, ifnull_e, ifne_e, if_icmpne_e, if_acmpne_e;
  wire ifnonnull_e, ifgt_e, if_icmpgt_e, iflt_e, if_icmplt_e;
  wire goto_e, goto_w_e, jsr_e, jsr_w_e, ret_e, write_pc_e, all_return_e, all_return_r;
  wire baload_e,bastore_e,castore_e,caload_e,saload_e,sastore_e;
  wire ucode_read_reg_e, ret_optop_update_e;


   output       monitorenter_e;		// monitorenter
   wire       monitorexit_e;		// monitorexit