output [31:0] mx_out;
input         sel;
input  [31:0] in0 , in1 ;

wire   [31:0] sel_not, mux_sel;

assign sel_not = {32{~sel}};
assign mux_sel = {32{ sel}};
assign mx_out  = ~(mux_sel & in1 | sel_not & in0) ;

endmodule


module compare_lt_32(out,in0,in1);
 
 input  [31:0]  in0,in1;
 output         out;
 
/* assign out = (in0 < in1) ? 1'h1 : 1'h0; */

cmp32_ks_lt  i_compare_lt_32 (	.ai(in0),
				.bi(in1),
				.a_ltn_b(out)
				);
endmodule


module pri_encode(out,in);
// Leading zero output: if all 32 bits are zero output 32.
 
 input  [31:0] in;
 output  [5:0]  out;
 
lbd32 f_dpcl_lbd32(.zr_num(out),.di(in));
 
endmodule



module rshifter(rshiftout,high,low,stin,sticky,saout);
 
  input  [31:0] low;
  input  [30:0] high;
  input         stin;   // Input from prevoius STICKY
  input   [4:0] saout;  // Shift Amount.
 
  output [31:0] rshiftout;
  output        sticky;  // Or of all bits below the GBIT.
 
rsft31_63i_32o fpu_dp_cells_rshift(.rsf_out(rshiftout),.hi(high),.lo(low),
                 .stin(stin),.sticky(sticky),.rsa(saout), .gbit(), .nxstin());
 
endmodule


module lshift(out,high,low,shifta);
// performs the 32-bit Left Shift.
 
 input  [31:0]  high;
 input  [30:0]  low;  // high 31 bits of the m0out bus.
 input  [4:0]   shifta;
 output [31:0]  out;
 
lsft31_63i_32o f_dpcl_lshift(.lsf_out(out),.hi(high),.lo(low),.lsa(shifta));
 
endmodule


module cmp_zro_16(out,in);
input [15:0]  in;
output        out;
 
cmp16zero f_dpcl_cmp16zero(.a_eql_z(out),.ai(in));
 
endmodule



module compare_zero_32(out,in);
//  Performs an EQUALITY comparision to zero:
input [31:0]  in;
output        out;
 
cmp32zero f_dpcl_cmp32zero(.a_eql_z(out),.ai(in));
endmodule


module compare_16(out,in0,in1);
//  Performs an EQUALITY comparision
input [15:0]  in0,in1;
output        out;
 
cmp16_e f_dpcl_cmp16_e(.a_eql_b(out),.ai(in0),.bi(in1));
endmodule



module encoder16( ptrap_in_e ,trap_vec_e);

output [15:0] ptrap_in_e;
input [15:0] trap_vec_e;
wire [3:0] ptrap_in_e1, ptrap_in_e2;
wire [3:0] ptrap_in_e3;
wire [3:0] ptrap_in_e0;
wire e2,e1,e0;
wire c2,c1;

/*always @(trap_vec_e[15:0]) begin
  casex (trap_vec_e[15:0])
    16'b1xxxxxxxxxxxxxxx : ptrap_in_e=16'h8000;
    16'b01xxxxxxxxxxxxxx : ptrap_in_e=16'h4000;
    16'b001xxxxxxxxxxxxx : ptrap_in_e=16'h2000;
    16'b0001xxxxxxxxxxxx : ptrap_in_e=16'h1000;
    16'b00001xxxxxxxxxxx : ptrap_in_e=16'h0800;
    16'b000001xxxxxxxxxx : ptrap_in_e=16'h0400;
    16'b0000001xxxxxxxxx : ptrap_in_e=16'h0200;
    16'b00000001xxxxxxxx : ptrap_in_e=16'h0100;
    16'b000000001xxxxxxx : ptrap_in_e=16'h0080;
    16'b0000000001xxxxxx : ptrap_in_e=16'h0040;
    16'b00000000001xxxxx : ptrap_in_e=16'h0020;
    16'b000000000001xxxx : ptrap_in_e=16'h0010;
    16'b0000000000001xxx : ptrap_in_e=16'h0008;
    16'b00000000000001xx : ptrap_in_e=16'h0004;
    16'b000000000000001x : ptrap_in_e=16'h0002;
    16'b0000000000000001 : ptrap_in_e=16'h0001;
   default               : ptrap_in_e=16'h0000;
  endcase
end
*/

assign e0 = (&(~(trap_vec_e[15:12])));
assign e1 = (&(~(trap_vec_e[11:8])));
assign e2 = (&(~(trap_vec_e[7:4])));

trp  trap3( .ptrap_in(ptrap_in_e3[3:0]),
	     .trap_v(trap_vec_e[15:12])
           );
trp  trap2( .ptrap_in(ptrap_in_e2[3:0]),
	     .trap_v(trap_vec_e[11:8])
           );
trp  trap1( .ptrap_in(ptrap_in_e1[3:0]),
	     .trap_v(trap_vec_e[7:4])
           );
trp  trap0( .ptrap_in(ptrap_in_e0[3:0]),
	     .trap_v(trap_vec_e[3:0])
           );

assign ptrap_in_e[15:12] = ptrap_in_e3[3:0];
assign ptrap_in_e[11:8] = ({4{e0}} & ptrap_in_e2[3:0]);
assign ptrap_in_e[7:4] = ({4{c1}} & ptrap_in_e1[3:0]);
assign ptrap_in_e[3:0] = ({4{c2}} & ptrap_in_e0[3:0]);

assign c1 = (e0 & e1) ;
assign c2 = (c1 & e2) ;

endmodule


module trp(ptrap_in,trap_v);
output[3:0] ptrap_in;
input[3:0] trap_v;
reg [3:0] ptrap_in;  
always @(trap_v)
begin
casex(trap_v[3:0])
     4'b1xxx : ptrap_in=4'h8;
     4'b01xx : ptrap_in=4'h4;
     4'b001x : ptrap_in=4'h2;
     4'b0001 : ptrap_in=4'h1;
       default : ptrap_in=4'h0;
endcase
end

endmodule



module buf_64 ( out,in );
output [63:0] out;
input [63:0]  in;

assign out = in ;

endmodule



module multor7 (in, out);
input [6:0] in;
output 	    out;

assign out = |in[6:0];

endmodule


... (truncated)
module multfa (ai, bi, ci, so, co);
input 	ai, bi, ci;
output	so, co;

assign {co,so} = ai + bi + ci;

endmodule



... (truncated)
module multha (ai, bi, so, co);
input 	ai, bi;
output	so, co;

assign {co,so} = ai + bi;

endmodule



module mppartial (	P0, P1, P2, P3,
			LO, RI,
			SBN, SB, SL0, SL1,
			A0, A1, A2, A3,
			B0, B1, B2, B3);

output P0,P1,P2,P3,LO;
input A0,B0,A1,B1,A2,B2,A3,B3,SBN,SB,RI,SL0,SL1;

reg P0,P1,P2,P3;
wire A3_OUT = SB ? B3:A3;
wire A2_OUT = SB ? B2:A2;
wire A1_OUT = SB ? B1:A1;
wire A0_OUT = SB ? B0:A0;
 
always @(SL0 or SL1 or A3_OUT or A2_OUT or A1_OUT or A0_OUT or RI) begin
  case ({SL0,SL1})
        2'b01:  {P0,P1,P2,P3} = {~RI, ~A0_OUT, ~A1_OUT, ~A2_OUT};
        2'b10:  {P0,P1,P2,P3} = {~A0_OUT, ~A1_OUT, ~A2_OUT, ~A3_OUT};
        2'b00:  {P0,P1,P2,P3} = 4'b1111;
        2'b11:  begin
                   P0 = (A0_OUT | RI) ? 1'b0 : 1'b1;
                   P1 = (A1_OUT | A0_OUT) ? 1'b0 : 1'b1;
                   P2 = (A2_OUT | A1_OUT) ? 1'b0 : 1'b1;
                   P3 = (A3_OUT | A2_OUT) ? 1'b0 : 1'b1;
                end
  endcase
  end
 
assign LO = A3_OUT;
endmodule
 


module adder_33 (op_a, op_b, cin, sum, cout);
 
input  [32:0]  op_a;
input  [32:0]  op_b;
input          cin;
output [32:0]  sum;
output         cout;
 
wire   [32:0]  sum;
 
  assign {cout, sum} = op_a + op_b + cin;
 
endmodule
 



module incre_32 (inp, out);
 
input  [31:0]  inp;
output [31:0]  out;
 
wire   [31:0]  out;
 
  assign out = inp + 1;
 
endmodule
 


module inc16 (ai, sum);
 
input  [15:0]  ai;
output [15:0]  sum;
 
assign  sum[15:0]=ai[15:0]+ 1'b1;
endmodule
 


module inc8 (ai, sum);
 
input  [7:0]  ai;
output [7:0]  sum;
 
assign  sum[7:0]=ai[7:0]+ 1'b1;
endmodule
 

module inc9 (ai, sum);
 
input  [8:0]  ai;
output [8:0]  sum;
 
assign  sum[8:0]=ai[8:0]+ 1'b1;
endmodule
 
 

module fa9 (a, b, c, sum, cout);
 
input  [8:0]  a;
input  [8:0]  b;
output  [8:0]  sum;
 
input           c;              // carry in
output          cout;           // carry out
 
assign {cout,sum} = a + b + c;
 
 
endmodule
 


module buf10_drv_32 (

	in,
	out

);

input	[31:0]	in;
output	[31:0]	out;

	assign	out = in;

endmodule


module inv10_drv_32 (

	in,
	out

);

input	[31:0]	in;
output	[31:0]	out;

	assign	out = ~in;

endmodule

module inv4_drv_32 (

	in,
	out

);

input	[31:0]	in;
output	[31:0]	out;

	assign	out = ~in;

endmodule