/****************************************************************
---------------------------------------------------------------
Copyright 1999 Sun Microsystems, Inc., 901 San Antonio
Road, Palo Alto, CA 94303, U.S.A. All Rights Reserved.
The contents of this file are subject to the current
version of the Sun Community Source License, picoJava-II
Core ("the License"). You may not use this file except
in compliance with the License. You may obtain a copy
of the License by searching for "Sun Community Source
License" on the World Wide Web at http://www.sun.com.
See the License for the rights, obligations, and
limitations governing use of the contents of this file.
Sun, Sun Microsystems, the Sun logo, and all Sun-based
trademarks and logos, Java, picoJava, and all Java-based
trademarks and logos are trademarks or registered trademarks
of Sun Microsystems, Inc. in the United States and other
countries.
----------------------------------------------------------------
******************************************************************/
// ------------------- 19-bit bit_wise comparator -----------------------
module cmp19_e
(ai, bi, a_eql_b);
input [18:0] ai;
input [18:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[18:0] == bi[18:0] ) ;
*/
/*Use this portion for RTL simulation.*/
wire [18:0] bit_eql; // bit-wise equal output
wire [4:0] level_1; // 8-equal_not output
wire [1:0] level_2; // 4-equal
assign bit_eql[18:0] = ai[18:0] ^~ bi[18:0] ; // 32 2-in exnor, g10p "en".
assign level_1[4] = !(&bit_eql[18:16]); // 1 3-in "nd3".
assign level_1[3] = !(&bit_eql[15:12]); // 1 4-in "nd4".
assign level_1[2] = !(&bit_eql[11:8]); // 1 4-in "nd4".
assign level_1[1] = !(&bit_eql[7:4]); // 1 4-in "nd4".
assign level_1[0] = !(&bit_eql[3:0]); // 1 4-in "nd4".
assign level_2[1] = !(|level_1[4:2]); // 1 2-in "nr3".
assign level_2[0] = !(|level_1[1:0]); // 1 2-in "nr2".
assign a_eql_b = (&level_2[1:0]); // 1 2-in "and4".
endmodule
// ------------------- 1) 20-bit bit_wise comparator -----------------------
![[Up: cmp_eq_19 i_cmp_eq_19]](v2html-up.gif)
module cmp20_e (ai, bi, a_eql_b);
input [19:0] ai;
input [19:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[19:0] == bi[19:0] ) ;
*/
/*Use this portion for RTL simulation.*/
wire [19:0] bit_eql; // bit-wise equal output
wire [4:0] level_1; // 8-equal_not output
wire [1:0] level_2; // 4-equal
assign bit_eql[19:0] = ai[19:0] ^~ bi[19:0] ; // 32 2-in exnor, g10p "en".
assign level_1[4] = !(&bit_eql[19:16]); // 1 4-in "nd4".
assign level_1[3] = !(&bit_eql[15:12]); // 1 4-in "nd4".
assign level_1[2] = !(&bit_eql[11:8]); // 1 4-in "nd4".
assign level_1[1] = !(&bit_eql[7:4]); // 1 4-in "nd4".
assign level_1[0] = !(&bit_eql[3:0]); // 1 4-in "nd4".
assign level_2[1] = !(|level_1[4:2]); // 1 2-in "nr3".
assign level_2[0] = !(|level_1[1:0]); // 1 2-in "nr2".
assign a_eql_b = (&level_2[1:0]); // 1 2-in "and4".
endmodule
// -------------------2) 6-bit adder --------------------------
module fa6 (a, b, c, sum, cout);
input [5:0] a;
input [5:0] b;
output [5:0] sum;
input c; // carry in
output cout; // carry out
// -------------------- carry tree level 1 ----------------------------
// produce the generate for the least significant bit
wire g0_l = !(((a[0] | b[0]) & c) | (a[0] &b[0]));
// produce the propagates and generates for the other bits
wire gen0_l, p0_l, g1_l, p1_l, g2_l, p2_l, g3_l, p3_l, g4_l, p4_l,
g5_l, p5_l;
pgnx_fa6 pgnx0 (a[0], b[0], gen0_l, p0_l); // gen0_l is used only for sum[0] calc.
pgnx_fa6 pgnx1 (a[1], b[1], g1_l, p1_l);
pgnx_fa6 pgnx2 (a[2], b[2], g2_l, p2_l);
pgnx_fa6 pgnx3 (a[3], b[3], g3_l, p3_l);
pgnx_fa6 pgnx4 (a[4], b[4], g4_l, p4_l);
pgnx_fa6 pgnx5 (a[5], b[5], g5_l, p5_l);
// -------------------- carry tree level 2 ----------------------------
// produce group propagates/generates for sets of 2 bits
// this stage contains the ling modification, which simplifies
// this stage, but the outputs are Pseudo-generates, which
// later need to be recovered by anding with p
wire g0to1, g1to2, g2to3, g4to5, p0to1, p1to2, p3to4;
pg2lg_fa6 pg2lg ( .gd_l(g0_l),
.gu_l(g1_l),
.g(g0to1)); //assign g0to1 = !(g0_l & g1_l);
pg2l_fa6 p2gl0 ( .gd_l(g1_l),
.gu_l(g2_l),
.pd_l(p0_l),
.pu_l(p1_l),
.g(g1to2), //assign g1to2 = !(g1_l & g2_l);
.p(p0to1)); //assign p0to1 = !(p0_l | p1_l);
pg2l_fa6 p2gl1 ( .gd_l(g2_l),
.gu_l(g3_l),
.pd_l(p1_l),
.pu_l(p2_l),
.g(g2to3), //assign g2to3 = !(g2_l & g3_l);
.p(p1to2)); //assign p1to2 = !(p1_l | p2_l);
pg2l_fa6 p2gl2 ( .gd_l(g4_l),
.gu_l(g5_l),
.pd_l(p3_l),
.pu_l(p4_l),
.g(g4to5), //assign g4to5 = !(g4_l & g5_l);
.p(p3to4)); //assign p3to4 = !(p3_l | p4_l);
// -------------------- carry tree level 3 ----------------------------
// use aoi to make group generates
wire g0to2_l, g0to3_l, g2to5_l, p1to4_l;
aoig_fa6 aoig0 ( .gd(~g0_l),
.gu(g1to2),
.pu(p0to1),
.g_l(g0to2_l)); //assign g0to2_l = !((!g0_l & p0to1) | g1to2);
aoig_fa6 aoig1 ( .gd(g0to1),
.gu(g2to3),
.pu(p1to2),
.g_l(g0to3_l)); //assign g0to3_l = !((g0to1 & p1to2) | g2to3);
baoi_fa6 baoi0 ( .gd(g2to3),
.gu(g4to5),
.pd(p1to2),
.pu(p3to4),
.g_l(g2to5_l), //assign g2to5_l = !((g2to3 & p3to4) | g4to5);
.p_l(p1to4_l)); //assign p1to4_l = !(p1to2 & p3to4);
// -------------------- carry tree level 4 ----------------------------
// use oai's since the inputs are active-low.
wire g0to5;
oaig_fa6 oaig0 ( .gd_l(~g0to1),
.gu_l(g2to5_l),
.pu_l(p1to4_l),
.g(g0to5));
//assign g0to5 = !((!g0to1 | p1to4_l) & g2to5_l);
// -------------------- sum, and cout ----------------------------
assign cout = g0to5 & !p5_l; // recover cout by anding p5 with the pseudo-generate
wire [5:0] suma, sumb; // local sums before carry select mux
sum2_fa6 sum0to1 (.g1(~gen0_l), .g2(~g1_l),
.p0(1'b1), .p1(~p0_l), .p2(~p1_l),
.sum1a(suma[0]), .sum2a(suma[1]),
.sum1b(sumb[0]), .sum2b(sumb[1]));
sum2_fa6 sum2to3 (.g1(~g2_l), .g2(~g3_l),
.p0(~p1_l), .p1(~p2_l), .p2(~p3_l),
.sum1a(suma[2]), .sum2a(suma[3]),
.sum1b(sumb[2]), .sum2b(sumb[3]));
sum2_fa6 sum4to5 (.g1(~g4_l), .g2(~g5_l),
.p0(~p3_l), .p1(~p4_l), .p2(~p5_l),
.sum1a(suma[4]), .sum2a(suma[5]),
.sum1b(sumb[4]), .sum2b(sumb[5]));
/********** mux to select sum using G* signals from carry tree *****/
selsum2_fa6 selsum0to1 ( .sum1a(suma[0]), .sum2a(suma[1]),
.sum1b(sumb[0]), .sum2b(sumb[1]),
.sel(c),
.sum1(sum[0]), .sum2(sum[1]));
selsum2_fa6 selsum2to3 ( .sum1a(suma[2]), .sum2a(suma[3]),
.sum1b(sumb[2]), .sum2b(sumb[3]),
.sel(g0to1),
.sum1(sum[2]), .sum2(sum[3]));
selsum2_fa6 selsum4to5 ( .sum1a(suma[4]), .sum2a(suma[5]),
.sum1b(sumb[4]), .sum2b(sumb[5]),
.sel(~g0to3_l),
.sum1(sum[4]), .sum2(sum[5]));
endmodule
// -------------------- selsum2 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selsum2_fa6 (sel, sum1, sum2,
sum1a, sum2a,
sum1b, sum2b);
input sum1a, sum2a,
sum1b, sum2b, sel;
output sum1, sum2;
wire sum1, sum2;
assign sum1 = sel ? sum1a : sum1b;
assign sum2 = sel ? sum2a : sum2b;
endmodule
// -------------------- sum ----------------------------
// we need to recover the real generates
// after the ling modification used in level 2.
// we also are replacing the a,b with p,g to reduce loading
// of the a,b inputs. (a ^ b = p & !g)
// send out two sets of sums to be selected with mux at last stage
module sum2_fa6 (g1, g2, p0, p1, p2,
sum1a, sum2a,
sum1b, sum2b);
output sum1a, sum2a,
sum1b, sum2b; // sum outputs.
input g1, g2; // individual generate inputs.
input p0, p1, p2; // individual propagate inputs.
//input G; // global carry input. (pseudo-generate)
wire sum1a, sum2a,
sum1b, sum2b;
assign sum1a = (p1 & (~g1)) ^ p0;
assign sum2a = (p2 & (~g2)) ^ (g1 | (p1 & p0));
assign sum1b = p1 & (~g1);
assign sum2b = (p2 & (~g2)) ^ g1;
endmodule
// -------------------- pgnx ----------------------------
module pgnx_fa6 (a, b, g_l, p_l); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
// -------------------- pg2lg ----------------------------
// ling modification stage, generate only
module pg2lg_fa6 (gd_l, gu_l, g);
input gd_l, gu_l;
output g;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
// -------------------- pg2l ----------------------------
// ling modification stage, psuedo group generate and propagate
module pg2l_fa6 (gd_l, gu_l, pd_l, pu_l, g, p);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
// -------------------- aoig ----------------------------
// aoi for carry tree generates
module aoig_fa6 (gd, gu, pu, g_l);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
// -------------------- oaig ----------------------------
// aoi for carry tree generates
module oaig_fa6 (gd_l, gu_l, pu_l, g);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
// -------------------- baoi ----------------------------
// aoi for carry tree generates + logic for propagate
module baoi_fa6 (gd, gu, pd, pu, g_l, p_l);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
// ------------------- 3) 6-bit greater than comparator------------------
module gr6 (a, b, gr);
input [5:0] a;
input [5:0] b;
output gr; // carry out
// -------------------- carry tree level 1 ----------------------------
// produce the generate for the least significant bit (sch: glsbs)
wire g0_l = !((a[0] &b[0]));
// produce the propagates and generates for the other bits
wire gen0_l, p0_l, g1_l, p1_l, g2_l, p2_l, g3_l, p3_l, g4_l, p4_l,
g5_l, p5_l;
pgnx_gr6 pgnx0 (a[0], b[0], gen0_l, p0_l); // gen0_l is used only for sum[0] calc.
pgnx_gr6 pgnx1 (a[1], b[1], g1_l, p1_l);
pgnx_gr6 pgnx2 (a[2], b[2], g2_l, p2_l);
pgnx_gr6 pgnx3 (a[3], b[3], g3_l, p3_l);
pgnx_gr6 pgnx4 (a[4], b[4], g4_l, p4_l);
pgnx_gr6 pgnx5 (a[5], b[5], g5_l, p5_l);
// -------------------- carry tree level 2 ----------------------------
// produce group propagates/generates for sets of 2 bits
// this stage contains the ling modification, which simplifies
// this stage, but the outputs are Pseudo-generates, which
// later need to be recovered by anding
wire g0to1, g1to2, g2to3, g4to5, p0to1, p1to2, p3to4;
pg2lg_gr6 pg2lg ( .gd_l(g0_l),
.gu_l(g1_l),
.g(g0to1)); //assign g0to1 = !(g0_l & g1_l);
pg2l_gr6 p2gl0 ( .gd_l(g1_l),
.gu_l(g2_l),
.pd_l(p0_l),
.pu_l(p1_l),
.g(g1to2), //assign g1to2 = !(g1_l & g2_l);
.p(p0to1)); //assign p0to1 = !(p0_l | p1_l);
pg2l_gr6 p2gl1 ( .gd_l(g2_l),
.gu_l(g3_l),
.pd_l(p1_l),
.pu_l(p2_l),
.g(g2to3), //assign g2to3 = !(g2_l & g3_l);
.p(p1to2)); //assign p1to2 = !(p1_l | p2_l);
pg2l_gr6 p2gl2 ( .gd_l(g4_l),
.gu_l(g5_l),
.pd_l(p3_l),
.pu_l(p4_l),
.g(g4to5), //assign g4to5 = !(g4_l & g5_l);
.p(p3to4)); //assign p3to4 = !(p3_l | p4_l);
// -------------------- carry tree level 3 ----------------------------
// use aoi to make group generates
wire g0to2_l, g0to3_l, g2to5_l, p1to4_l;
aoig_gr6 aoig0 ( .gd(~g0_l),
.gu(g1to2),
.pu(p0to1),
.g_l(g0to2_l)); //assign g0to2_l = !((!g0_l & p0to1) | g1to2);
aoig_gr6 aoig1 ( .gd(g0to1),
.gu(g2to3),
.pu(p1to2),
.g_l(g0to3_l)); //assign g0to3_l = !((g0to1 & p1to2) | g2to3);
baoi_gr6 baoi0 ( .gd(g2to3),
.gu(g4to5),
.pd(p1to2),
.pu(p3to4),
.g_l(g2to5_l), //assign g2to5_l = !((g2to3 & p3to4) | g4to5);
.p_l(p1to4_l)); //assign p1to4_l = !(p1to2 & p3to4);
// -------------------- carry tree level 4 ----------------------------
// use oai's since the inputs are active-low.
wire g0to5;
oaig_gr6 oaig0 ( .gd_l(~g0to1),
.gu_l(g2to5_l),
.pu_l(p1to4_l),
.g(g0to5));
//assign g0to5 = !((!g0to1 | p1to4_l) & g2to5_l);
// -------------------- cout ----------------------------
assign gr = g0to5 & !p5_l; // recover gr by anding p5 with the pseudo-generate
endmodule
// -------------------- pgnx ----------------------------
module pgnx_gr6 (a, b, g_l, p_l); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make initial generate
assign p_l = !(a | b); //nor to make initial propagate
endmodule
// -------------------- pg2lg ----------------------------
// ling modification stage, generate only
module pg2lg_gr6 (gd_l, gu_l, g);
input gd_l, gu_l;
output g;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
// -------------------- pg2l ----------------------------
// ling modification stage, psuedo group generate and propagate
module pg2l_gr6 (gd_l, gu_l, pd_l, pu_l, g, p);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
// -------------------- aoig ----------------------------
// aoi for carry tree generates
module aoig_gr6 (gd, gu, pu, g_l);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
// -------------------- oaig ----------------------------
// aoi for carry tree generates
module oaig_gr6 (gd_l, gu_l, pu_l, g);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
// -------------------- baoi ----------------------------
// aoi for carry tree generates + logic for propagate
module baoi_gr6 (gd, gu, pd, pu, g_l, p_l);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
// -------------------4) 32-bit all_zero comparator -----------------------
module cmp32zero (ai, a_eql_z);
input [31:0] ai;
output a_eql_z; // ai equal to all_zero.
/* Logic
assign a_eql_z = ( ai[31:0] == 32'b0 ) ;
*/
/* Use this portion for RTL simulation.*/
wire [31:0] bit_eql; // bit-wise equal output
wire [7:0] level_1; // 8-equal_not output
wire [3:0] level_2; // 4-equal
assign bit_eql[31:0] = ~ai[31:0] ; // 32 "n1a".
assign level_1[7] = !(&bit_eql[31:28]); // 1 4-in "nd4".
assign level_1[6] = !(&bit_eql[27:24]); // 1 4-in "nd4".
assign level_1[5] = !(&bit_eql[23:20]); // 1 4-in "nd4".
assign level_1[4] = !(&bit_eql[19:16]); // 1 4-in "nd4".
assign level_1[3] = !(&bit_eql[15:12]); // 1 4-in "nd4".
assign level_1[2] = !(&bit_eql[11:8]); // 1 4-in "nd4".
assign level_1[1] = !(&bit_eql[7:4]); // 1 4-in "nd4".
assign level_1[0] = !(&bit_eql[3:0]); // 1 4-in "nd4".
assign level_2[3] = !(|level_1[7:6]); // 1 2-in "nr2".
assign level_2[2] = !(|level_1[5:4]); // 1 2-in "nr2".
assign level_2[1] = !(|level_1[3:2]); // 1 2-in "nr2".
assign level_2[0] = !(|level_1[1:0]); // 1 2-in "nr2".
assign a_eql_z = (&level_2[3:0]); // 1 2-in "and4".
endmodule
// ------------------- 5) 30-bit incrementer --------------
module inc30 (ai, sum);
input [29:0] ai;
output [29:0] sum;
assign sum[29:0]=ai[29:0]+ 1'b1;
endmodule
// ------------------- 5) 32-bit incrementer ---------------
// ------------------- Kogge-Stone style ---------------
module inc32 (ai, sum);
input [31:0] ai;
output [31:0] sum;
wire g1_0_l;
wire p26_25_l, p24_23_l, p22_21_l, p20_19_l, p18_17_l, p16_15_l, p14_13_l,
p12_11_l, p10_9_l, p8_7_l, p6_5_l, p4_3_l, p2_1_l;
wire g3_0;
wire p26_23, p22_19, p18_15, p14_11, p10_7, p6_3;
wire g7_0_l;
wire p26_19_l, p22_15_l, p18_11_l, p14_7_l, p10_3_l;
wire g15_0, g11_0;
wire p26_11, p22_7, p18_3;
wire g27_0_l, g23_0_l, g19_0_l;
wire w2i_g3_0, w3_g7_0, w3_g3_0, w4i_g15_0, w4i_g11_0, w4i_g7_0, w4i_g3_0 ;
wire [31:0] in, inb;
wire [31:0] sum;
/* prop0_inc32 stage */
prop0_inc32 p_26_25 ( .p2grp_l(p26_25_l),
.ain(ai[26:25]));
prop0_inc32 p_24_23 ( .p2grp_l(p24_23_l),
.ain(ai[24:23]));
prop0_inc32 p_22_21 ( .p2grp_l(p22_21_l),
.ain(ai[22:21]));
prop0_inc32 p_20_19 ( .p2grp_l(p20_19_l),
.ain(ai[20:19]));
prop0_inc32 p_18_17 ( .p2grp_l(p18_17_l),
.ain(ai[18:17]));
prop0_inc32 p_16_15 ( .p2grp_l(p16_15_l),
.ain(ai[16:15]));
prop0_inc32 p_14_13 ( .p2grp_l(p14_13_l),
.ain(ai[14:13]));
prop0_inc32 p_12_11 ( .p2grp_l(p12_11_l),
.ain(ai[12:11]));
prop0_inc32 p_10_9 ( .p2grp_l(p10_9_l),
.ain(ai[10:9]));
prop0_inc32 p_8_7 ( .p2grp_l(p8_7_l),
.ain(ai[8:7]));
prop0_inc32 p_6_5 ( .p2grp_l(p6_5_l),
.ain(ai[6:5]));
prop0_inc32 p_4_3 ( .p2grp_l(p4_3_l),
.ain(ai[4:3]));
prop0_inc32 p_2_1 ( .p2grp_l(p2_1_l),
.ain(ai[2:1]));
assign g1_0_l = !ai[0];
/* prop1_inc32 stage */
prop1_inc32 p_26_23 ( .pgrp(p26_23),
.pu_in(p26_25_l),
.pd_in(p24_23_l));
prop1_inc32 p_22_19 ( .pgrp(p22_19),
.pu_in(p22_21_l),
.pd_in(p20_19_l));
prop1_inc32 p_18_15 ( .pgrp(p18_15),
.pu_in(p18_17_l),
.pd_in(p16_15_l));
prop1_inc32 p_14_11 ( .pgrp(p14_11),
.pu_in(p14_13_l),
.pd_in(p12_11_l));
prop1_inc32 p_10_7 ( .pgrp(p10_7),
.pu_in(p10_9_l),
.pd_in(p8_7_l));
prop1_inc32 p_6_3 ( .pgrp(p6_3),
.pu_in(p6_5_l),
.pd_in(p4_3_l));
gen1_inc32 g_3_0 ( .ggrp(g3_0),
.pu_in(p2_1_l),
.gd_in(g1_0_l));
/* prop2_inc32 stage */
prop2_inc32 p_26_19 ( .pgrp_l(p26_19_l),
.pu_in(p26_23),
.pd_in(p22_19));
prop2_inc32 p_22_15 ( .pgrp_l(p22_15_l),
.pu_in(p22_19),
.pd_in(p18_15));
prop2_inc32 p_18_11 ( .pgrp_l(p18_11_l),
.pu_in(p18_15),
.pd_in(p14_11));
prop2_inc32 p_14_7 ( .pgrp_l(p14_7_l),
.pu_in(p14_11),
.pd_in(p10_7));
prop2_inc32 p_10_3 ( .pgrp_l(p10_3_l),
.pu_in(p10_7),
.pd_in(p6_3));
gen2_inc32 g_7_0 ( .ggrp_l(g7_0_l),
.pu_in(p6_3),
.gd_in(g3_0));
assign w2i_g3_0 = !g3_0;
/* prop3_inc32 stage */
prop3_inc32 p_26_11 (.pgrp(p26_11),
.pu_in(p26_19_l),
.pd_in(p18_11_l));
prop3_inc32 p_22_7 ( .pgrp(p22_7),
.pu_in(p22_15_l),
.pd_in(p14_7_l));
prop3_inc32 p_18_3 ( .pgrp(p18_3),
.pu_in(p18_11_l),
.pd_in(p10_3_l));
gen3_inc32 g_15_0 ( .ggrp(g15_0),
.pu_in(p14_7_l),
.gd_in(g7_0_l));
gen3_inc32 g_11_0 ( .ggrp(g11_0),
.pu_in(p10_3_l),
.gd_in(w2i_g3_0));
assign w3_g7_0 = !g7_0_l;
assign w3_g3_0 = !w2i_g3_0;
/* g4 stage */
gen4_inc32 g_27_0 ( .ggrp_l(g27_0_l),
.pu_in(p26_11),
.gd_in(g11_0));
gen4_inc32 g_23_0 ( .ggrp_l(g23_0_l),
.pu_in(p22_7),
.gd_in(w3_g7_0));
gen4_inc32 g_19_0 ( .ggrp_l(g19_0_l),
.pu_in(p18_3),
.gd_in(w3_g3_0));
assign w4i_g15_0 = !g15_0;
assign w4i_g11_0 = !g11_0;
assign w4i_g7_0 = !w3_g7_0;
assign w4i_g3_0 = !w3_g3_0;
/* Local Sum, Carry-select stage */
presum_i32 psum31_28 (.p0(!(!ai[27])), .p1(!(!ai[28])), .p2(!(!ai[29])), .p3(!(!ai[30])), .p4(!(!ai[31])),
.s1(in[28]), .s2(in[29]), .s3(in[30]), .s4(in[31]),
.s1b(inb[28]), .s2b(inb[29]), .s3b(inb[30]), .s4b(inb[31]));
presum_i32 psum27_24 (.p0(!(!ai[23])), .p1(!(!ai[24])), .p2(!(!ai[25])), .p3(!(!ai[26])), .p4(!(!ai[27])),
.s1(in[24]), .s2(in[25]), .s3(in[26]), .s4(in[27]),
.s1b(inb[24]), .s2b(inb[25]), .s3b(inb[26]), .s4b(inb[27]));
presum_i32 psum23_20 (.p0(!(!ai[19])), .p1(!(!ai[20])), .p2(!(!ai[21])), .p3(!(!ai[22])), .p4(!(!ai[23])),
.s1(in[20]), .s2(in[21]), .s3(in[22]), .s4(in[23]),
.s1b(inb[20]), .s2b(inb[21]), .s3b(inb[22]), .s4b(inb[23]));
presum_i32 psum19_16 (.p0(!(!ai[15])), .p1(!(!ai[16])), .p2(!(!ai[17])), .p3(!(!ai[18])), .p4(!(!ai[19])),
.s1(in[16]), .s2(in[17]), .s3(in[18]), .s4(in[19]),
.s1b(inb[16]), .s2b(inb[17]), .s3b(inb[18]), .s4b(inb[19]));
presum_i32 psum15_12 (.p0(!(!ai[11])), .p1(!(!ai[12])), .p2(!(!ai[13])), .p3(!(!ai[14])), .p4(!(!ai[15])),
.s1(in[12]), .s2(in[13]), .s3(in[14]), .s4(in[15]),
.s1b(inb[12]), .s2b(inb[13]), .s3b(inb[14]), .s4b(inb[15]));
presum_i32 psum11_8 (.p0(!(!ai[7])), .p1(!(!ai[8])), .p2(!(!ai[9])), .p3(!(!ai[10])), .p4(!(!ai[11])),
.s1(in[8]), .s2(in[9]), .s3(in[10]), .s4(in[11]),
.s1b(inb[8]), .s2b(inb[9]), .s3b(inb[10]), .s4b(inb[11]));
presum_i32 psum7_4 (.p0(!(!ai[3])), .p1(!(!ai[4])), .p2(!(!ai[5])), .p3(!(!ai[6])), .p4(!(!ai[7])),
.s1(in[4]), .s2(in[5]), .s3(in[6]), .s4(in[7]),
.s1b(inb[4]), .s2b(inb[5]), .s3b(inb[6]), .s4b(inb[7]));
presum_i32 psum3_0 (.p0(1'b1), .p1(!(!ai[0])), .p2(!(!ai[1])), .p3(!(!ai[2])), .p4(!(!ai[3])),
.s1(in[0]), .s2(in[1]), .s3(in[2]), .s4(in[3]),
.s1b(inb[0]), .s2b(inb[1]), .s3b(inb[2]), .s4b(inb[3]));
/* Sum stage */
sum4s_i32 sum31_28 (.csel(!g27_0_l), .sin1(in[28]), .sin2(in[29]), .sin3(in[30]), .sin4(in[31]),
.sin1b(inb[28]), .sin2b(inb[29]), .sin3b(inb[30]), .sin4b(inb[31]),
.sum1(sum[28]), .sum2(sum[29]), .sum3(sum[30]), .sum4(sum[31]));
sum4s_i32 sum27_24 (.csel(!g23_0_l), .sin1(in[24]), .sin2(in[25]), .sin3(in[26]), .sin4(in[27]),
.sin1b(inb[24]), .sin2b(inb[25]), .sin3b(inb[26]), .sin4b(inb[27]),
.sum1(sum[24]), .sum2(sum[25]), .sum3(sum[26]), .sum4(sum[27]));
sum4s_i32 sum23_20 (.csel(!g19_0_l), .sin1(in[20]), .sin2(in[21]), .sin3(in[22]), .sin4(in[23]),
.sin1b(inb[20]), .sin2b(inb[21]), .sin3b(inb[22]), .sin4b(inb[23]),
.sum1(sum[20]), .sum2(sum[21]), .sum3(sum[22]), .sum4(sum[23]));
sum4s_i32 sum19_16 (.csel(!w4i_g15_0), .sin1(in[16]), .sin2(in[17]), .sin3(in[18]), .sin4(in[19]),
.sin1b(inb[16]), .sin2b(inb[17]), .sin3b(inb[18]), .sin4b(inb[19]),
.sum1(sum[16]), .sum2(sum[17]), .sum3(sum[18]), .sum4(sum[19]));
sum4s_i32 sum15_12 (.csel(!w4i_g11_0), .sin1(in[12]), .sin2(in[13]), .sin3(in[14]), .sin4(in[15]),
.sin1b(inb[12]), .sin2b(inb[13]), .sin3b(inb[14]), .sin4b(inb[15]),
.sum1(sum[12]), .sum2(sum[13]), .sum3(sum[14]), .sum4(sum[15]));
sum4s_i32 sum11_8 (.csel(!w4i_g7_0), .sin1(in[8]), .sin2(in[9]), .sin3(in[10]), .sin4(in[11]),
.sin1b(inb[8]), .sin2b(inb[9]), .sin3b(inb[10]), .sin4b(inb[11]),
.sum1(sum[8]), .sum2(sum[9]), .sum3(sum[10]), .sum4(sum[11]));
sum4s_i32 sum7_4 (.csel(!w4i_g3_0), .sin1(in[4]), .sin2(in[5]), .sin3(in[6]), .sin4(in[7]),
.sin1b(inb[4]), .sin2b(inb[5]), .sin3b(inb[6]), .sin4b(inb[7]),
.sum1(sum[4]), .sum2(sum[5]), .sum3(sum[6]), .sum4(sum[7]));
sum4s_i32 sum3_0 (.csel(1'b1), .sin1(in[0]), .sin2(in[1]), .sin3(in[2]), .sin4(in[3]),
.sin1b(inb[0]), .sin2b(inb[1]), .sin3b(inb[2]), .sin4b(inb[3]),
.sum1(sum[0]), .sum2(sum[1]), .sum3(sum[2]), .sum4(sum[3]));
endmodule
/* prop0_inc32 */
module prop0_inc32 (p2grp_l, ain);
output p2grp_l;
input [1:0] ain;
assign p2grp_l = !(ain[1] & ain[0]);
endmodule
/* prop1_inc32 */
module prop1_inc32 (pgrp, pu_in, pd_in);
output pgrp;
input pu_in, pd_in;
assign pgrp = !(pu_in | pd_in);
endmodule
/* gen1_inc32 */
module gen1_inc32 (ggrp, pu_in, gd_in);
output ggrp;
input pu_in, gd_in;
assign ggrp = !(pu_in | gd_in);
endmodule
/* prop2_inc32 */
module prop2_inc32 (pgrp_l, pu_in, pd_in);
output pgrp_l;
input pu_in, pd_in;
assign pgrp_l = !(pu_in & pd_in);
endmodule
/* gen2_inc32 */
module gen2_inc32 (ggrp_l, pu_in, gd_in);
output ggrp_l;
input pu_in, gd_in;
assign ggrp_l = !(pu_in & gd_in);
endmodule
/* prop3_inc32 */
module prop3_inc32 (pgrp, pu_in, pd_in);
output pgrp;
input pu_in, pd_in;
assign pgrp = !(pu_in | pd_in);
endmodule
/* gen3_inc32 */
module gen3_inc32 (ggrp, pu_in, gd_in);
output ggrp;
input pu_in, gd_in;
assign ggrp = !(pu_in | gd_in);
endmodule
/* gen4_inc32 */
module gen4_inc32 (ggrp_l, pu_in, gd_in);
output ggrp_l;
input pu_in, gd_in;
assign ggrp_l = !(pu_in & gd_in);
endmodule
/* Sum stage logic. Carry-select approach is used */
module sum4s_i32 (csel, sin1, sin2, sin3, sin4, sin1b, sin2b, sin3b, sin4b, sum1, sum2, sum3, sum4);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inputs assuming csel=0
input csel; // global carry input.
/* carry-select approach used here */
assign sum1 = csel == 1 ? sin1 : sin1b;
assign sum2 = csel == 1 ? sin2 : sin2b;
assign sum3 = csel == 1 ? sin3 : sin3b;
assign sum4 = csel == 1 ? sin4 : sin4b;
endmodule
module presum_i32 (p0, p1, p2, p3, p4, s1, s2, s3, s4, s1b, s2b, s3b, s4b);
input p0, p1, p2, p3, p4;
output s1, s2, s3, s4;
output s1b, s2b, s3b, s4b;
assign s1b = p1;
assign s2b = p2;
assign s3b = p3;
assign s4b = p4;
assign s1 = p1 ^ p0;
assign s2 = p2 ^ (p1 & p0);
assign s3 = p3 ^ ((p1 & p0) & p2);
assign s4 = p4 ^ (((p1 & p0) & p2) & p3);
endmodule
// -------------------6) 32-bit full adder -----------------------------------
// ------------------- Kogge-Stone style -----------------------------------
module fa32 (ai, bi, cin, sum, cout);
input [31:0] ai, bi;
input cin;
output [31:0] sum;
output cout;
wire [31:0] gi_l; // bit-wise generate carry output
wire [31:0] pi_l; // bit-wise propgate carry output
wire gen1_l;
wire g31_30, g2_fa329_28, g2_fa327_26, g2_fa325_24, g2_fa323_22, g2_fa321_20, g19_18, g17_16, g15_14,
g13_12, g11_10, g9_8, g7_6, g5_4, g3_2, g1_0;
wire p30_29, p28_27, p26_25, p24_23, p22_21, p20_19, p18_17, p16_15, p14_13,
p12_11, p10_9, p8_7, p6_5, p4_3, p2_1;
wire g31_28_l, g2_fa327_24_l, g2_fa323_20_l, g19_16_l, g15_12_l, g11_8_l, g7_4_l, g3_0_l;
wire p30_27_l, p26_23_l, p22_19_l, p18_15_l, p14_11_l, p10_7_l, p6_3_l;
wire g31_24, g2_fa327_20, g2_fa323_16, g19_12, g15_8, g11_4, g7_0;
wire p30_23, p26_19, p22_15, p18_11, p14_7, p10_3;
wire g31_16_l, g2_fa327_12_l, g2_fa323_8_l, g19_4_l, g15_0_l, g11_0_l;
wire p30_15_l, p26_11_l, p22_7_l, p18_3_l;
wire g31_0, g2_fa327_0, g2_fa323_0, g19_0;
wire w2_3_0, w3i_7_0, w3i_3_0, w4_15_0, w4_11_0, w4_7_0, w4_3_0;
wire [31:0] in, inb;
wire [31:0] sum;
assign gen1_l = ~ (ai[0] & bi[0]);
/* pgnx_fa32 stage */
pgnx_fa32 pg_31 ( .gen_l(gi_l[31]), .pro_l(pi_l[31]), .ain(ai[31]), .bin(bi[31]));
pgnx_fa32 pg_30 ( .gen_l(gi_l[30]), .pro_l(pi_l[30]), .ain(ai[30]), .bin(bi[30]));
pgnx_fa32 pg_29 ( .gen_l(gi_l[29]), .pro_l(pi_l[29]), .ain(ai[29]), .bin(bi[29]));
pgnx_fa32 pg_28 ( .gen_l(gi_l[28]), .pro_l(pi_l[28]), .ain(ai[28]), .bin(bi[28]));
pgnx_fa32 pg_27 ( .gen_l(gi_l[27]), .pro_l(pi_l[27]), .ain(ai[27]), .bin(bi[27]));
pgnx_fa32 pg_26 ( .gen_l(gi_l[26]), .pro_l(pi_l[26]), .ain(ai[26]), .bin(bi[26]));
pgnx_fa32 pg_25 ( .gen_l(gi_l[25]), .pro_l(pi_l[25]), .ain(ai[25]), .bin(bi[25]));
pgnx_fa32 pg_24 ( .gen_l(gi_l[24]), .pro_l(pi_l[24]), .ain(ai[24]), .bin(bi[24]));
pgnx_fa32 pg_23 ( .gen_l(gi_l[23]), .pro_l(pi_l[23]), .ain(ai[23]), .bin(bi[23]));
pgnx_fa32 pg_22 ( .gen_l(gi_l[22]), .pro_l(pi_l[22]), .ain(ai[22]), .bin(bi[22]));
pgnx_fa32 pg_21 ( .gen_l(gi_l[21]), .pro_l(pi_l[21]), .ain(ai[21]), .bin(bi[21]));
pgnx_fa32 pg_20 ( .gen_l(gi_l[20]), .pro_l(pi_l[20]), .ain(ai[20]), .bin(bi[20]));
pgnx_fa32 pg_19 ( .gen_l(gi_l[19]), .pro_l(pi_l[19]), .ain(ai[19]), .bin(bi[19]));
pgnx_fa32 pg_18 ( .gen_l(gi_l[18]), .pro_l(pi_l[18]), .ain(ai[18]), .bin(bi[18]));
pgnx_fa32 pg_17 ( .gen_l(gi_l[17]), .pro_l(pi_l[17]), .ain(ai[17]), .bin(bi[17]));
pgnx_fa32 pg_16 ( .gen_l(gi_l[16]), .pro_l(pi_l[16]), .ain(ai[16]), .bin(bi[16]));
pgnx_fa32 pg_15 ( .gen_l(gi_l[15]), .pro_l(pi_l[15]), .ain(ai[15]), .bin(bi[15]));
pgnx_fa32 pg_14 ( .gen_l(gi_l[14]), .pro_l(pi_l[14]), .ain(ai[14]), .bin(bi[14]));
pgnx_fa32 pg_13 ( .gen_l(gi_l[13]), .pro_l(pi_l[13]), .ain(ai[13]), .bin(bi[13]));
pgnx_fa32 pg_12 ( .gen_l(gi_l[12]), .pro_l(pi_l[12]), .ain(ai[12]), .bin(bi[12]));
pgnx_fa32 pg_11 ( .gen_l(gi_l[11]), .pro_l(pi_l[11]), .ain(ai[11]), .bin(bi[11]));
pgnx_fa32 pg_10 ( .gen_l(gi_l[10]), .pro_l(pi_l[10]), .ain(ai[10]), .bin(bi[10]));
pgnx_fa32 pg_9 ( .gen_l(gi_l[9]), .pro_l(pi_l[9]), .ain(ai[9]), .bin(bi[9]));
pgnx_fa32 pg_8 ( .gen_l(gi_l[8]), .pro_l(pi_l[8]), .ain(ai[8]), .bin(bi[8]));
pgnx_fa32 pg_7 ( .gen_l(gi_l[7]), .pro_l(pi_l[7]), .ain(ai[7]), .bin(bi[7]));
pgnx_fa32 pg_6 ( .gen_l(gi_l[6]), .pro_l(pi_l[6]), .ain(ai[6]), .bin(bi[6]));
pgnx_fa32 pg_5 ( .gen_l(gi_l[5]), .pro_l(pi_l[5]), .ain(ai[5]), .bin(bi[5]));
pgnx_fa32 pg_4 ( .gen_l(gi_l[4]), .pro_l(pi_l[4]), .ain(ai[4]), .bin(bi[4]));
| This page: |
Created: | Wed Mar 24 09:43:31 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/custom_cells_behv.v
|