wire out1a, out2a, out3a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
endmodule
// -------------------- local4_inc10 -----------------------
![[Up: inc10 local6to9]](v2html-up.gif)
module local4_inc10
(in1, in2, in3, in4,
out1a, out2a, out3a, out4a);
input in1, in2, in3, in4;
output out1a, out2a, out3a, out4a;
wire out1a, out2a, out3a, out4a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
assign out4a = (in1 & in2 & in3) ^ in4;
endmodule
// -------------------- selout3_inc10 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selout3_inc10 (sel_l, out1, out2, out3,
out1a, out2a, out3a,
out1b, out2b, out3b);
input out1a, out2a, out3a,
out1b, out2b, out3b,
sel_l;
output out1, out2, out3;
wire out1, out2, out3;
assign out1 = ~sel_l ? out1a : out1b;
assign out2 = ~sel_l ? out2a : out2b;
assign out3 = ~sel_l ? out3a : out3b;
endmodule
// -------------------- selout4_inc10 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selout4_inc10 (sel_l, out1, out2, out3, out4,
out1a, out2a, out3a, out4a,
out1b, out2b, out3b, out4b);
input out1a, out2a, out3a, out4a,
out1b, out2b, out3b, out4b,
sel_l;
output out1, out2, out3, out4;
wire out1, out2, out3, out4;
assign out1 = ~sel_l ? out1a : out1b;
assign out2 = ~sel_l ? out2a : out2b;
assign out3 = ~sel_l ? out3a : out3b;
assign out4 = ~sel_l ? out4a : out4b;
endmodule
/***********28) OR7 gate *******************************/
module mj_s_or7 (in, out);
input [6:0] in;
output out;
assign out = |in[6:0];
endmodule
/***********29) OR5 gate *******************************/
module mj_s_or5 (in, out);
input [4:0] in;
output out;
assign out = |in[4:0];
endmodule
/***********30) OR12 gate *******************************/
module mj_s_or12 (in, out);
input [11:0] in;
output out;
assign out = |in[11:0];
endmodule
/***********31) OR12 gate *******************************/
module mj_s_and6 (in, out);
input [5:0] in;
output out;
assign out = &in[5:0];
endmodule
// ----------30) 30-bit bit_wise comparator -----------------------
module cmp30_e (ai, bi, a_eql_b);
input [29:0] ai;
input [29:0] bi;
output a_eql_b; // ai equal to bi.
assign a_eql_b = ( ai[29:0] == bi[29:0] ) ;
endmodule
// ----------32) 32-bit bit_wise comparator -----------------------
module cmp32_e (ai, bi, a_eql_b);
input [31:0] ai;
input [31:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[31:0] == bi[31:0] ) ;
*/
wire [31:0] bit_eql; // bit-wise equal output
wire [7:0] level_1; // 8-equal_not output
wire [3:0] level_2; // 4-equal
assign bit_eql[31:0] = ai[31:0] ^~ bi[31:0] ; // 32 2-in exnor, g10p "en".
assign level_1[7] = !(&bit_eql[31:28]); // 1 4-in "nd4".
assign level_1[6] = !(&bit_eql[27:24]); // 1 4-in "nd4".
assign level_1[5] = !(&bit_eql[23:20]); // 1 4-in "nd4".
assign level_1[4] = !(&bit_eql[19:16]); // 1 4-in "nd4".
assign level_1[3] = !(&bit_eql[15:12]); // 1 4-in "nd4".
assign level_1[2] = !(&bit_eql[11:8]); // 1 4-in "nd4".
assign level_1[1] = !(&bit_eql[7:4]); // 1 4-in "nd4".
assign level_1[0] = !(&bit_eql[3:0]); // 1 4-in "nd4".
assign level_2[3] = !(|level_1[7:6]); // 1 2-in "nr2".
assign level_2[2] = !(|level_1[5:4]); // 1 2-in "nr2".
assign level_2[1] = !(|level_1[3:2]); // 1 2-in "nr2".
assign level_2[0] = !(|level_1[1:0]); // 1 2-in "nr2".
assign a_eql_b = (&level_2[3:0]); // 1 2-in "and4".
endmodule
module comp_ge_8 (
in1,
in2,
ge );
input [7:0] in1;
input [7:0] in2;
output ge;
assign ge = (in1 >= in2 );
endmodule
/******Shells**********/
module cla_adder_32 (
in1,
in2,
cin,
sum,
cout
);
input [31:0] in1;
input [31:0] in2;
input cin;
output [31:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa32 i_fa32(.ai(in1),
.bi(in2),
.cin(cin),
.sum(sum),
.cout(cout)
);
endmodule
module comp_gle_32 (
in1,
in2,
gr,
ls,
eq
);
input [31:0] in1;
input [31:0] in2;
output gr;
output ls;
output eq;
/*
assign gr = (in1 > in2)?1'b1:1'b0;
assign ls = (in1 < in2)?1'b1:1'b0;
assign eq = (in1 == in2)?1'b1:1'b0;
*/
cmp3s_32_leg i_cmp3s_32_leg (.ai(in1), .bi(in2),
.a_ltn_b(ls), .a_eql_b(eq), .a_gtn_b(gr) );
endmodule
module cla_adder_16 (
in1,
in2,
cin,
sum,
cout
);
input [15:0] in1;
input [15:0] in2;
input cin;
output [15:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa16 i_fa16 ( .sum(sum), .cout(cout),
.a(in1), .b(in2), .c(cin));
endmodule
module cla_adder_28 (
in1,
in2,
cin,
sum,
cout
);
input [27:0] in1;
input [27:0] in2;
input cin;
output [27:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa28 i_fa28_dp ( .sum(sum), .cout(cout),
.ai(in1), .bi(in2), .cin(cin) );
endmodule
module comp_eq_32 (
in1,
in2,
eq
);
input [31:0] in1;
input [31:0] in2;
output eq;
/*assign eq = (in1==in2)?1'b1:1'b0;*/
cmp32_e i_cmp32_e (.ai(in1), .bi(in2), .a_eql_b(eq)
);
endmodule
// -------------------- increment_23 ------------------------------
module increment_23(cout,sum,in);
input [22:0] in;
output [22:0] sum;
output cout;
inc23 f_dpcl_inc23(.cout(cout),.sum(sum),.data(in));
// miss from dp_cells.v
// assign {cout,sum} = in + 1'h1;
endmodule
// ------------------- 23-bit incrementer --------------------------
module inc23 (data, sum, cout);
input [22:0] data;
output [22:0] sum;
output cout;
// use Kogge-Stone to design the logic
// -------------------- and tree level 1 ----------------------------
wire p22_20, p19_16, p15_12, p11_8, p7_4, p3_0_i;
lev1inc23 lev1tree ( .datain(data),
.propout({p22_20,
p19_16,
p15_12,
p11_8,
p7_4,
p3_0_i})
);
// -------------------- and tree level 2 ----------------------------
wire p22_12_l, p19_8_l, p15_4_l, p11_0_l, p7_0_l, p3_0;
lev2inc23 lev2tree ( .datain({p22_20,
p19_16,
p15_12,
p11_8,
p7_4,
p3_0_i}),
.propout({p22_12_l,
p19_8_l,
p15_4_l,
p11_0_l,
p7_0_l,
p3_0})
);
// -------------------- and tree level 3 ----------------------------
wire p22_0_l, p19_0_l, p15_0_l;
lev3inc23 lev3tree ( .datain({~p22_12_l,
~p19_8_l,
~p15_4_l,
~p11_0_l,
~p7_0_l,
p3_0}),
.propout({p22_0_l,
p19_0_l,
p15_0_l})
);
// -------------------- local propagates ---------------------------
wire [22:0] outa;
local4_inc23 local0to3 ( .in1(data[0]),
.in2(data[1]),
.in3(data[2]),
.in4(data[3]),
.out1a(outa[0]),
.out2a(outa[1]),
.out3a(outa[2]),
.out4a(outa[3]));
local4_inc23 local4to7 ( .in1(data[4]),
.in2(data[5]),
.in3(data[6]),
.in4(data[7]),
.out1a(outa[4]),
.out2a(outa[5]),
.out3a(outa[6]),
.out4a(outa[7]));
local4_inc23 local8to11 ( .in1(data[8]),
.in2(data[9]),
.in3(data[10]),
.in4(data[11]),
.out1a(outa[8]),
.out2a(outa[9]),
.out3a(outa[10]),
.out4a(outa[11]));
local4_inc23 local12to15 ( .in1(data[12]),
.in2(data[13]),
.in3(data[14]),
.in4(data[15]),
.out1a(outa[12]),
.out2a(outa[13]),
.out3a(outa[14]),
.out4a(outa[15]));
local4_inc23 local16to19 ( .in1(data[16]),
.in2(data[17]),
.in3(data[18]),
.in4(data[19]),
.out1a(outa[16]),
.out2a(outa[17]),
.out3a(outa[18]),
.out4a(outa[19]));
local3_inc23 local20to22 ( .in1(data[20]),
.in2(data[21]),
.in3(data[22]),
.out1a(outa[20]),
.out2a(outa[21]),
.out3a(outa[22]));
// -------------------- select output ---------------------------
selout4_inc23 selout3to0 ( .sel_l(1'b0),
.out1(sum[0]), .out2(sum[1]), .out3(sum[2]), .out4(sum[3]),
.out1a(outa[0]), .out2a(outa[1]), .out3a(outa[2]), .out4a(outa[3]),
.out1b(data[0]), .out2b(data[1]), .out3b(data[2]), .out4b(data[3]));
selout4_inc23 selout7to4 ( .sel_l(~p3_0),
.out1(sum[4]), .out2(sum[5]), .out3(sum[6]), .out4(sum[7]),
.out1a(outa[4]), .out2a(outa[5]), .out3a(outa[6]), .out4a(outa[7]),
.out1b(data[4]), .out2b(data[5]), .out3b(data[6]), .out4b(data[7]));
selout4_inc23 selout11to8 ( .sel_l(p7_0_l),
.out1(sum[8]), .out2(sum[9]), .out3(sum[10]), .out4(sum[11]),
.out1a(outa[8]), .out2a(outa[9]), .out3a(outa[10]), .out4a(outa[11]),
.out1b(data[8]), .out2b(data[9]), .out3b(data[10]), .out4b(data[11]));
selout4_inc23 selout12to15 ( .sel_l(p11_0_l),
.out1(sum[12]), .out2(sum[13]), .out3(sum[14]), .out4(sum[15]),
.out1a(outa[12]), .out2a(outa[13]), .out3a(outa[14]), .out4a(outa[15]),
.out1b(data[12]), .out2b(data[13]), .out3b(data[14]), .out4b(data[15]));
selout4_inc23 selout16to19 ( .sel_l(p15_0_l),
.out1(sum[16]), .out2(sum[17]), .out3(sum[18]), .out4(sum[19]),
.out1a(outa[16]), .out2a(outa[17]), .out3a(outa[18]), .out4a(outa[19]),
.out1b(data[16]), .out2b(data[17]), .out3b(data[18]), .out4b(data[19]));
selout3_inc23 selout20to22 ( .sel_l(p19_0_l),
.out1(sum[20]), .out2(sum[21]), .out3(sum[22]),
.out1a(outa[20]), .out2a(outa[21]), .out3a(outa[22]),
.out1b(data[20]), .out2b(data[21]), .out3b(data[22]));
assign cout = ~p22_0_l;
endmodule
// ***********end of incrementer top module ************
// -------------------- lev1-----------------------
module lev1inc23 (datain, propout);
input [22:0] datain;
output [5:0] propout;
wire [5:0] propout;
assign propout[0] = (datain[0] & datain[1] & datain[2] & datain[3]);
assign propout[1] = (datain[4] & datain[5] & datain[6] & datain[7]);
assign propout[2] = (datain[8] & datain[9] & datain[10] & datain[11]);
assign propout[3] = (datain[12] & datain[13] & datain[14] & datain[15]);
assign propout[4] = (datain[16] & datain[17] & datain[18] & datain[19]);
assign propout[5] = (datain[20] & datain[21] & datain[22]);
endmodule
// -------------------- lev2 -----------------------
module lev2inc23 (datain, propout);
input [5:0] datain;
output [5:0] propout;
wire [5:0] propout;
assign propout[0] = datain[0];
assign propout[1] = ~(datain[0] & datain[1]);
assign propout[2] = ~(datain[0] & datain[1] & datain[2]);
assign propout[3] = ~(datain[1] & datain[2] & datain[3]);
assign propout[4] = ~(datain[2] & datain[3] & datain[4]);
assign propout[5] = ~(datain[3] & datain[4] & datain[5]);
endmodule
// -------------------- lev3and -----------------------
module lev3inc23 (datain, propout);
input [5:0] datain;
output [2:0] propout;
wire [2:0] propout;
assign propout[0] = ~(datain[0] & datain[3]);
assign propout[1] = ~(datain[1] & datain[4]);
assign propout[2] = ~(datain[2] & datain[5]);
endmodule
// -------------------- local3_inc23 -----------------------
module local3_inc23 (in1, in2, in3,
out1a, out2a, out3a);
input in1, in2, in3;
output out1a, out2a, out3a;
wire out1a, out2a, out3a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
endmodule
// -------------------- local4_inc23 -----------------------
module local4_inc23 (in1, in2, in3, in4,
out1a, out2a, out3a, out4a);
input in1, in2, in3, in4;
output out1a, out2a, out3a, out4a;
wire out1a, out2a, out3a, out4a;
assign out1a = ~in1;
assign out2a = in1 ^ in2;
assign out3a = (in1 & in2) ^ in3;
assign out4a = (in1 & in2 & in3) ^ in4;
endmodule
// -------------------- selout3_inc23 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selout3_inc23 (sel_l, out1, out2, out3,
out1a, out2a, out3a,
out1b, out2b, out3b);
input out1a, out2a, out3a,
out1b, out2b, out3b,
sel_l;
output out1, out2, out3;
wire out1, out2, out3;
assign out1 = ~sel_l ? out1a : out1b;
assign out2 = ~sel_l ? out2a : out2b;
assign out3 = ~sel_l ? out3a : out3b;
endmodule
// -------------------- selout4_inc23 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selout4_inc23 (sel_l, out1, out2, out3, out4,
out1a, out2a, out3a, out4a,
out1b, out2b, out3b, out4b);
input out1a, out2a, out3a, out4a,
out1b, out2b, out3b, out4b,
sel_l;
output out1, out2, out3, out4;
wire out1, out2, out3, out4;
assign out1 = ~sel_l ? out1a : out1b;
assign out2 = ~sel_l ? out2a : out2b;
assign out3 = ~sel_l ? out3a : out3b;
assign out4 = ~sel_l ? out4a : out4b;
endmodule
module comp_ls_32 (
in1,
in2,
less
);
input [31:0] in1;
input [31:0] in2;
output less;
/*assign less = (in1<in2)?1'b1:1'b0; */
cmp32_ks_lt i_cmp32_ks_lt ( .ai(in1),
.bi(in2),
.a_ltn_b(less)
);
endmodule
module comp_gr_6 (
in1,
in2,
gr
);
input [5:0] in1;
input [5:0] in2;
output gr;
wire [5:0] in2_l;
/*assign gr = (in1 > in2);*/
gr6 i_gr6 ( .gr(gr),
.a(in1), .b(in2_l)
);
assign in2_l = ~in2 ;
endmodule
module cla_adder_6 (
in1,
in2,
cin,
sum,
cout
);
input [5:0] in1;
input [5:0] in2;
input cin;
output [5:0] sum;
output cout;
/*assign {cout,sum} = in1 + in2 + cin;*/
fa6 i_fa6 ( .sum(sum), .cout(cout),
.a(in1), .b(in2), .c(cin) );
endmodule
module comp_gr_32 (
in1,
in2,
gr
);
input [31:0] in1;
input [31:0] in2;
output gr;
/* assign gr = (in1>in2)?1'b1:1'b0; */
cmp32_ks_lt i_comp_gr_32 ( .ai(in2),
.bi(in1),
.a_ltn_b(gr)
);
endmodule
module incr_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
/* assign out = in + 1; */
inc32 i_incr_32 ( .ai(in),
.sum(out)
);
endmodule
module dec_32 (
in,
out
);
input [31:0] in;
output [31:0] out;
/* assign out = in - 1; */
dec32 i_dec_32 ( .ai(in),
.sum(out)
);
endmodule
module pencoder_16( trap_vec_c, ptrap_in_c);
input [15:0] trap_vec_c;
output [15:0] ptrap_in_c;
encoder16 i_pencoder_16 ( .ptrap_in_e(ptrap_in_c),
.trap_vec_e(trap_vec_c)
);
/**********************************************
reg [15:0] ptrap_in_c;
always @(trap_vec_c) begin
casex (trap_vec_c[15:0])
16'b1xxxxxxxxxxxxxxx : ptrap_in_c=16'h8000;
16'b01xxxxxxxxxxxxxx : ptrap_in_c=16'h4000;
16'b001xxxxxxxxxxxxx : ptrap_in_c=16'h2000;
16'b0001xxxxxxxxxxxx : ptrap_in_c=16'h1000;
16'b00001xxxxxxxxxxx : ptrap_in_c=16'h0800;
16'b000001xxxxxxxxxx : ptrap_in_c=16'h0400;
16'b0000001xxxxxxxxx : ptrap_in_c=16'h0200;
16'b00000001xxxxxxxx : ptrap_in_c=16'h0100;
16'b000000001xxxxxxx : ptrap_in_c=16'h0080;
16'b0000000001xxxxxx : ptrap_in_c=16'h0040;
16'b00000000001xxxxx : ptrap_in_c=16'h0020;
16'b000000000001xxxx : ptrap_in_c=16'h0010;
16'b0000000000001xxx : ptrap_in_c=16'h0008;
16'b00000000000001xx : ptrap_in_c=16'h0004;
16'b000000000000001x : ptrap_in_c=16'h0002;
16'b0000000000000001 : ptrap_in_c=16'h0001;
default : ptrap_in_c=16'h0000;
endcase
end
**********************************************/
endmodule
/*******************************************************************************
*
* Module: cmp_32
*
* This module contains the 32-bit comparator that can handle both signed
* and unsigned comparisons.
*
******************************************************************************/
module cmp_32(in1,
in2,
sign,
gt,
eq,
lt);
input [31:0] in1; // Operand on the LHS to be compared
input [31:0] in2; // Operand on the RHS to be compared
input sign; // 0: unsigned comparison, 1: signed comparison
output gt; // in1 > in2
output eq; // in1 == in2
output lt; // in1 < in2
cmp_legs_32 i_cmp_32 ( .gt(gt),
.eq(eq),
.lt(lt),
.in1(in1),
.in2(in2),
.sign(sign)
);
/******************************************************************
reg cmp_gt; // Intermediate result, in1 > in2
reg cmp_eq; // Intermediate result, in1 == in2
reg cmp_lt; // Intermediate result, in1 < in2
reg [31:0] tmp1; // 2's complement of in1
reg [31:0] tmp2; // 2's complement of in2
always @(in1 or in2 or sign)
begin
if (sign == 0)
begin
cmp_gt = (in1 > in2);
cmp_eq = (in1 == in2);
cmp_lt = (in1 < in2);
end // if (sign == 0)
else
begin
case ({in1[31], in2[31]})
2'b00:
begin
cmp_gt = (in1 > in2);
cmp_eq = (in1 == in2);
cmp_lt = (in1 < in2);
end // case: 2'b00
2'b01:
begin
cmp_gt = 1;
cmp_eq = 0;
cmp_lt = 0;
end // case: 2'b01
2'b10:
begin
cmp_gt = 0;
cmp_eq = 0;
cmp_lt = 1;
end // case: 2'b10
2'b11:
begin
tmp1 = (~in1) + 1;
tmp2 = (~in2) + 1;
cmp_gt = (tmp1 < tmp2);
cmp_eq = (in1 == in2);
cmp_lt = (tmp1 > tmp2);
end // case: 2'b11
endcase // case({in1[31], in2[31]})
end // else: !if(sign == 0)
end // always @ (in1 or in2 or sign)
assign gt = cmp_gt;
assign eq = cmp_eq;
assign lt = cmp_lt;
******************************************************************/
endmodule // cmp_32
/*******************************************************************************
*
* Module: cmp_eq_19
*
* This module implements 19-bit equality comparator
*
******************************************************************************/
module cmp_eq_19(in1,
in2,
eq
);
input [18:0] in1; // Operand 1 to be compared
input [18:0] in2; // Operand 2 to be compared
output eq; // 1 if in1 == in2, 0 otherwise
/* assign eq = (in1 == in2) ? 1'b1 : 1'b0; */
cmp20_e i_cmp_eq_19 ( .ai({1'b0,in1}),
.bi({1'b0,in2}),
.a_eql_b(eq)
);
endmodule // cmp_eq_19
/*******************************************************************************
*
* Module: ucmp_16
*
* This module implements unsigned 16-bit comparator with gt, eq, and lt outputs
*
******************************************************************************/
module ucmp_16(in1,
in2,
gt,
eq,
lt);
input [15:0] in1; // Operand 1 to be compared
input [15:0] in2; // Operand 2 to be compared
output gt; // in1 > in2
output eq; // in1 = in2
output lt; // in1 < in2
cmp3s_32_leg i_cmp3s_32_leg ( .ai({16'b0,in2}),
.bi({16'b0,in1}),
.a_ltn_b(gt),
.a_eql_b(eq),
.a_gtn_b(lt)
);
/*******************************************************
wire [16:0] op1; // in1 with leading 0
wire [16:0] op2; // in2 with leading 0
assign op1 = {1'b0, in1};
assign op2 = {1'b0, in2};
assign gt = (op1 > op2) ? 1'b1 : 1'b0;
assign eq = (op1 == op2) ? 1'b1 : 1'b0;
assign lt = (op1 < op2) ? 1'b1 : 1'b0;
*******************************************************/
endmodule // ucmp_16
/*******************************************************************************
*
* Module: cmp_eq_8
*
* This module implements 8-bit equality comparator
*
******************************************************************************/
module cmp_eq_8(in1,
in2,
eq
);
input [7:0] in1; // Operand 1 to be compared
input [7:0] in2; // Operand 2 to be compared
output eq; // 1 if in1 == in2, 0 otherwise
/* assign eq = (in1 == in2) ? 1'b1 : 1'b0; */
cmp16_e i_cmp_eq_8 ( .ai({8'b0,in1}),
.bi({8'b0,in2}),
.a_eql_b(eq)
);
endmodule // cmp_eq_8
/*******************************************************************************
*
* Module: cla_adder_8
*
* This module implements an 8-bit adder
*
******************************************************************************/
module cla_adder_8(in1,
in2,
cin,
sum,
cout
);
input [7:0] in1;
input [7:0] in2;
input cin;
output [7:0] sum;
output cout;
/* assign {cout,sum} = in1 + in2 + cin; */
fa8 i_fa8 ( .a(in1),
.b(in2),
.c(cin),
.sum(sum),
.cout(cout)
);
endmodule // cla_adder_8
// Use the following cells with caution
// These may not be available as megacells
module comp_le_32 (
in1,
in2,
le
);
input [31:0] in1;
input [31:0] in2;
output le;
wire gr;
/* assign le = (in1<=in2)?1'b1:1'b0; */
comp_gr_32 i_comp_le_32 ( .in1(in1),
.in2(in2),
.gr(gr)
);
assign le = ~gr ;
endmodule
module comp_ge_32 (
in1,
in2,
ge
);
input [31:0] in1;
input [31:0] in2;
output ge;
wire lt;
/* assign ge = (in1>=in2)?1'b1:1'b0; */
cmp32_ks_lt i_comp_ge_32 ( .ai(in1),
.bi(in2),
.a_ltn_b(lt)
);
assign ge = ~lt ;
endmodule
module mx21_32_l (mx_out, sel, in0, in1);
| This page: |
Created: | Wed Mar 24 09:43:43 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/custom_cells_behv.v
|