.clk(clk),
			      .enable(~hold_e),
			      .reset_l(reset_l));

// Mux select for scr1 of data adder
  assign adder_src1_mux_sel_r[1] = isub | ineg | 
				   (lsub & (first_cyc_r | second_cyc_r)) | 
				   (lneg & (first_cyc_r | second_cyc_r));
  assign adder_src1_mux_sel_r[0] = ~adder_src1_mux_sel_r[1]; 

  ff_sre_2   adder_src1_mux_sel_raw_ereg (.out(adder_src1_mux_sel_raw_e[1:0]),
				          .din(adder_src1_mux_sel_r[1:0]),
				          .clk(clk),
				          .enable(~hold_e),
				          .reset_l(reset_l));

  assign adder_src1_mux_sel[1] = adder_src1_mux_sel_raw_e[1] |
				 (~alu_adder_fn[1] & alu_adder_fn[0]);
  assign adder_src1_mux_sel[0] = ~(adder_src1_mux_sel[1]);

// Mux select for scr2 of data adder
  ff_sre   adder_src2_mux_sel_reg (.out(adder_src2_mux_sel_r),
				     .din(lneg|ineg),
				     .clk(clk),
				     .enable(~hold_e),
				     .reset_l(reset_l));
assign	adder_src2_mux_sel[2]	=	adder_src2_mux_sel_r&~ucode_busy_e;
assign	adder_src2_mux_sel[1]	=	ucode_busy_e&alu_adder_fn[1] & ~alu_adder_fn[0];
assign	adder_src2_mux_sel[0] 	=	~adder_src2_mux_sel[2]&~adder_src2_mux_sel[1];

// Ucode busy pipe.
  ff_sre   ucode_busy_e_reg (.out(ucode_busy_e),
			     .din(ucode_busy_r),
			     .clk(clk),
			     .enable(~hold_e),
			     .reset_l(reset_l));

 ff_sre   ucode_busy_c_reg (.out(ucode_busy_c),
                             .din(ucode_busy_e),
                             .clk(clk),
                             .enable(~hold_c),
                             .reset_l(reset_l));

// Mux select for branch address 
  assign iu_br_pc_mux_sel[2] = ucode_busy_e & ~reissue_c;
  assign iu_br_pc_mux_sel[1] = reissue_c;
  assign iu_br_pc_mux_sel[0] = ~(iu_br_pc_mux_sel[2] | iu_br_pc_mux_sel[1]);

   // Bit logic control
   assign bit_mux_sel_r[4] = fneg | dneg;
   assign bit_mux_sel_r[3] = jsr  | jsr_w;
   assign bit_mux_sel_r[2] = ixor | (lxor & (first_cyc_r | second_cyc_r));
   assign bit_mux_sel_r[1] = iand | land & (first_cyc_r | second_cyc_r);
   assign bit_mux_sel_r[0] = ~(|bit_mux_sel_r[4:1]);

   ff_sre_5 bit_mux_sel_reg (.out    (bit_mux_sel[4:0]),
			     .din    (bit_mux_sel_r[4:0]),
			     .enable (~hold_e),
			     .reset_l (reset_l),
			     .clk    (clk)
			     );

// Convert logic control
  assign cvt_mux_sel_r[4] = int2short; 
  assign cvt_mux_sel_r[3] = int2char; 
  assign cvt_mux_sel_r[2] = int2byte; 
  assign cvt_mux_sel_r[1] = i2l; 
  assign cvt_mux_sel_r[0] = ~(cvt_mux_sel_r[4] | cvt_mux_sel_r[3] |
				cvt_mux_sel_r[2] | cvt_mux_sel_r[1]); 

  ff_sre_5   cvt_mux_sel_reg (.out(cvt_mux_sel[4:0]),
			     .din(cvt_mux_sel_r[4:0]),
			     .clk(clk),
			     .reset_l(reset_l),
			     .enable(~hold_e)
			      );

   // Mux select for scr1 of shifter
   assign shifter_src1_mux_sel_r[4] = (lshr | lushr) & second_cyc_r;
   assign shifter_src1_mux_sel_r[3] = ishr;
   assign shifter_src1_mux_sel_r[2] = (lshr | lushr) & first_cyc_r;
   assign shifter_src1_mux_sel_r[1] = lshl & second_cyc_r;
   assign shifter_src1_mux_sel_r[0] = ~(|shifter_src1_mux_sel_r[4:1]);
   ff_sre_5 shifter_src1_mux_sel_reg (.out    (shifter_src1_mux_sel[4:0]),
				      .din    (shifter_src1_mux_sel_r[4:0]),
				      .enable (~hold_e),
				      .reset_l (reset_l),
				      .clk    (clk)
				      );

   // Mux select for scr2 of shifter
   assign shifter_src2_mux_sel_r[2] = lshl & second_cyc_r;
   assign shifter_src2_mux_sel_r[1] = ishl | (lshl & first_cyc_r) |
				      ishr | iushr | (lshr & second_cyc_r) |
				      (lushr & second_cyc_r);
   assign shifter_src2_mux_sel_r[0] = ~(|shifter_src2_mux_sel_r[2:1]);
   ff_sre_3 shifter_src2_mux_sel_reg (.out    (shifter_src2_mux_sel[2:0]),
				      .din    (shifter_src2_mux_sel_r[2:0]),
				      .enable (~hold_e),
				      .reset_l (reset_l),
				      .clk    (clk)
				      );

// Shifter word select MSW LSW 
  assign shifter_word_sel_r = (lshl & second_cyc_r) | (lshr & first_cyc_r) | 
			      (lushr & first_cyc_r); 

   ff_sre shifter_word_sel_flop(.out	(shifter_word_sel),
				.din	(shifter_word_sel_r),
				.enable	(~hold_e),
				.reset_l	(reset_l),
				.clk	(clk)
				);

   // Mux select for a 32 bits or 16 bits PC offset
   assign offset_mux_sel_r[4] = load_word_index | store_word_index |
				nastore_word_index;
   assign offset_mux_sel_r[3] = load_short_index | load_char_index |
				store_short_index;
   assign offset_mux_sel_r[2] = load_byte_index | load_ubyte_index |
				store_byte_index; 
   assign offset_mux_sel_r[1] = goto_w | jsr_w; 
   assign offset_mux_sel_r[0] = ~(|offset_mux_sel_r[4:1]);

   ff_sre_5 offset_mux_sel_reg (.out	(offset_mux_sel[4:0]),
				.din	(offset_mux_sel_r[4:0]),
				.enable	(~hold_e),
				.reset_l	(reset_l),
				.clk	(clk)
				);


mj_spare spare1( .clk(clk),
                .reset_l(reset_l));

mj_spare spare2( .clk(clk),
                .reset_l(reset_l));

 
endmodule



module branch_logic 
		(	
		 branch_qual,
		 cmp_eq_e,
		 cmp_gt_e,
	         cmp_lt_e,
		 reissue_c,
		 sc_dcache_req,
		 kill_inst_e,
		 iu_inst_raw_e,
		 inst_valid,
		 ucode_dcu_req,
		 ucode_busy_e,
		 iu_brtaken_e,
		 branch_taken_e,
		 iu_inst_e

);


input	[4:0]	branch_qual;
input		cmp_eq_e;
input		cmp_gt_e;
input		cmp_lt_e;
input		reissue_c;
input		sc_dcache_req;
input		kill_inst_e;
input	[3:2]	iu_inst_raw_e;
input		inst_valid;
input	[1:0]	ucode_dcu_req;
input		ucode_busy_e;

output		iu_brtaken_e;
output		branch_taken_e;
output	[3:2]	iu_inst_e;

wire	[3:2]	iu_inst_raw;
wire	[3:2]	ucode_inst_e;


assign	iu_brtaken_e 	=	branch_qual[4]& cmp_eq_e |
				branch_qual[3]&!cmp_eq_e |
				branch_qual[2]& cmp_gt_e |
				branch_qual[1]& cmp_lt_e |
				branch_qual[0] |reissue_c;

assign	branch_taken_e	 =      iu_brtaken_e;

assign iu_inst_e[3]	=  (ucode_dcu_req[1] & ~ucode_dcu_req[0]|iu_inst_raw_e[3])& ~sc_dcache_req & inst_valid;
assign iu_inst_e[2]	=  (ucode_dcu_req[0]| iu_inst_raw_e[2] | sc_dcache_req )
	  	           &inst_valid;

endmodule