wire iucmp_e
; // Latched iucmp signal
wire lcmp_e; // Latched lcmp signal
wire first_cyc_e; // Latched first_cyc_r signal
wire second_cyc_e; // Latched second_cyc_r signal
wire first_gt; // lcmp first cycle -> gt
wire first_eq; // lcmp first cycle -> eq
wire first_lt; // lcmp first cycle -> lt
wire second_gt; // lcmp second cycle -> gt
wire second_eq; // lcmp second cycle -> eq
wire second_lt; // lcmp second cycle -> lt
wire iucmp_gt; // iucmp -> gt
wire iucmp_eq; // iucmp -> eq
wire iucmp_lt; // iucmp -> lt
wire [5:0] shift_count_e1; // Intermediate shift count
wire [2:0] shift_count_mux_sel; // Select for shift_count_mux
wire shift_32_r; // Indicate it's a 32-bit shift instr.
wire shift_64_r; // Indicate it's a 64-bit shift instr.
wire shift_32_e; // Latched version of shift_32_r
wire shift_64_e; // Latched version of shift_64_r
wire load_store_e; // There is a ld/st to D$ in E stage
wire load_store_c; // There is a ld/st to D$ in C stage
wire iu_load_e; // load in E
wire iu_store_e; // store in E
wire smu_access; /* Latched smu_ld | smu_st to match
* smu_addr_d1
*/
wire mem_prot_ldst; /* Extended ld/st causes memory
* protection error exception.
*/
wire mem_prot_stack; /* Stack access causes memory
* protection error exception.
*/
wire [6:0] data_brk1_eq; /* bit 6: [31:13]
* bit 5: 12
* bit 4: [11:4]
* bit 3: 3
* bit 2: 2
* bit 1: 1
* bit 0: 0
*/
wire data_brk1_match_e; // Asserted if data_brk1_eq[6:0]==0x7f
wire [6:0] data_brk2_eq; /* bit 6: [31:13]
* bit 5: 12
* bit 4: [11:4]
* bit 3: 3
* bit 2: 2
* bit 1: 1
* bit 0: 0
*/
wire data_brk2_match_e; // Asserted if data_brk2_eq[6:0]==0x7f
wire [6:0] inst_brk1_eq; /* bit 6: [31:13]
* bit 5: 12
* bit 4: [11:4]
* bit 3: 3
* bit 2: 2
* bit 1: 1
* bit 0: 0
*/
wire inst_brk1_match; // Asserted if inst_brk1_eq[6:0]==0x7f
wire inst_brk1_taken; /* Inst breakpoint 1 will be taken after
* this signal is qualified with bit 31
* of BRK12C.
*/
wire [6:0] inst_brk2_eq; /* bit 6: [31:13]
* bit 5: 12
* bit 4: [11:4]
* bit 3: 3
* bit 2: 2
* bit 1: 1
* bit 0: 0
*/
wire inst_brk2_match; // Asserted if inst_brk2_eq[6:0]==0x7f
wire inst_brk2_taken; /* Inst breakpoint 2 will be taken after
* this signal is qualified with bit 31
* of BRK12C.
*/
/******************** monitor caching change *****************/
wire monitorenter_c; // monitorenter waits for lockbit from DCU in C stage
wire la0_null_c; // la0_null_e propagate to C stage
wire la1_null_c; // la1_null_e propagate to C stage
wire lock0_enter; // monitorenter hits on lockaddr0
wire lock0_exit; // monitorexit hits on lockaddr0
wire lock1_enter; // monitorenter hits on lockaddr1
wire lock1_exit; // monitorexit hits on lockaddr1
wire lock0_overflow; /* monitorenter hits on lockaddr0, and
* lockcount0 is 255
*/
wire lock0_underflow; /* monitorexit hits on lockaddr0, and
* lockcount0 is 0
*/
wire lock1_overflow; /* monitorenter hits on lockaddr1, and
* lockcount1 is 255
*/
wire lock1_underflow; /* monitorexit hits on lockaddr1, and
* lockcount1 is 0
*/
wire lock_miss_valid; /* monitorenter or monitorexit misses
* both lockaddr0 and lockaddr1,
* qualified with E stage inst_valid[0]
*/
wire lock0_release; /* monitorexit hits on lockaddr0, and
* lockcount0 - 1 == 0, and
* lockwant0 (bit 14) == 1
*/
wire lock1_release; /* monitorexit hits on lockaddr1, and
* lockcount1 - 1 == 0, and
* lockwant1 (bit 14) == 1
*/
wire nonnull_quick_e; // E stage nonnull_quick signal
wire curr_s; // Current state of the double-load FSM
wire next_s; // Next state of the double-load FSM
// Signals for mis-aligned exception
wire ldst_half_word_r, ldst_word_r; // Half word and word aligned ld/st in R
wire ldst_half_word_e, ldst_word_e; // Half word and word aligned ld/st in E
wire ldst_half_word_c, ldst_word_c; // Half word and word aligned ld/st in C
wire data_st_e;
wire data_brk1_vld_e,data_brk2_vld_e;
wire offset_branch_r,offset_branch_e,fpu_op_e;
// R-stage logic
ex_decode ex_decode(
.opcode_1_op_r (opcode_1_op_r[7:0]),
.opcode_2_op_r (opcode_2_op_r[7:0]),
.decodeout_1 (decodeout_1[255:0]),
.decodeout_2 (decodeout_2[255:0]),
.invalid_op_r (invalid_op_r),
.illegal_op_r (illegal_op_raw_r));
assign illegal_op_r = illegal_op_raw_r & valid_op_r;
// Output to IU for updating optop
assign wr_optop_r = (write_optop & first_cyc_r) |
(priv_update_optop & first_cyc_r);
ff_sre wr_optop_e_flop (.out (wr_optop_raw_e),
.din (wr_optop_r),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
assign wr_optop_e = (wr_optop_raw_e | ucode_wr_optop_e |
ucode_wr_vars_optop_e)&inst_valid[0];
assign ret_optop_update_e = all_return_e & wr_optop_e & ~hold_c;
ff_sr ret_optop_update_flop (.out (ret_optop_update),
.din (ret_optop_update_e),
.reset_l (reset_l),
.clk (clk)
);
// Output to IU if branch taken or not
ff_sre ifeq_e_flop (.out (ifeq_e),
.din (ifeq),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_icmpeq_e_flop (.out (if_icmpeq_e),
.din (if_icmpeq),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_acmpeq_e_flop (.out (if_acmpeq_e),
.din (if_acmpeq),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifge_e_flop (.out (ifge_e),
.din (ifge),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_icmpge_e_flop (.out (if_icmpge_e),
.din (if_icmpge),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifle_e_flop (.out (ifle_e),
.din (ifle),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_icmple_e_flop (.out (if_icmple_e),
.din (if_icmple),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifnull_e_flop (.out (ifnull_e),
.din (ifnull),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifne_e_flop (.out (ifne_e),
.din (ifne),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_icmpne_e_flop (.out (if_icmpne_e),
.din (if_icmpne),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_acmpne_e_flop (.out (if_acmpne_e),
.din (if_acmpne),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifnonnull_e_flop (.out (ifnonnull_e),
.din (ifnonnull),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre ifgt_e_flop (.out (ifgt_e),
.din (ifgt),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre if_icmpgt_e_flop (.out(if_icmpgt_e),
.din(if_icmpgt),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre iflt_e_flop (.out(iflt_e),
.din(iflt),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre if_icmplt_e_flop (.out(if_icmplt_e),
.din(if_icmplt),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre goto_e_flop (.out(goto_e),
.din(goto),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre goto_w_e_flop (.out(goto_w_e),
.din(goto_w),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre jsr_e_flop (.out(jsr_e),
.din(jsr),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre jsr_w_e_flop (.out(jsr_w_e),
.din(jsr_w),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre write_pc_e_flop (.out(write_pc_e),
.din(write_pc),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre ret_e_flop (.out(ret_e),
.din(ret),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre priv_powerdown_flop (.out(priv_powerdown_raw_e),
.din(priv_powerdown),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign priv_powerdown_e = priv_powerdown_raw_e & inst_valid[0];
ff_sre priv_reset_flop (.out(priv_reset_raw_e),
.din(priv_reset),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign priv_reset_e = priv_reset_raw_e & inst_valid[0] & psr_su;
assign all_return_r = ireturn | lreturn | freturn | dreturn | areturn | return
| priv_ret_from_trap | return0 | return1 | return2;
ff_sre all_return_flop (.out(all_return_e),
.din(all_return_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
// branch is asserted only when there is no hold_e due to loaduse or scache rd miss.
// this avoids asserting incorrect brtaken_e even though, there was no branch.
/***
assign iu_brtaken_e = (((ifeq_e | if_icmpeq_e | if_acmpeq_e | ifge_e | if_icmpge_e |
ifle_e | if_icmple_e | ifnull_e) & cmp_eq_e) |
((ifne_e | if_icmpne_e | if_acmpne_e | ifnonnull_e) & ~cmp_eq_e) |
((ifge_e | if_icmpge_e | ifgt_e | if_icmpgt_e) & cmp_gt_e) |
((iflt_e | ifle_e | if_icmplt_e | if_icmple_e) & cmp_lt_e) |
goto_e | goto_w_e | jsr_e | jsr_w_e | write_pc_e | ret_e)
& inst_valid[0]&~kill_inst_e | ucode_wr_pc_e&inst_valid[0]| reissue_c;
***/
// Modify logic for timing purposes.
assign branch_qual[4] = (ifeq_e | if_icmpeq_e | if_acmpeq_e | ifge_e | if_icmpge_e|
ifle_e | if_icmple_e | ifnull_e)&inst_valid[0]&~kill_inst_e;
assign branch_qual[3] = (ifne_e | if_icmpne_e | if_acmpne_e | ifnonnull_e)&inst_valid[0]&~kill_inst_e;
assign branch_qual[2] = (ifge_e | if_icmpge_e | ifgt_e | if_icmpgt_e)&inst_valid[0]&~kill_inst_e ;
assign branch_qual[1] = (iflt_e | ifle_e | if_icmplt_e | if_icmple_e)&inst_valid[0]&~kill_inst_e ;
assign branch_qual[0] = (goto_e | goto_w_e | jsr_e | jsr_w_e | write_pc_e | ret_e|ucode_wr_pc_e)&
inst_valid[0]&~kill_inst_e;
branch_logic branch_logic(
.branch_qual (branch_qual[4:0]),
.cmp_eq_e (cmp_eq_e),
.cmp_gt_e (cmp_gt_e),
.cmp_lt_e (cmp_lt_e),
.reissue_c (reissue_c),
.sc_dcache_req (sc_dcache_req),
.kill_inst_e (kill_inst_e),
.iu_inst_raw_e (iu_inst_raw_e[3:2]),
.inst_valid (inst_valid[0]),
.ucode_busy_e (ucode_busy_e),
.ucode_dcu_req (ucode_dcu_req[1:0]),
.iu_brtaken_e (iu_brtaken_e),
.branch_taken_e (branch_taken_e),
.iu_inst_e (iu_inst_e[3:2])
);
// Output to DCU
assign iu_inst_r[7] = nastore_word_index;
assign iu_inst_r[6] = load_char_oe | load_short_oe | load_word_oe |
ncload_char_oe | ncload_short_oe | ncload_word_oe |
store_short_oe | store_word_oe | ncstore_short_oe |
ncstore_word_oe;
assign iu_inst_r[5] = ~(load_char_index | load_ubyte_index |
load_ubyte | load_char | load_char_oe |
ncload_ubyte | ncload_char | ncload_char_oe);
assign iu_inst_r[4] = ncload_ubyte | ncload_byte | ncload_char |
ncload_short | ncload_word | ncload_char_oe |
ncload_short_oe | ncload_word_oe | ncstore_byte |
ncstore_short | ncstore_word | ncstore_short_oe |
ncstore_word_oe;
assign iu_inst_r[3] = store_word_index | nastore_word_index |
store_short_index | store_byte_index |
store_byte | store_short | store_word |
store_short_oe | store_word_oe | ncstore_byte |
ncstore_short | ncstore_word | ncstore_short_oe |
ncstore_word_oe;
assign iu_inst_r[2] = load_word_index | load_short_index | load_char_index |
load_byte_index | load_ubyte_index | load_ubyte |
load_byte | load_char | load_short | load_word |
load_char_oe | load_short_oe | load_word_oe |
ncload_ubyte | ncload_byte | ncload_char |
ncload_short | ncload_word | ncload_char_oe |
ncload_short_oe | ncload_word_oe;
// iu_inst_e[1:0] for size 2'b00 => byte, 2'b01 => half word and 2'b10 => word
assign iu_inst_r[1] = load_word_index | store_word_index | nastore_word_index |
load_word | load_word_oe | ncload_word | ncload_word_oe |
store_word | store_word_oe | ncstore_word |
ncstore_word_oe;
assign iu_inst_r[0] = load_short_index | store_short_index | load_short |
load_short_oe | ncload_short | ncload_short_oe |
store_short | store_short_oe | ncstore_short |
ncstore_short_oe | load_char_index | load_char |
load_char_oe | ncload_char | ncload_char_oe;
ff_sre_8 iu_inst_e_reg (.out(iu_inst_raw_e[7:0]),
.din(iu_inst_r[7:0]),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l)
);
assign iu_inst_raw[7] = iu_inst_raw_e[7] & ~sc_dcache_req;
assign iu_inst_raw[6] = (iu_inst_raw_e[6] ^ iu_addr_e[30]) & ~sc_dcache_req;
assign iu_inst_raw[5] = iu_inst_raw_e[5] | sc_dcache_req;
assign iu_inst_raw[4] = (iu_inst_raw_e[4] | (iu_addr_e[29] & iu_addr_e[28]))
& ~sc_dcache_req ;
assign iu_inst_raw[1] = iu_inst_raw_e[1] | sc_dcache_req | monitorenter_e;
assign iu_inst_raw[0] = iu_inst_raw_e[0] & ~sc_dcache_req;
ff_sre_3 baload_e_reg(.out({baload_e,saload_e,caload_e}),
.din({baload,saload,caload}),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l)
);
ff_sre_3 bastore_e_reg(.out({bastore_e,sastore_e,castore_e}),
.din({bastore,sastore,castore}),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l)
);
// For ucode, when there is an array_load_e, then need to look at
// the instruction to determine the size.by default, size is word.
// need sign extension for saload and baload instructions.
assign array_load_e = ucode_dcu_req[1] & ucode_dcu_req[0];
assign ucode_st_e = ucode_dcu_req[1] & ~ucode_dcu_req[0];
assign ucode_inst_e[7:6] = 2'b00;
assign ucode_inst_e[5] = saload_e | baload_e ;
assign ucode_inst_e[4] = 1'b0 ;
assign ucode_inst_e[1:0]= (baload_e&array_load_e |
bastore_e&ucode_st_e)? 2'b00:
(saload_e|caload_e)&array_load_e |
(sastore_e|castore_e)&ucode_st_e?2'b01:
2'b10 ;
mux2_6 iu_inst_e_mux(.out ({iu_inst_e[7:4],iu_inst_e[1:0]}),
.in1 ({ucode_inst_e[7:4],ucode_inst_e[1:0]}),
.in0 ({iu_inst_raw[7:4],iu_inst_raw[1:0]}),
.sel (iu_inst_e_mux_sel[1:0])
);
assign iu_inst_e_mux_sel[1] = ucode_busy_e & ~sc_dcache_req;
assign iu_inst_e_mux_sel[0] = ~iu_inst_e_mux_sel[1];
assign iu_store_e = iu_inst_e[3] ;
assign iu_load_e = iu_inst_e[2] ;
// Keep track there is a any normal load or diag load in C stage
assign all_load_e = iu_load_e | iu_d_diag_e[0] | iu_d_diag_e[2] |
iu_i_diag_e[0] | iu_i_diag_e[2];
ff_sre all_load_c_flop (.out(all_load_c_raw),
.din(all_load_e),
.clk(clk),
.enable(~hold_c),
.reset_l(reset_l));
assign all_load_c = all_load_c_raw & inst_valid[1];
// Signals to ICU
assign iu_icu_flush_r = cache_flush | cache_index_flush | cache_invalidate;
ff_sre iu_icu_flush_e_flop (.out(iu_icu_flush_raw_e),
.din(iu_icu_flush_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_icu_flush_e = iu_icu_flush_raw_e & inst_valid[0] & psr_ice;
// Signals to DCU
assign iu_dcu_flush_r[2] = cache_flush;
assign iu_dcu_flush_r[1] = cache_index_flush;
assign iu_dcu_flush_r[0] = cache_invalidate;
ff_sre_3 iu_dcu_flush_e_flop (.out(iu_dcu_flush_raw_e[2:0]),
.din(iu_dcu_flush_r[2:0]),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_dcu_flush_e[2:0] = iu_dcu_flush_raw_e[2:0] & {3{inst_valid[0]}} & {3{psr_dce}};
assign iu_zero_r = zero_line & valid_op_r;
ff_sre iu_zero_e_flop (.out(iu_zero_raw_e),
.din(iu_zero_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_zero_e = iu_zero_raw_e & inst_valid[0];
wire iu_special_r,iu_special_raw_e;
assign iu_special_r = (|iu_dcu_flush_r[2:0])|zero_line | (|iu_d_diag_r[3:0]) ;
ff_sre iu_special_e_ff (.out(iu_special_raw_e),
.din(iu_special_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_special_e = iu_special_raw_e&inst_valid[0];
// Take zero_line E-trap in E stage
assign zero_trap_e = iu_zero_e & (~psr_dce | zero_addr_e[29]&zero_addr_e[28]);
assign iu_d_diag_r[3] = priv_write_dcache_data;
assign iu_d_diag_r[2] = priv_read_dcache_data;
assign iu_d_diag_r[1] = priv_write_dcache_tag;
assign iu_d_diag_r[0] = priv_read_dcache_tag;
ff_sre_4 iu_d_diag_e_reg (.out(iu_d_diag_raw_e[3:0]),
.din(iu_d_diag_r[3:0]),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_e)
);
assign iu_d_diag_e[3:0] = iu_d_diag_raw_e[3:0] & {4{inst_valid[0]}};
assign iu_i_diag_r[3] = priv_write_icache_data;
assign iu_i_diag_r[2] = priv_read_icache_data&first_cyc_r;
assign iu_i_diag_r[1] = priv_write_icache_tag;
assign iu_i_diag_r[0] = priv_read_icache_tag&first_cyc_r;
ff_sre_4 iu_i_diag_e_reg (.out(iu_i_diag_raw_e[3:0]),
.din(iu_i_diag_r[3:0]),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_e)
);
assign iu_i_diag_e[3:0] = iu_i_diag_raw_e[3:0] & {4{inst_valid[0]}};
// Decode the emulated trap opcodes
assign emulated_trap_r = (ldiv
| lmul
| lrem
| ldc
| ldc_w
| ldc2_w
| getstatic
| putstatic
| getfield
| putfield
| new
| newarray
| anewarray
| checkcast
| instanceof
| multianewarray
| new_quick
| anewarray_quick
| multianewarray_quick
| invokevirtual
| invokenonvirtual
| invokestatic
| invokeinterface
| invokeinterface_quick
// | invokevirtualobject_quick
| putfield_quick_w
| getfield_quick_w
| aastore
| athrow
| breakpoint
| lookupswitch
| wide
| (drem & psr_drt)
| invalid_op_r ) & valid_op_r
;
ff_sre_8 opcode_1_op_e_reg (.out(opcode_1_op_e[7:0]),
.din(opcode_1_op_r[7:0]),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l)
);
ff_sre_8 opcode_1_op_c_reg (.out(opcode_1_op_c[7:0]),
.din(opcode_1_op_e[7:0]),
.clk(clk),
.enable(~hold_c),
.reset_l(reset_l)
);
assign soft_trap_r = soft_trap & valid_op_r;
// The ucoded instructions:
assign ucode_op_r = (iaload
| laload
| faload
| daload
| aaload
| baload
| caload
| saload
| aastore_quick
| iastore
| lastore
| fastore
| dastore
| bastore
| castore
| sastore
| dup_x1
| dup_x2
| dup2
| dup2_x1
| dup2_x2
| swap
| tableswitch
| ireturn
| lreturn
| freturn
| dreturn
| areturn
| return
| arraylength
| ldc_quick
| ldc_w_quick
| ldc2_w_quick
| getfield_quick
| putfield_quick
| getfield2_quick
| putfield2_quick
| getstatic_quick
| putstatic_quick
| getstatic2_quick
| putstatic2_quick
| invokevirtual_quick
| invokenonvirtual_quick
| invokesuper_quick
| invokestatic_quick
| invokevirtual_quick_w
| checkcast_quick
| instanceof_quick
| agetfield_quick
| aputfield_quick
| agetstatic_quick
| aputstatic_quick
| aldc_quick
| aldc_w_quick
| exit_sync_method
| priv_ret_from_trap
| return0
| return1
| return2
| get_current_class
| call ) & valid_op_r;
assign priv_inst_r = (priv_ret_from_trap |
priv_read_dcache_tag |
priv_read_dcache_data |
priv_read_icache_tag |
priv_read_icache_data |
priv_powerdown |
priv_write_dcache_tag |
priv_write_dcache_data |
priv_write_icache_tag |
priv_write_icache_data |
priv_reset |
priv_update_optop |
priv_read_oplim |
priv_read_psr |
priv_read_trapbase |
priv_read_lockcount0 |
priv_read_lockcount1 |
priv_read_lockaddr0 |
priv_read_lockaddr1 |
priv_read_userrange1 |
priv_read_gc_config |
priv_read_brk1a |
priv_read_brk2a |
priv_read_brk12c |
priv_read_userrange2 |
priv_read_versionid |
priv_read_hcr |
priv_read_sc_bottom |
priv_write_oplim |
priv_write_psr |
priv_write_trapbase |
priv_write_lockcount0 |
priv_write_lockcount1 |
priv_write_lockaddr0 |
priv_write_lockaddr1 |
priv_write_userrange1 |
priv_write_gc_config |
priv_write_brk1a |
priv_write_brk2a |
priv_write_brk12c |
priv_write_userrange2 |
priv_write_sc_bottom) & valid_op_r & (~psr_su);
assign ldst_half_word_r = load_short_index |
load_char_index |
load_char |
load_short |
load_char_oe |
load_short_oe |
ncload_char |
ncload_short |
ncload_char_oe |
ncload_short_oe |
store_short_index |
store_short |
store_short_oe |
ncstore_short |
ncstore_short_oe;
ff_sre ldst_half_word_e_flop (.out(ldst_half_word_e),
.din(ldst_half_word_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre ldst_half_word_c_flop (.out(ldst_half_word_c),
.din(ldst_half_word_e),
.clk(clk),
.enable(~hold_c),
.reset_l(reset_l));
assign ldst_word_r = load_word_index |
load_word |
load_word_oe |
ncload_word |
ncload_word_oe |
store_word_index |
nastore_word_index |
store_word |
store_word_oe |
ncstore_word |
ncstore_word_oe;
ff_sre ldst_word_e_flop (.out(ldst_word_e),
.din(ldst_word_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
ff_sre ldst_word_c_flop (.out(ldst_word_c),
.din(ldst_word_e),
.clk(clk),
.enable(~hold_c),
.reset_l(reset_l));
assign mis_align_c = ((iu_addr_c[0] & (ldst_half_word_c | ldst_word_c)) |
(iu_addr_c[1] & ldst_word_c)) & inst_valid[1];
assign ucode_busy_r = ~ucode_done | ucode_op_r| iu_trap_r;
// Bypass logic
assign iu_bypass_rs2_r = ucode_op_r |
fpu_op_r |
iadd |
ladd |
isub |
lsub |
imul |
idiv |
irem |
ishl |
lshl |
ishr |
lshr |
iushr |
lushr |
iand |
land |
ior |
lor |
ixor |
lxor |
lcmp |
if_icmpeq |
if_icmpne |
if_icmplt |
if_icmpge |
if_icmpgt |
if_icmple |
if_acmpeq |
if_acmpne |
store_word_index |
nastore_word_index |
store_short_index |
store_byte_index |
iucmp |
cache_invalidate |
cache_flush |
cache_index_flush |
store_byte |
store_short |
store_word |
priv_write_dcache_tag |
priv_write_dcache_data |
store_short_oe |
store_word_oe |
priv_write_icache_tag |
priv_write_icache_data |
ncstore_byte |
ncstore_short |
ncstore_word |
ncstore_short_oe |
ncstore_word_oe |
priv_update_optop ;
assign iu_bypass_rs1_r = ucode_op_r | ~(
emulated_trap_r |
illegal_op_r |
nop |
aconst_null |
iconst_m1 |
iconst_0 |
iconst_1 |
iconst_2 |
iconst_3 |
iconst_4 |
iconst_5 |
lconst_0 |
lconst_1 |
fconst_0 |
fconst_1 |
fconst_2 |
dconst_0 |
dconst_1 |
bipush |
sipush |
pop |
pop2 |
l2i |
goto |
jsr |
goto_w |
jsr_w |
priv_powerdown |
priv_reset |
read_pc |
read_vars |
read_frame |
read_optop |
priv_read_oplim |
read_const_pool |
priv_read_psr |
priv_read_trapbase |
priv_read_lockcount0 |
priv_read_lockcount1 |
priv_read_lockaddr0 |
priv_read_lockaddr1 |
priv_read_userrange1 |
priv_read_gc_config |
priv_read_brk1a |
priv_read_brk2a |
priv_read_brk12c |
priv_read_userrange2 |
priv_read_versionid |
priv_read_hcr |
priv_read_sc_bottom |
read_global0 |
read_global1 |
read_global2 |
soft_trap |
read_global3 );
ff_sre iu_bypass_rs1_flop (.out(iu_bypass_rs1),
.din(iu_bypass_rs1_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_bypass_rs1_e = iu_bypass_rs1 & inst_valid[0];
ff_sre iu_bypass_rs2_flop (.out(iu_bypass_rs2),
.din(iu_bypass_rs2_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign iu_bypass_rs2_e = iu_bypass_rs2 & inst_valid[0];
// FPU opcodes
assign fpu_op_r = (fadd | dadd | fsub | dsub | fmul | dmul |
fdiv | ddiv | frem | drem | i2f | i2d |
l2f | l2d | f2i | f2l | d2i | d2l | f2d |
d2f | fcmpg | fcmpl | dcmpg | dcmpl) & valid_op_r;
// Re-extract the decode outputs from ex_decode.v
assign nop = decodeout_1[0];
assign aconst_null = decodeout_1[1];
assign iconst_m1 = decodeout_1[2];
assign iconst_0 = decodeout_1[3];
assign iconst_1 = decodeout_1[4];
assign iconst_2 = decodeout_1[5];
assign iconst_3 = decodeout_1[6];
assign iconst_4 = decodeout_1[7];
assign iconst_5 = decodeout_1[8];
assign lconst_0 = decodeout_1[9];
assign lconst_1 = decodeout_1[10];
assign fconst_0 = decodeout_1[11];
assign fconst_1 = decodeout_1[12];
assign fconst_2 = decodeout_1[13];
assign dconst_0 = decodeout_1[14];
assign dconst_1 = decodeout_1[15];
assign bipush = decodeout_1[16];
assign sipush = decodeout_1[17];
assign ldc = decodeout_1[18];
assign ldc_w = decodeout_1[19];
assign ldc2_w = decodeout_1[20];
assign iload = decodeout_1[21];
assign lload = decodeout_1[22];
assign fload = decodeout_1[23];
assign dload = decodeout_1[24];
assign aload = decodeout_1[25];
assign iload_0 = decodeout_1[26];
assign iload_1 = decodeout_1[27];
assign iload_2 = decodeout_1[28];
assign iload_3 = decodeout_1[29];
assign lload_0 = decodeout_1[30];
assign lload_1 = decodeout_1[31];
assign lload_2 = decodeout_1[32];
assign lload_3 = decodeout_1[33];
assign fload_0 = decodeout_1[34];
assign fload_1 = decodeout_1[35];
assign fload_2 = decodeout_1[36];
assign fload_3 = decodeout_1[37];
assign dload_0 = decodeout_1[38];
assign dload_1 = decodeout_1[39];
assign dload_2 = decodeout_1[40];
assign dload_3 = decodeout_1[41];
assign aload_0 = decodeout_1[42];
assign aload_1 = decodeout_1[43];
assign aload_2 = decodeout_1[44];
assign aload_3 = decodeout_1[45];
assign iaload = decodeout_1[46];
assign laload = decodeout_1[47];
assign faload = decodeout_1[48];
assign daload = decodeout_1[49];
assign aaload = decodeout_1[50];
assign baload = decodeout_1[51];
assign caload = decodeout_1[52];
assign saload = decodeout_1[53];
assign istore = decodeout_1[54];
assign lstore = decodeout_1[55];
assign fstore = decodeout_1[56];
assign dstore = decodeout_1[57];
assign astore = decodeout_1[58];
assign istore_0 = decodeout_1[59];
assign istore_1 = decodeout_1[60];
assign istore_2 = decodeout_1[61];
assign istore_3 = decodeout_1[62];
assign lstore_0 = decodeout_1[63];
assign lstore_1 = decodeout_1[64];
assign lstore_2 = decodeout_1[65];
assign lstore_3 = decodeout_1[66];
assign fstore_0 = decodeout_1[67];
assign fstore_1 = decodeout_1[68];
assign fstore_2 = decodeout_1[69];
assign fstore_3 = decodeout_1[70];
assign dstore_0 = decodeout_1[71];
assign dstore_1 = decodeout_1[72];
assign dstore_2 = decodeout_1[73];
assign dstore_3 = decodeout_1[74];
assign astore_0 = decodeout_1[75];
assign astore_1 = decodeout_1[76];
assign astore_2 = decodeout_1[77];
assign astore_3 = decodeout_1[78];
assign iastore = decodeout_1[79];
assign lastore = decodeout_1[80];
assign fastore = decodeout_1[81];
assign dastore = decodeout_1[82];
assign aastore = decodeout_1[83];
assign bastore = decodeout_1[84];
assign castore = decodeout_1[85];
assign sastore = decodeout_1[86];
assign pop = decodeout_1[87];
assign pop2 = decodeout_1[88];
assign dup = decodeout_1[89];
assign dup_x1 = decodeout_1[90];
assign dup_x2 = decodeout_1[91];
assign dup2 = decodeout_1[92];
assign dup2_x1 = decodeout_1[93];
assign dup2_x2 = decodeout_1[94];
assign swap = decodeout_1[95];
| This page: |
Created: | Wed Mar 24 09:45:00 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/iu/ex/rtl/ex_ctl.v
|