assign g = !(gd_l & gu_l); //nand to make pseudo generate
endmodule
// -------------------- pg2l ----------------------------
// ling modification stage, psuedo group generate and propagate
![[Up: fa16 p2gl0]](v2html-up.gif)
module pg2l_fa16
(gd_l, gu_l, pd_l, pu_l, g, p);
input gd_l, gu_l, pd_l, pu_l;
output g, p;
assign g = !(gd_l & gu_l); //nand to make pseudo generate
assign p = !(pd_l | pu_l); //nor to make pseudo generate
endmodule
// -------------------- aoig ----------------------------
// aoi for carry tree generates
module aoig_fa16 (gd, gu, pu, g_l);
input gd, gu, pu;
output g_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
endmodule
// -------------------- oaig ----------------------------
// aoi for carry tree generates
module oaig_fa16 (gd_l, gu_l, pu_l, g);
input gd_l, gu_l, pu_l;
output g;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
endmodule
// -------------------- baoi ----------------------------
// aoi for carry tree generates + logic for propagate
module baoi_fa16 (gd, gu, pd, pu, g_l, p_l);
input gd, gu, pd, pu;
output g_l, p_l;
assign g_l = ~((gd & pu) | gu); //aoi to make group generate
assign p_l = ~(pd & pu); // nand to make group prop
endmodule
// -------------------- boai ----------------------------
// aoi for carry tree generates
module boai_fa16 (gd_l, gu_l, pd_l, pu_l, g, p);
input gd_l, gu_l, pu_l, pd_l;
output g, p;
assign g = ~((gd_l | pu_l) & gu_l); //aoi to make group generate
assign p = ~(pu_l | pd_l); // nor to make group prop
endmodule
// ------------------- 9) 16-bit bit_wise comparator -----------------------
module cmp16_e (ai, bi, a_eql_b);
input [15:0] ai;
input [15:0] bi;
output a_eql_b; // ai equal to bi.
/* Logic
assign a_eql_b = ( ai[15:0] == bi[15:0] ) ;
*/
wire [15:0] ben; // bit-wise equal_not output
wire [7:0] lv1; // 8-equal output
wire [3:0] lv2; // 4-equal_not output
wire [1:0] lv3; // 2-equal output
/* Behaviral model's performence is at 1.14 ns.*/
assign ben[15:0] = ai[15:0] ^ bi[15:0] ; // 16 2-in exor, g10p "eo".
assign lv1[3] = !(|ben[15:12]); // 1 4-in "nr4".
assign lv1[2] = !(|ben[11:8]); // 1 4-in "nr4".
assign lv1[1] = !(|ben[7:4]); // 1 4-in "nr4".
assign lv1[0] = !(|ben[3:0]); // 1 4-in "nr4".
assign lv2[1] = !(&lv1[3:2]); // 1 2-in "nd2".
assign lv2[0] = !(&lv1[1:0]); // 1 2-in "nd2".
assign a_eql_b = !(|lv2[1:0]); // 1 2-in "nr2".
endmodule
// -------------------10) 16-bit all_zero comparator -----------------------
module cmp16zero (ai, a_eql_z);
input [15:0] ai;
output a_eql_z; // ai equal to all_zero.
/* Logic
assign a_eql_z = ( ai[15:0] == 16'b0 ) ;
*/
/*Behaviral model's performence is at 1.28 ns.*/
wire [15:0] bit_eql; // bit-wise equal output
wire [ 3:0] level_1; // 8-equal_not output
wire [ 1:0] level_2; // 4-equal
assign bit_eql[15:0] = ~ai[15:0] ; // 16 "n1a".
assign level_1[3] = !(&bit_eql[15:12]); // 1 4-in "nd4".
assign level_1[2] = !(&bit_eql[11:8]); // 1 4-in "nd4".
assign level_1[1] = !(&bit_eql[7:4]); // 1 4-in "nd4".
assign level_1[0] = !(&bit_eql[3:0]); // 1 4-in "nd4".
assign level_2[1] = !(|level_1[3:2]); // 1 2-in "nr2".
assign level_2[0] = !(|level_1[1:0]); // 1 2-in "nr2".
assign a_eql_z = (&level_2[1:0]); // 1 2-in "and4".
endmodule
// --11) Leading zero detector block, continous leading zeros numbers output --
module lbd32 (zr_num, di);
output [ 5:0] zr_num;
input [31:0] di;
reg [3:0] b3_num, b2_num, b1_num, b0_num;
reg w5, w4, w3, w2, w1, w0;
/* Logic */
always @ ( di )
begin
casex (di[31:24]) //synopsys parallel_case
8'b00000000: b3_num = 4'b1000 ; // 8 zeros
8'b00000001: b3_num = 4'b0111 ; // 7 zeros
8'b0000001x: b3_num = 4'b0110 ; // 6 zeros
8'b000001xx: b3_num = 4'b0101 ; // 5 zeros
8'b00001xxx: b3_num = 4'b0100 ; // 4 zeros
8'b0001xxxx: b3_num = 4'b0011 ; // 3 zeros
8'b001xxxxx: b3_num = 4'b0010 ; // 2 zeros
8'b01xxxxxx: b3_num = 4'b0001 ; // 1 zero
8'b1xxxxxxx: b3_num = 4'b0000 ; // none
default: b3_num = 4'bxxxx ;
endcase
casex (di[23:16]) //synopsys parallel_case
8'b00000000: b2_num = 4'b1000 ;
8'b00000001: b2_num = 4'b0111 ;
8'b0000001x: b2_num = 4'b0110 ;
8'b000001xx: b2_num = 4'b0101 ;
8'b00001xxx: b2_num = 4'b0100 ;
8'b0001xxxx: b2_num = 4'b0011 ;
8'b001xxxxx: b2_num = 4'b0010 ;
8'b01xxxxxx: b2_num = 4'b0001 ;
8'b1xxxxxxx: b2_num = 4'b0000 ;
default: b2_num = 4'bxxxx ;
endcase
casex (di[15:8]) //synopsys parallel_case
8'b00000000: b1_num = 4'b1000 ;
8'b00000001: b1_num = 4'b0111 ;
8'b0000001x: b1_num = 4'b0110 ;
8'b000001xx: b1_num = 4'b0101 ;
8'b00001xxx: b1_num = 4'b0100 ;
8'b0001xxxx: b1_num = 4'b0011 ;
8'b001xxxxx: b1_num = 4'b0010 ;
8'b01xxxxxx: b1_num = 4'b0001 ;
8'b1xxxxxxx: b1_num = 4'b0000 ;
default: b1_num = 4'bxxxx ;
endcase
casex (di[7:0]) //synopsys parallel_case
8'b00000000: b0_num = 4'b1000 ; // 8 zero
8'b00000001: b0_num = 4'b0111 ; // 7 zero
8'b0000001x: b0_num = 4'b0110 ; // 6 zero
8'b000001xx: b0_num = 4'b0101 ; // 5 zero
8'b00001xxx: b0_num = 4'b0100 ; // 4 zero
8'b0001xxxx: b0_num = 4'b0011 ; // 3 zero
8'b001xxxxx: b0_num = 4'b0010 ; // 2 zero
8'b01xxxxxx: b0_num = 4'b0001 ; // 1 zero
8'b1xxxxxxx: b0_num = 4'b0000 ; // 0 zero
default: b0_num = 4'bxxxx ;
endcase
end
always @ ( b3_num or b2_num or b1_num or b0_num )
begin
casex ({~b3_num[3],~b2_num[3],~b1_num[3],~b0_num[3]}) //synopsys parallel_case
4'b0000: begin
{w5,w4,w3,w2,w1,w0} = 6'b100000 ; // select b3_num same as b0_num. both 0
end
4'b0001: begin
{w5,w4,w3} = 3'b011 ; // select b0_num
{w2,w1,w0} = b0_num[2:0] ; // 0
end
4'b001x: begin
{w5,w4,w3} = 3'b010 ; // select b1_num
{w2,w1,w0} = b1_num[2:0] ; // 1
end
4'b01xx: begin
{w5,w4,w3} = 3'b001 ; // select b2_num
{w2,w1,w0} = b2_num[2:0] ; // 2
end
4'b1xxx: begin
{w5,w4,w3} = 3'b000 ; // select b3_num
{w2,w1,w0} = b3_num[2:0] ; // 3
end
default: {w5,w4,w3,w2,w1,w0} = 6'bxxxxxx ;
endcase
end
assign zr_num[5:0] = {w5,w4,w3,w2,w1,w0} ; // pack outputs
endmodule
// -------------------12) 28-bit full adder -----------------------------------
// ------------------- Kogge-Stone style -----------------------------------
module fa28 (ai, bi, cin, sum, cout);
input [27:0] ai, bi;
input cin;
output [27:0] sum;
output cout;
wire [27:0] gi_l; // bit-wise generate carry output
wire [27:0] pi_l; // bit-wise propgate carry output
wire gen1_l;
wire g27_26, g25_24, g23_22, g21_20, g19_18, g17_16, g15_14,
g13_12, g11_10, g9_8, g7_6, g5_4, g3_2, g1_0;
wire p26_25, p24_23, p22_21, p20_19, p18_17, p16_15, p14_13,
p12_11, p10_9, p8_7, p6_5, p4_3, p2_1;
wire g27_24_l, g23_20_l, g19_16_l, g15_12_l, g11_8_l, g7_4_l, g3_0_l;
wire p26_23_l, p22_19_l, p18_15_l, p14_11_l, p10_7_l, p6_3_l;
wire g27_20, g23_16, g19_12, g15_8, g11_4, g7_0;
wire p26_19, p22_15, p18_11, p14_7, p10_3;
wire g27_12_l, g23_8_l, g19_4_l, g15_0_l, g11_0_l;
wire p26_11_l, p22_7_l, p18_3_l;
wire g27_0, g23_0, g19_0;
wire w2_3_0, w3i_7_0, w3i_3_0, w4_15_0, w4_11_0, w4_7_0, w4_3_0;
wire [27:0] in, inb;
wire [27:0] sum;
assign gen1_l = ~ (ai[0] & bi[0]);
pgnx28 pg_27 ( .gen_l(gi_l[27]), .pro_l(pi_l[27]), .ain(ai[27]), .bin(bi[27]));
pgnx28 pg_26 ( .gen_l(gi_l[26]), .pro_l(pi_l[26]), .ain(ai[26]), .bin(bi[26]));
pgnx28 pg_25 ( .gen_l(gi_l[25]), .pro_l(pi_l[25]), .ain(ai[25]), .bin(bi[25]));
pgnx28 pg_24 ( .gen_l(gi_l[24]), .pro_l(pi_l[24]), .ain(ai[24]), .bin(bi[24]));
pgnx28 pg_23 ( .gen_l(gi_l[23]), .pro_l(pi_l[23]), .ain(ai[23]), .bin(bi[23]));
pgnx28 pg_22 ( .gen_l(gi_l[22]), .pro_l(pi_l[22]), .ain(ai[22]), .bin(bi[22]));
pgnx28 pg_21 ( .gen_l(gi_l[21]), .pro_l(pi_l[21]), .ain(ai[21]), .bin(bi[21]));
pgnx28 pg_20 ( .gen_l(gi_l[20]), .pro_l(pi_l[20]), .ain(ai[20]), .bin(bi[20]));
pgnx28 pg_19 ( .gen_l(gi_l[19]), .pro_l(pi_l[19]), .ain(ai[19]), .bin(bi[19]));
pgnx28 pg_18 ( .gen_l(gi_l[18]), .pro_l(pi_l[18]), .ain(ai[18]), .bin(bi[18]));
pgnx28 pg_17 ( .gen_l(gi_l[17]), .pro_l(pi_l[17]), .ain(ai[17]), .bin(bi[17]));
pgnx28 pg_16 ( .gen_l(gi_l[16]), .pro_l(pi_l[16]), .ain(ai[16]), .bin(bi[16]));
pgnx28 pg_15 ( .gen_l(gi_l[15]), .pro_l(pi_l[15]), .ain(ai[15]), .bin(bi[15]));
pgnx28 pg_14 ( .gen_l(gi_l[14]), .pro_l(pi_l[14]), .ain(ai[14]), .bin(bi[14]));
pgnx28 pg_13 ( .gen_l(gi_l[13]), .pro_l(pi_l[13]), .ain(ai[13]), .bin(bi[13]));
pgnx28 pg_12 ( .gen_l(gi_l[12]), .pro_l(pi_l[12]), .ain(ai[12]), .bin(bi[12]));
pgnx28 pg_11 ( .gen_l(gi_l[11]), .pro_l(pi_l[11]), .ain(ai[11]), .bin(bi[11]));
pgnx28 pg_10 ( .gen_l(gi_l[10]), .pro_l(pi_l[10]), .ain(ai[10]), .bin(bi[10]));
pgnx28 pg_9 ( .gen_l(gi_l[9]), .pro_l(pi_l[9]), .ain(ai[9]), .bin(bi[9]));
pgnx28 pg_8 ( .gen_l(gi_l[8]), .pro_l(pi_l[8]), .ain(ai[8]), .bin(bi[8]));
pgnx28 pg_7 ( .gen_l(gi_l[7]), .pro_l(pi_l[7]), .ain(ai[7]), .bin(bi[7]));
pgnx28 pg_6 ( .gen_l(gi_l[6]), .pro_l(pi_l[6]), .ain(ai[6]), .bin(bi[6]));
pgnx28 pg_5 ( .gen_l(gi_l[5]), .pro_l(pi_l[5]), .ain(ai[5]), .bin(bi[5]));
pgnx28 pg_4 ( .gen_l(gi_l[4]), .pro_l(pi_l[4]), .ain(ai[4]), .bin(bi[4]));
pgnx28 pg_3 ( .gen_l(gi_l[3]), .pro_l(pi_l[3]), .ain(ai[3]), .bin(bi[3]));
pgnx28 pg_2 ( .gen_l(gi_l[2]), .pro_l(pi_l[2]), .ain(ai[2]), .bin(bi[2]));
pgnx28 pg_1 ( .gen_l(gi_l[1]), .pro_l(pi_l[1]), .ain(ai[1]), .bin(bi[1]));
pgnl28 pg_0 ( .gen_l(gi_l[0]), .pro_l(pi_l[0]), .ain(ai[0]), .bin(bi[0]), .carryin(cin));
/* pg2 stage */
pg2_fa28 pg_27_26 ( .g_u_d(g27_26),
.p_u_d(p26_25),
.g_l_in(gi_l[27:26]),
.p_l_in(pi_l[26:25]));
pg2_fa28 pg_25_24 ( .g_u_d(g25_24),
.p_u_d(p24_23),
.g_l_in(gi_l[25:24]),
.p_l_in(pi_l[24:23]));
pg2_fa28 pg_23_22 ( .g_u_d(g23_22),
.p_u_d(p22_21),
.g_l_in(gi_l[23:22]),
.p_l_in(pi_l[22:21]));
pg2_fa28 pg_21_20 ( .g_u_d(g21_20),
.p_u_d(p20_19),
.g_l_in(gi_l[21:20]),
.p_l_in(pi_l[20:19]));
pg2_fa28 pg_19_18 ( .g_u_d(g19_18),
.p_u_d(p18_17),
.g_l_in(gi_l[19:18]),
.p_l_in(pi_l[18:17]));
pg2_fa28 pg_17_16 ( .g_u_d(g17_16),
.p_u_d(p16_15),
.g_l_in(gi_l[17:16]),
.p_l_in(pi_l[16:15]));
pg2_fa28 pg_15_14 ( .g_u_d(g15_14),
.p_u_d(p14_13),
.g_l_in(gi_l[15:14]),
.p_l_in(pi_l[14:13]));
pg2_fa28 pg_13_12 ( .g_u_d(g13_12),
.p_u_d(p12_11),
.g_l_in(gi_l[13:12]),
.p_l_in(pi_l[12:11]));
pg2_fa28 pg_11_10 ( .g_u_d(g11_10),
.p_u_d(p10_9),
.g_l_in(gi_l[11:10]),
.p_l_in(pi_l[10:9]));
pg2_fa28 pg_9_8 ( .g_u_d(g9_8),
.p_u_d(p8_7),
.g_l_in(gi_l[9:8]),
.p_l_in(pi_l[8:7]));
pg2_fa28 pg_7_6 ( .g_u_d(g7_6),
.p_u_d(p6_5),
.g_l_in(gi_l[7:6]),
.p_l_in(pi_l[6:5]));
pg2_fa28 pg_5_4 ( .g_u_d(g5_4),
.p_u_d(p4_3),
.g_l_in(gi_l[5:4]),
.p_l_in(pi_l[4:3]));
pg2_fa28 pg_3_2 ( .g_u_d(g3_2),
.p_u_d(p2_1),
.g_l_in(gi_l[3:2]),
.p_l_in(pi_l[2:1]));
assign g1_0 = ~ (gi_l[1] & gi_l[0]);
/* b1 stage */
b1aoi_fa28 pg_27_24 ( .ggrp_l(g27_24_l),
.pgrp_l(p26_23_l),
.gu_in(g27_26),
.pu_in(p26_25),
.gd_in(g25_24),
.pd_in(p24_23));
b1aoi_fa28 pg_23_20 ( .ggrp_l(g23_20_l),
.pgrp_l(p22_19_l),
.gu_in(g23_22),
.pu_in(p22_21),
.gd_in(g21_20),
.pd_in(p20_19));
b1aoi_fa28 pg_19_16 ( .ggrp_l(g19_16_l),
.pgrp_l(p18_15_l),
.gu_in(g19_18),
.pu_in(p18_17),
.gd_in(g17_16),
.pd_in(p16_15));
b1aoi_fa28 pg_15_12 ( .ggrp_l(g15_12_l),
.pgrp_l(p14_11_l),
.gu_in(g15_14),
.pu_in(p14_13),
.gd_in(g13_12),
.pd_in(p12_11));
b1aoi_fa28 pg_11_8 ( .ggrp_l(g11_8_l),
.pgrp_l(p10_7_l),
.gu_in(g11_10),
.pu_in(p10_9),
.gd_in(g9_8),
.pd_in(p8_7));
b1aoi_fa28 pg_7_4 ( .ggrp_l(g7_4_l),
.pgrp_l(p6_3_l),
.gu_in(g7_6),
.pu_in(p6_5),
.gd_in(g5_4),
.pd_in(p4_3));
g1aoi_fa28 g_3_0 ( .ggrp_l(g3_0_l),
.gu_in(g3_2),
.pu_in(p2_1),
.gd_in(g1_0));
/* b2 stage */
b2oai_fa28 pg_27_20 ( .ggrp(g27_20),
.pgrp(p26_19),
.gu_in(g27_24_l),
.pu_in(p26_23_l),
.gd_in(g23_20_l),
.pd_in(p22_19_l));
b2oai_fa28 pg_23_16 ( .ggrp(g23_16),
.pgrp(p22_15),
.gu_in(g23_20_l),
.pu_in(p22_19_l),
.gd_in(g19_16_l),
.pd_in(p18_15_l));
b2oai_fa28 pg_19_12 ( .ggrp(g19_12),
.pgrp(p18_11),
.gu_in(g19_16_l),
.pu_in(p18_15_l),
.gd_in(g15_12_l),
.pd_in(p14_11_l));
b2oai_fa28 pg_15_8 ( .ggrp(g15_8),
.pgrp(p14_7),
.gu_in(g15_12_l),
.pu_in(p14_11_l),
.gd_in(g11_8_l),
.pd_in(p10_7_l));
b2oai_fa28 pg_11_4 ( .ggrp(g11_4),
.pgrp(p10_3),
.gu_in(g11_8_l),
.pu_in(p10_7_l),
.gd_in(g7_4_l),
.pd_in(p6_3_l));
g2oai_fa28 g_7_0 ( .ggrp(g7_0),
.gu_in(g7_4_l),
.pu_in(p6_3_l),
.gd_in(g3_0_l));
assign w2_3_0 = ~ g3_0_l;
/* b3 stage */
b3aoi_fa28 pg_27_12 ( .ggrp_l(g27_12_l),
.pgrp_l(p26_11_l),
.gu_in(g27_20),
.pu_in(p26_19),
.gd_in(g19_12),
.pd_in(p18_11));
b3aoi_fa28 pg_23_8 ( .ggrp_l(g23_8_l),
.pgrp_l(p22_7_l),
.gu_in(g23_16),
.pu_in(p22_15),
.gd_in(g15_8),
.pd_in(p14_7));
b3aoi_fa28 pg_19_4 ( .ggrp_l(g19_4_l),
.pgrp_l(p18_3_l),
.gu_in(g19_12),
.pu_in(p18_11),
.gd_in(g11_4),
.pd_in(p10_3));
g3aoi_fa28 g_15_0 ( .ggrp_l(g15_0_l),
.gu_in(g15_8),
.pu_in(p14_7),
.gd_in(g7_0));
g3aoi_fa28 g_11_0 ( .ggrp_l(g11_0_l),
.gu_in(g11_4),
.pu_in(p10_3),
.gd_in(w2_3_0));
assign w3i_7_0 = ~ g7_0;
assign w3i_3_0 = ~ w2_3_0;
/* g4 stage */
g4oai_fa28 g_27_0 ( .ggrp(g27_0),
.gu_in(g27_12_l),
.pu_in(p26_11_l),
.gd_in(g11_0_l));
g4oai_fa28 g_23_0 ( .ggrp(g23_0),
.gu_in(g23_8_l),
.pu_in(p22_7_l),
.gd_in(w3i_7_0));
g4oai_fa28 g_19_0 ( .ggrp(g19_0),
.gu_in(g19_4_l),
.pu_in(p18_3_l),
.gd_in(w3i_3_0));
assign w4_15_0 = ~ g15_0_l;
assign w4_11_0 = ~ g11_0_l;
assign w4_7_0 = ~ w3i_7_0;
assign w4_3_0 = ~ w3i_3_0;
/* Local Sum, Carry-select stage */
presum_fa28 psum27_24 (.g1(~gi_l[24]), .g2(~gi_l[25]), .g3(~gi_l[26]), .g4(~gi_l[27]),
.p0(~pi_l[23]), .p1(~pi_l[24]), .p2(~pi_l[25]), .p3(~pi_l[26]), .p4(~pi_l[27]),
.s1(in[24]), .s2(in[25]), .s3(in[26]), .s4(in[27]),
.s1b(inb[24]), .s2b(inb[25]), .s3b(inb[26]), .s4b(inb[27]));
presum_fa28 psum23_20 (.g1(~gi_l[20]), .g2(~gi_l[21]), .g3(~gi_l[22]), .g4(~gi_l[23]),
.p0(~pi_l[19]), .p1(~pi_l[20]), .p2(~pi_l[21]), .p3(~pi_l[22]), .p4(~pi_l[23]),
.s1(in[20]), .s2(in[21]), .s3(in[22]), .s4(in[23]),
.s1b(inb[20]), .s2b(inb[21]), .s3b(inb[22]), .s4b(inb[23]));
presum_fa28 psum19_16 (.g1(~gi_l[16]), .g2(~gi_l[17]), .g3(~gi_l[18]), .g4(~gi_l[19]),
.p0(~pi_l[15]), .p1(~pi_l[16]), .p2(~pi_l[17]), .p3(~pi_l[18]), .p4(~pi_l[19]),
.s1(in[16]), .s2(in[17]), .s3(in[18]), .s4(in[19]),
.s1b(inb[16]), .s2b(inb[17]), .s3b(inb[18]), .s4b(inb[19]));
presum_fa28 psum15_12 (.g1(~gi_l[12]), .g2(~gi_l[13]), .g3(~gi_l[14]), .g4(~gi_l[15]),
.p0(~pi_l[11]), .p1(~pi_l[12]), .p2(~pi_l[13]), .p3(~pi_l[14]), .p4(~pi_l[15]),
.s1(in[12]), .s2(in[13]), .s3(in[14]), .s4(in[15]),
.s1b(inb[12]), .s2b(inb[13]), .s3b(inb[14]), .s4b(inb[15]));
presum_fa28 psum11_8 (.g1(~gi_l[8]), .g2(~gi_l[9]), .g3(~gi_l[10]), .g4(~gi_l[11]),
.p0(~pi_l[7]), .p1(~pi_l[8]), .p2(~pi_l[9]), .p3(~pi_l[10]), .p4(~pi_l[11]),
.s1(in[8]), .s2(in[9]), .s3(in[10]), .s4(in[11]),
.s1b(inb[8]), .s2b(inb[9]), .s3b(inb[10]), .s4b(inb[11]));
presum_fa28 psum7_4 (.g1(~gi_l[4]), .g2(~gi_l[5]), .g3(~gi_l[6]), .g4(~gi_l[7]),
.p0(~pi_l[3]), .p1(~pi_l[4]), .p2(~pi_l[5]), .p3(~pi_l[6]), .p4(~pi_l[7]),
.s1(in[4]), .s2(in[5]), .s3(in[6]), .s4(in[7]),
.s1b(inb[4]), .s2b(inb[5]), .s3b(inb[6]), .s4b(inb[7]));
presum_fa28 psum3_0 (.g1(~gen1_l), .g2(~gi_l[1]), .g3(~gi_l[2]), .g4(~gi_l[3]),
.p0(1'b1), .p1(~pi_l[0]), .p2(~pi_l[1]), .p3(~pi_l[2]), .p4(~pi_l[3]),
.s1(in[0]), .s2(in[1]), .s3(in[2]), .s4(in[3]),
.s1b(inb[0]), .s2b(inb[1]), .s3b(inb[2]), .s4b(inb[3]));
/* Sum stage */
sum4s_fa28 sum27_24 (.csel(g23_0), .sin1(in[24]), .sin2(in[25]), .sin3(in[26]), .sin4(in[27]),
.sin1b(inb[24]), .sin2b(inb[25]), .sin3b(inb[26]), .sin4b(inb[27]),
.sum1(sum[24]), .sum2(sum[25]), .sum3(sum[26]), .sum4(sum[27]));
sum4s_fa28 sum23_20 (.csel(g19_0), .sin1(in[20]), .sin2(in[21]), .sin3(in[22]), .sin4(in[23]),
.sin1b(inb[20]), .sin2b(inb[21]), .sin3b(inb[22]), .sin4b(inb[23]),
.sum1(sum[20]), .sum2(sum[21]), .sum3(sum[22]), .sum4(sum[23]));
sum4s_fa28 sum19_16 (.csel(w4_15_0), .sin1(in[16]), .sin2(in[17]), .sin3(in[18]), .sin4(in[19]),
.sin1b(inb[16]), .sin2b(inb[17]), .sin3b(inb[18]), .sin4b(inb[19]),
.sum1(sum[16]), .sum2(sum[17]), .sum3(sum[18]), .sum4(sum[19]));
sum4s_fa28 sum15_12 (.csel(w4_11_0), .sin1(in[12]), .sin2(in[13]), .sin3(in[14]), .sin4(in[15]),
.sin1b(inb[12]), .sin2b(inb[13]), .sin3b(inb[14]), .sin4b(inb[15]),
.sum1(sum[12]), .sum2(sum[13]), .sum3(sum[14]), .sum4(sum[15]));
sum4s_fa28 sum11_8 (.csel(w4_7_0), .sin1(in[8]), .sin2(in[9]), .sin3(in[10]), .sin4(in[11]),
.sin1b(inb[8]), .sin2b(inb[9]), .sin3b(inb[10]), .sin4b(inb[11]),
.sum1(sum[8]), .sum2(sum[9]), .sum3(sum[10]), .sum4(sum[11]));
sum4s_fa28 sum7_4 (.csel(w4_3_0), .sin1(in[4]), .sin2(in[5]), .sin3(in[6]), .sin4(in[7]),
.sin1b(inb[4]), .sin2b(inb[5]), .sin3b(inb[6]), .sin4b(inb[7]),
.sum1(sum[4]), .sum2(sum[5]), .sum3(sum[6]), .sum4(sum[7]));
sum4s_fa28 sum3_0 (.csel(cin), .sin1(in[0]), .sin2(in[1]), .sin3(in[2]), .sin4(in[3]),
.sin1b(inb[0]), .sin2b(inb[1]), .sin3b(inb[2]), .sin4b(inb[3]),
.sum1(sum[0]), .sum2(sum[1]), .sum3(sum[2]), .sum4(sum[3]));
assign cout = (~pi_l[27]) & g27_0;
endmodule
/* pgnx28 */
module pgnx28 (gen_l, pro_l, ain, bin);
output gen_l;
output pro_l;
input ain;
input bin;
assign gen_l = ~ (ain & bin);
assign pro_l = ~ (ain | bin);
endmodule
/* pgnl28 */
module pgnl28 (gen_l, pro_l, ain, bin, carryin);
output gen_l;
output pro_l;
input ain;
input bin;
input carryin;
assign gen_l = ~ ((ain & bin) | (carryin & (ain | bin)));
assign pro_l = ~ (ain | bin);
endmodule
/* pg2 stage */
module pg2_fa28 (g_u_d, p_u_d, g_l_in, p_l_in);
output g_u_d; // carry_generated.
output p_u_d; // carry_propgated. lower 1-bit
input [1:0] g_l_in; // generate inputs.
input [1:0] p_l_in; // propgate inputs. lower 1-bit
/* Ling modification used here */
assign g_u_d = ~ (g_l_in[1] & g_l_in[0]); // 2-bit pseudo generate.
assign p_u_d = ~ (p_l_in[1] | p_l_in[0]); // 2-bit pseudo propagate.
endmodule
/* g2 stage */
module g2_fa28 (g_u_d, g_l_in);
output g_u_d; // carry_generated.
input [1:0] g_l_in; // generate inputs.
/* Ling modification used here */
assign g_u_d = ~ (g_l_in[1] & g_l_in[0]); // 2-bit pseudo generate.
endmodule
/* B1AOI stage */
module b1aoi_fa28 (ggrp_l, pgrp_l, gu_in, pu_in, gd_in, pd_in);
output ggrp_l; // group generate.
output pgrp_l; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
assign pgrp_l = ~ (pu_in & pd_in); // group propagate. lower 1-bit
endmodule
/* G1AOI stage */
module g1aoi_fa28 (ggrp_l, gu_in, pu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
endmodule
/* B3AOI stage */
module b3aoi_fa28 (ggrp_l, pgrp_l, gu_in, pu_in, gd_in, pd_in);
output ggrp_l; // group generate.
output pgrp_l; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
assign pgrp_l = ~ (pu_in & pd_in); // group propagate. lower 1-bit
endmodule
/* G3AOI stage */
module g3aoi_fa28 (ggrp_l, gu_in, pu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
endmodule
/* B2OAI stage */
module b2oai_fa28 (ggrp, pgrp, gu_in, pu_in, gd_in, pd_in);
output ggrp; // group generate.
output pgrp; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
assign pgrp = ~ (pu_in | pd_in); // group propagate. lower 1-bit
endmodule
/* G2OAI stage */
module g2oai_fa28 (ggrp, gu_in, pu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
endmodule
/* G4OAI stage */
module g4oai_fa28 (ggrp, gu_in, pu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
endmodule
/* Sum stage logic. Carry-select approach is used */
module sum4s_fa28 (csel, sin1, sin2, sin3, sin4, sin1b, sin2b, sin3b, sin4b, sum1, sum2, sum3, sum4);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inputs assuming csel=0
input csel; // global carry input.
/* carry-select approach used here */
assign sum1 = csel == 1 ? sin1 : sin1b;
assign sum2 = csel == 1 ? sin2 : sin2b;
assign sum3 = csel == 1 ? sin3 : sin3b;
assign sum4 = csel == 1 ? sin4 : sin4b;
endmodule
module presum_fa28 (g1, g2, g3, g4, p0, p1, p2, p3, p4, s1, s2, s3, s4, s1b, s2b, s3b, s4b);
input g1, g2, g3, g4, p0, p1, p2, p3, p4;
output s1, s2, s3, s4;
output s1b, s2b, s3b, s4b;
assign s1 = (p1 & (~g1)) ^ p0;
assign s2 = (p2 & (~g2)) ^ (g1 | (p1 & p0));
assign s3 = (p3 & (~g3)) ^ (g2 | ((g1 | (p1 & p0)) & p2));
assign s4 = (p4 & (~g4)) ^ (g3 | ((g2 | ((g1 | (p1 & p0)) & p2)) & p3));
assign s1b = p1 & (~g1);
assign s2b = (p2 & (~g2)) ^ g1;
assign s3b = (p3 & (~g3)) ^ (g2 | (g1 & p2));
assign s4b = (p4 & (~g4)) ^ (g3 | (g2 | (g1 & p2)) & p3);
endmodule
// --13) Left shifter, 63-bit input, 0~31 positions, output 32-bit --
module lsft31_63i_32o (lsf_out, hi, lo, lsa);
output [31:0] lsf_out;
input [31:0] hi;
input [31:1] lo;
input [4:0] lsa;
/* Logic
assign lsf[62:0] = {hi[31:0],lo[31:1]} << lsa[4:0] ;
assign lsf_out[31:0] = lsf[62:31];
*/
// The following module has indentical functionality as above assignment.
// It should be used in circuit design.
// Only lvl_0[46:16] portion is two loads to inputs and the other two portions
// has one loading to previous stage.
// If inverting mux provides better timing and area than non_inverting one,the
// inverting type mux should be used, and a row of inverting output buffer
// should be provided.
// Total of 47+39+35+33+32 = 186 2:1 muxs.
// Implementation tips: lev_1 through lev_5 indicates 5-level of two_to_one mux
// structure which can be implemented differently by using 4:1 or even 8:1 mux
// if over all area and timing can be improved. Circuit group have the
// flexibility to implemente it differently. Adequate buffering should be
// provided on lsa pins, especially on rsa[4] and rsa[3] pins.
wire [62:0] lvl_0; // level 0 wiring.
wire [46:0] lvl_1; // level_1 47-bit 2:1 mux output
wire [38:0] lvl_2; // level_2 39-bit 2:1 mux output
wire [34:0] lvl_3; // level_3 35-bit 2:1 mux output
wire [32:0] lvl_4; // level_4 33-bit 2:1 mux output
wire [31:0] lvl_5; // level_5 32-bit 2:1 mux output
wire [ 4:0] mux_sel; // internal buffering;
assign mux_sel[4:0] = ~lsa[4:0] ; // inverting & buffering once for left shift.
// wiring lvl_0.
assign lvl_0[62:0] = {hi[31:0],lo[31:1]};
assign lvl_1 = ~((mux_sel[4]) ? (lvl_0[62:16]) : (lvl_0[46:0]) );
assign lvl_2 = ~((mux_sel[3]) ? (lvl_1[46: 8]) : (lvl_1[38:0]) );
assign lvl_3 = ~((mux_sel[2]) ? (lvl_2[38: 4]) : (lvl_2[34:0]) );
assign lvl_4 = ~((mux_sel[1]) ? (lvl_3[34: 2]) : (lvl_3[32:0]) );
assign lvl_5 = ~((mux_sel[0]) ? (lvl_4[32: 1]) : (lvl_4[31:0]) );
assign lsf_out[31:0] = ~lvl_5;
endmodule
//-14)Right shifter, 63-bit input, 0~31 positions, output 32-bit,with sticky --
module rsft31_63i_32o (rsf_out, gbit, sticky, nxstin, hi, lo, rsa, stin);
output [31:0] rsf_out;
output gbit; // 1 bit below LSB of result.
output sticky; // 2-bit below LSB
output nxstin; // Or of GBIT and STICKY
input [30:0] hi;
input [31:0] lo;
input [4:0] rsa;
input stin; // Input from prevoius STICKY
assign gbit = 1'b0; // no connection for now.
assign nxstin = 1'b0; // no connection for now.
/* Logic
assign rsf_out[31:0] = {hi[30:0],lo[31:0]} >> rsa[4:0] ;
assign sticky = rsa[4]&(| lo[14:0]) |
rsa[3]&(| lvl_1[ 6:0]) |
rsa[2]&(| lvl_2[ 2:0]) |
rsa[1]&(| lvl_3[ 0:0]) |
rsa[0]&( 1'b0) | stin;
assing gbit = (rsa[0]) ? lvl_4[0] :
(rsa[1]) ? lvl_3[1] :
(rsa[2]) ? lvl_2[3] :
(rsa[3]) ? lvl_1[7] :
(rsa[4]) ? lo[15] : 1'b0;
assign nxstin = gbit | sticky;
*/
// The following module has indentical functionality as above assignment.
// It should be used in circuit design.
// Only lvl_0[46:16] portion is two loads to inputs and the other two portions
// has one loading to previous stage.
// If inverting mux provides better timing and area than non_inverting one, the
// inverting type mux should be used, and a row of inverting output buffer
// should be provided.
// Total of 47+39+35+33+32 = 186 2:1 muxs.
// Total 186 x 8 = 1488 CU.
// Implementation tips: lev_1 through lev_5 indicates 5-level of two_to_one mux
// structure which can be implemented differently by using 4:1 or even 8:1 mux
// if over all area and timing can be improved. Circuit group have the
// flexibility to implemente it differently. Adequate buffering should be
// provided on rsa pins, especially on rsa[4] and rsa[3] pins.
wire [62:0] lvl_0; // level 0 wiring.
wire [46:0] lvl_1; // level_1 47-bit 2:1 mux output
wire [38:0] lvl_2; // level_2 39-bit 2:1 mux output
wire [34:0] lvl_3; // level_3 35-bit 2:1 mux output
wire [32:0] lvl_4; // level_4 33-bit 2:1 mux output
wire [31:0] lvl_5; // level_5 32-bit 2:1 mux output
wire [ 4:0] mux_sel; // internal buffering;
wire sticky_1, sticky_2, sticky_3, sticky_4, sticky_5;
wire sticky_even, sticky_odd;
assign mux_sel[4:0] = ~rsa[4:0] ; // inverting & buffering twice. or none
// wiring lvl_0.
assign lvl_0[62:0] = {hi[30:0],lo[31:0]};
assign lvl_1 = ~((~mux_sel[4]) ? (lvl_0[62:16]) : (lvl_0[46:0])) ;
assign lvl_2 = ~((~mux_sel[3]) ? (lvl_1[46: 8]) : (lvl_1[38:0])) ;
assign lvl_3 = ~((~mux_sel[2]) ? (lvl_2[38: 4]) : (lvl_2[34:0])) ;
assign lvl_4 = ~((~mux_sel[1]) ? (lvl_3[34: 2]) : (lvl_3[32:0])) ;
assign lvl_5 = ~((~mux_sel[0]) ? (lvl_4[32: 1]) : (lvl_4[31:0])) ;
assign rsf_out[31:0] = ~lvl_5;
/* sticky portion. Use even and odd path to speed up. */
assign sticky_1 = | lvl_0[15:0] ;
assign sticky_2 = ~(& lvl_1[ 7:0]) ; // lvl_1 is reversed
assign sticky_3 = | lvl_2[ 3:0] ;
assign sticky_4 = ~(& lvl_3[ 1:0]) ; // lvl_3 is reversed
assign sticky_5 = | lvl_4[ 0] ;
assign sticky_even = (~mux_sel[4])&sticky_1 | (~mux_sel[2])&sticky_3 |
(~mux_sel[0])&sticky_5 | stin ; // prev.stage.
assign sticky_odd = (~mux_sel[3])&sticky_2 | (~mux_sel[1])&sticky_4 ;
assign sticky = ~(!sticky_even & !sticky_odd) ; // nd2 <= nr2 + nr3
endmodule
// ------------------- 15) 32-bit bit_wise comparator --------------------------
// ------------------- Kogge-Stone style -----------------------------------
// ------------------- a less than b only ----------------------------------
module cmp32_ks_lt (ai, bi, a_ltn_b);
input [31:0] ai;
input [31:0] bi;
output a_ltn_b; // ai less_than bi.
/* Logic
assign a_ltn_b = ( ai[31:0] < bi[31:0] ) ;
*/
// a_ltn_b portion below
wire [31:0] bi_invert; // bit-wise invert output
wire [31:0] gi; // bit-wise generate carry output
wire [31:0] pi; // bit-wise propgate carry output
wire p30_27, g31_28; // 7th's group_pseudo_P* and G*
wire p26_23, g27_24; // 6th
wire p22_19, g23_20; // 5th
wire p18_15, g19_16; // 4th
wire g15_12, g11_8, g7_4, g3_0; // 3~0th
wire p14_11, p10_7, p6_3, p2_0; // 3~0th
wire p30_15, g31_16, g15_0; // second level P* and G*.
wire NC; // no connection wire.
assign bi_invert = ~ bi ;
assign gi[31:1] = ai[31:1] & bi_invert[31:1] ;
assign pi[31:1] = ai[31:1] | bi_invert[31:1] ;
assign gi[0] = ai[0] | bi_invert[0]; // insert c_in here.
assign pi[0] = 1'b1; // not used.
pg4bt_lt32 i_pg_31_28 ( .gs_3_0(g31_28),
.ps_2_n1(p30_27),
.g_in(gi[31:28]),
.p_in(pi[30:28]),
.pn_3(pi[27]));
pg4bt_lt32 i_pg_27_24 ( .gs_3_0(g27_24),
.ps_2_n1(p26_23),
.g_in(gi[27:24]),
.p_in(pi[26:24]),
.pn_3(pi[23]));
pg4bt_lt32 i_pg_23_20 ( .gs_3_0(g23_20),
.ps_2_n1(p22_19),
.g_in(gi[23:20]),
.p_in(pi[22:20]),
.pn_3(pi[19]));
pg4bt_lt32 i_pg_19_16 ( .gs_3_0(g19_16),
.ps_2_n1(p18_15),
.g_in(gi[19:16]),
.p_in(pi[18:16]),
.pn_3(pi[15]));
| This page: |
Created: | Wed Mar 24 09:43:37 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/custom_cells_behv.v
|