| Prev Page | Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
| A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z |
| V |
| Connects up to: | ifu:fold_logic:dec_valid |
| Connects up to: | ifu:fold_logic:dec_valid |
| Connects up to: | ifu:fold_logic:dec_valid |
| Connects up to: | ifu:fold_logic:dec_valid |
| Connects up to: | rcu_ctl:dest_dec:valid_op_r |
| Connects up to: | ifu:ex_len_dec:fetch_valid |
| Connects down to: | ibuf_ctl:ibuf_ctl:valid |
| Connects up to: | icu_nocache:icctl:valid , icu:icctl:valid |
| Connects down to: | icctl:icctl:valid , icu_dpath:icu_dpath:valid |
| Connects down to: | ibuffer:ibuffer:buf_ic_sel |
| Connects up to: | icu_nocache:icu_dpath:valid , icu:icu_dpath:valid |
| Connects down to: | icctl:icctl:valid , icu_dpath:icu_dpath:valid |
| Connects down to: | ibuf_monitor:ibuf_monitor:num_val_byte |
| Connects up to: | rcu_ctl:optop_dec:valid_op_r |
| Connects up to: | main_dec:rs1_dec:fetch_valid |
| Connects up to: | main_dec:rs2_dec_len1:fetch_valid , main_dec:rs2_dec_len2:fetch_valid , main_dec:rs2_dec_len3:fetch_valid |
| Connects down to: | ff_sr:vld_w_reg:din |
| Connects down to: | mj_s_ff_snr_d:valid_diag_c_reg:out |
| Connects down to: | mj_s_ff_snr_d:valid_diag_c_reg:in |
| Connects down to: | mj_s_ff_s_d:valid_diag_window_flop:in |
| Connects down to: | mj_s_ff_s_d:valid_diag_window_flop:out |
| Connects down to: | ff_sre:vld_c_reg:din |
| Connects down to: | mux8:valid_mux:out , mj_s_ff_snre_d:valid_flop:in |
| Connects down to: | ff_sre:flop_vld_op_rcu:din , ff_sre:flop_vld_op_ucode:din , ff_sre:flop_vld_op_gen:din |
| Connects up to: | monitor:instruction_monitor:valid_r , monitor:instruction_monitor:pipe_cntl , monitor:instruction_monitor:pipe , monitor:instruction_monitor:iu |
| Connects up to: | code_seq_dp:acode:valid_opcode |
| Connects down to: | code_seq_cntl:p_code_seq_cntl:valid_opcode , code_seq_dp:p_code_seq_dp:valid_opcode |
| Connects down to: | fpu_dec:fpud:valid_opcode |
| Connects up to: | code_seq:p_code_seq_cntl:valid_opcode |
| Connects down to: | acode_dec:acode:valid_opcode , mj_s_ff_snre_d:ff_valid:out |
| Connects up to: | code_seq:p_code_seq_dp:valid_opcode |
| Connects up to: | code_seq_cntl:fpud:valid_opcode |
| Connects down to: | mj_s_ff_snre_d:ff_valid_a:out |
| Connects down to: | ex_ctl:ex_ctl:valid_op_r |
| Connects up to: | iu:ex:valid_op_r_ex |
| Connects up to: | ex:ex_ctl:valid_op_r |
| Connects down to: | ifu:ifu:valid_op_r_fpu |
| Connects up to: | cpu:iu:fpop_valid |
| Connects down to: | ucode_monitor:ucode_monitor:ifu_op_valid_r , ucode_monitor:ucode_monitor:valid_op_r |
| Connects down to: | rcu_ctl:rcu_ctl:valid_op_r |
| Connects up to: | iu:rcu:valid_op_r_rcu |
| Connects down to: | dest_decoder:dest_dec:valid , optop_decoder:optop_dec:valid , ff_sre:flop_fc_e:din |
| Connects up to: | rcu:rcu_ctl:valid_op_r |
| Connects down to: | ucode_ctrl:ucode_ctrl_0:valid_op_r |
| Connects up to: | iu:ucode:valid_op_r_ucode |
| Connects down to: | ucode_dec:ucode_dec_0:valid_op_r |
| Connects up to: | ucode_ctrl:ucode_add_0:valid_op_r |
| Connects down to: | ucode_add:ucode_add_0:valid_op_r |
| Connects up to: | ucode:ucode_ctrl_0:valid_op_r |
| Connects up to: | ucode_add:ucode_dec_0:valid_op_r |
| Connects up to: | monitor:ucode_monitor:valid_op_r |
| Connects up to: | iu:ifu:valid_op_r_ex |
| Connects down to: | ex:ex:valid_op_r , ifu:ifu:valid_op_r_ex |
| Connects up to: | iu:ifu:valid_op_r |
| Connects down to: | ff_sre:flop_vld_op_gen:out |
| Connects up to: | iu:ifu:valid_op_r_pipe |
| Connects down to: | ifu:ifu:valid_op_r_pipe , pipe:pipe:inst_vld_r |
| Connects down to: | ff_sre:flop_vld_op_rcu:out |
| Connects up to: | iu:ifu:valid_op_r_rcu |
| Connects down to: | ifu:ifu:valid_op_r_rcu , rcu:rcu:valid_op_r |
| Connects down to: | ff_sre:flop_vld_op_ucode:out |
| Connects up to: | iu:ifu:valid_op_r_ucode |
| Connects down to: | ifu:ifu:valid_op_r_ucode , ucode:ucode:valid_op_r |
| Connects down to: | instruction_monitor:instruction_monitor:valid_op |
| Connects down to: | ff_sre:vld_e_reg:din , ff_sre:vld_e_v1_reg:din |
| Connects down to: | mux2:mux_valid_rs1:out , ff_sre:flop_valid_rs1:din |
| Connects down to: | rs1_dec:rs1_dec:valid_rs1 |
| Connects up to: | ifu:main_dec:valid_rs1_int1 |
| Connects up to: | main_dec:rs1_dec:valid_rs1 |
| Connects down to: | mux2:mux_valid_rs1:in0 , mux2:mux_valid_rs2:in1 |
| Connects down to: | main_dec:main_dec:valid_rs1 |
| Connects down to: | ff_sre:flop_valid_rs1:out |
| Connects up to: | iu:ifu:valid_rs1_r |
| Connects down to: | ifu:ifu:valid_rs1_r , rcu:rcu:valid_rs1_r |
| Connects down to: | rcu_ctl:rcu_ctl:valid_rs1_r |
| Connects up to: | iu:rcu:valid_rs1_r |
| Connects down to: | decode_opcode:decode_opcode_rs1:valid |
| Connects up to: | rcu:rcu_ctl:valid_rs1_r |
| Connects down to: | mux2:mux_valid_rs2:out , ff_sre:flop_vld_rs2:din |
| Connects down to: | mux2:mux_valid_rs1:in1 , mux2:mux_valid_rs2:in0 |
| Connects down to: | ff_sre:flop_vld_rs2:out |
| Connects up to: | iu:ifu:valid_rs2_r |
| Connects down to: | ifu:ifu:valid_rs2_r , rcu:rcu:valid_rs2_r |
| Connects down to: | rcu_ctl:rcu_ctl:valid_rs2_r |
| Connects up to: | iu:rcu:valid_rs2_r |
| Connects down to: | decode_opcode:decode_opcode_rs2:valid |
| Connects up to: | rcu:rcu_ctl:valid_rs2_r |
| Connects down to: | ff_sre:flop_vld_rsd:din |
| Connects down to: | ff_sre:flop_vld_rsd:out |
| Connects up to: | iu:ifu:valid_rsd_r |
| Connects down to: | ifu:ifu:valid_rsd_r , rcu:rcu:valid_rsd_r |
| Connects down to: | rcu_ctl:rcu_ctl:valid_rsd_r |
| Connects up to: | iu:rcu:valid_rsd_r |
| Connects up to: | rcu:rcu_ctl:valid_rsd_r |
| Connects up to: | monitor:ucode_monitor:lvars , monitor:ucode_monitor:iu |
| Connects down to: | mux2_30:vars_din_mux:out , ff_se_30:vars_reg:din |
| Connects down to: | ex_dpath:ex_dpath:vars_out , ex_regs:ex_regs:vars_out |
| Connects up to: | iu:ex:lvars |
| Connects down to: | mux2_32:wr_optop_mux:in1 |
| Connects up to: | ex:ex_dpath:vars_out |
| Connects down to: | ff_se_30:vars_reg:out , mux21_32:reg_rd_mux:in1 , mux7_32:ucode_reg_data_mux:in1 , ff_s_32:vars_w_reg:din |
| Connects up to: | ex:ex_regs:vars_out |
| Connects down to: | ff_s_32:vars_w_reg:out |
| Connects down to: | ff_se_30:vars_reg:enable |
| Connects down to: | mux21_32:reg_rd_mux:in18 , ff_s_32:versionid_w_reg:din |
| Connects down to: | ff_s_32:versionid_w_reg:out |
| Connects down to: | mux4:mux_vld_1_byte:out , mux8:mux_vld_1_inst:in1 , mux8:mux_vld_2_inst:in1 , mux8:mux_vld_3_inst:in1 |
| Connects down to: | mux4:mux_vld_1_byte:in1 |
| Connects down to: | mux4:mux_vld_1_byte:in2 |
| Connects down to: | mux4:mux_vld_1_byte:in3 |
| Connects down to: | mux4:mux_vld_2_byte:out , mux8:mux_vld_1_inst:in2 , mux8:mux_vld_2_inst:in2 , mux8:mux_vld_3_inst:in2 |
| Connects down to: | mux4:mux_vld_2_byte:in1 |
| Connects down to: | mux4:mux_vld_2_byte:in2 |
| Connects down to: | mux4:mux_vld_2_byte:in3 |
| Connects down to: | mux4:mux_vld_3_byte:out , mux8:mux_vld_1_inst:in3 , mux8:mux_vld_2_inst:in3 , mux8:mux_vld_3_inst:in3 |
| Connects down to: | mux4:mux_vld_3_byte:in1 |
| Connects down to: | mux4:mux_vld_3_byte:in2 |
| Connects down to: | mux4:mux_vld_3_byte:in3 |
| Connects down to: | mux4:mux_vld_4_byte:out , mux8:mux_vld_1_inst:in4 , mux8:mux_vld_2_inst:in4 , mux8:mux_vld_3_inst:in4 |
| Connects down to: | mux4:mux_vld_4_byte:in1 |
| Connects down to: | mux4:mux_vld_4_byte:in2 |
| Connects down to: | mux4:mux_vld_4_byte:in3 |
| Connects down to: | mux4:mux_vld_5_byte:out , mux8:mux_vld_1_inst:in5 , mux8:mux_vld_2_inst:in5 , mux8:mux_vld_3_inst:in5 |
| Connects down to: | mux4:mux_vld_5_byte:in1 |
| Connects down to: | mux4:mux_vld_5_byte:in2 |
| Connects down to: | mux4:mux_vld_5_byte:in3 |
| Connects down to: | mux4:mux_vld_6_byte:out , mux8:mux_vld_1_inst:in6 , mux8:mux_vld_2_inst:in6 , mux8:mux_vld_3_inst:in6 |
| Connects down to: | mux4:mux_vld_6_byte:in1 |
| Connects down to: | mux4:mux_vld_6_byte:in2 |
| Connects down to: | mux4:mux_vld_6_byte:in3 |
| A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z |
| Next Page | Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
| This page: | Created: | Wed Mar 24 09:43:03 1999 |
| Verilog converted to html by v2html 5.0 (written by Costas Calamvokis). | Help |