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| X |
| Connects down to: | mj_s_mux4_d_8:i_dout_4b_mux_31_24:in1 , mj_s_mux3_d_8:i_dout_4b_mux_23_16:in0 |
| Y |
| Connects down to: | mj_s_mux4_d_8:i_dout_4b_mux_31_24:in2 , mj_s_mux3_d_8:i_dout_4b_mux_23_16:in1 , mj_s_mux2_d_8:i_dout_4b_mux_15_8:in0 |
| Z |
| Connects down to: | mj_s_mux4_d_8:i_dout_4b_mux_31_24:in3 , mj_s_mux3_d_8:i_dout_4b_mux_23_16:in2 , mj_s_mux2_d_8:i_dout_4b_mux_15_8:in1 |
| Connects up to: | zero_det:zero_a_32_0:zero32_a |
| Connects up to: | zero_det:zero_b_32_0:zero32_b |
| Connects down to: | zero_a_32:zero_a_32_0:zero32 |
| Connects down to: | zero_b_32:zero_b_32_0:zero32 |
| Connects down to: | dc_dec:dc_dec:zeroline_busy , miss_cntl:miss_cntl:zeroline_busy |
| Connects up to: | dcctl:dc_dec:zeroline_busy |
| Connects up to: | dcctl:miss_cntl:zeroline_busy |
| Connects down to: | dc_dec:dc_dec:zeroline_c , dcudp_cntl:dcudp_cntl:zeroline_c , miss_cntl:miss_cntl:zeroline_c |
| Connects up to: | dcctl:dcudp_cntl:zeroline_c |
| Connects up to: | dcctl:dc_dec:zeroline_c |
| Connects up to: | dcctl:miss_cntl:zeroline_c |
| Connects down to: | dcudp_cntl:dcudp_cntl:zeroline_cyc , miss_cntl:miss_cntl:zeroline_cyc |
| Connects up to: | dcctl:dcudp_cntl:zeroline_cyc |
| Connects up to: | dcctl:miss_cntl:zeroline_cyc |
| Connects down to: | ff_s:zeroline_c_reg:out |
| Connects down to: | cmp32zero:cmp32zero:a_eql_z |
| Connects up to: | zero_det:zero_a_32_0:zero_31_2_a |
| Connects down to: | cmp32zero:cmp32zero:a_eql_z |
| Connects up to: | zero_det:zero_b_32_0:zero_31_2_b |
| Connects down to: | zero_a_32:zero_a_32_0:zero_31_2 |
| Connects down to: | zero_b_32:zero_b_32_0:zero_31_2 |
| Connects up to: | ex:ex_ctl:rs1_bypass_mux_out |
| Connects down to: | ff_sr:zero_flop:din |
| Connects down to: | ff_sr:zero_flop:out |
| Connects down to: | smu_ctl:smu_ctl:zero_entries_fl , smu_dpath:smu_dpath:zero_entries_fl |
| Connects up to: | smu:smu_ctl:zero_entries_fl |
| Connects down to: | comp_eq_32:comp:eq |
| Connects up to: | smu:smu_dpath:zero_entries_fl |
| Connects down to: | ff_sr_5:zero_state_reg:out , ff_s:zero_state_reg_0:out |
| Connects down to: | ff_sre:zero_c_reg:out |
| Connects down to: | ex_ctl:ex_ctl:zero_trap_e |
| Connects up to: | iu:ex:zero_trap_e |
| Connects up to: | ex:ex_ctl:zero_trap_e |
| Connects down to: | ex:ex:zero_trap_e , trap:trap:zero_trap_e |
| Connects down to: | ff_sre:zero_c_reg:din |
| Connects up to: | iu:trap:zero_trap_e |
| Connects down to: | inc_decode:incdec:zmd , mj_s_mux2_d_32:loadd_mux:sel |
| Connects up to: | incmod:incdec:zmd |
| Connects up to: | pri_encode:f_dpcl_lbd32:out |
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| This page: | Created: | Wed Mar 24 09:43:03 1999 |
| Verilog converted to html by v2html 5.0 (written by Costas Calamvokis). | Help |