.in2 (userrange1_out[15:0]),
			 .gt  (range1_l_cmp2_gt),
			 .eq  (range1_l_cmp2_eq),
			 .lt  (range1_l_cmp2_lt)
			 );
   ucmp_16 range1_h_cmp2(.in1 (smu_addr_d1[29:14]),
			 .in2 (userrange1_out[31:16]),
			 .gt  (range1_h_cmp2_gt),
			 .eq  (range1_h_cmp2_eq),
			 .lt  (range1_h_cmp2_lt)
			 );
   ucmp_16 range2_l_cmp2(.in1 (smu_addr_d1[29:14]),
			 .in2 (userrange2_out[15:0]),
			 .gt  (range2_l_cmp2_gt),
			 .eq  (range2_l_cmp2_eq),
			 .lt  (range2_l_cmp2_lt)
			 );
   ucmp_16 range2_h_cmp2(.in1 (smu_addr_d1[29:14]),
			 .in2 (userrange2_out[31:16]),
			 .gt  (range2_h_cmp2_gt),
			 .eq  (range2_h_cmp2_eq),
			 .lt  (range2_h_cmp2_lt)
			 );

   /****************************************************************************
    * breakpoint1 and breakpoint2
    ***************************************************************************/
   cmp_eq_19 data_brk1_31_13_cmp(.in1 ({2'b00,iu_addr_e[29:13]}),
				 .in2 (brk1a_out[31:13]),
				 .eq  (data_brk1_31_13_eq)
				 );
   cmp_eq_8 data_brk1_11_4_cmp(.in1 (iu_addr_e[11:4]),
			       .in2 (brk1a_out[11:4]),
			       .eq  (data_brk1_11_4_eq)
			       );
   assign data_brk1_misc_eq[4]   = ~(iu_addr_e[12]  ^ brk1a_out[12]);
   assign data_brk1_misc_eq[3:0] = ~(iu_addr_e[3:0] ^ brk1a_out[3:0]);
   cmp_eq_19 data_brk2_31_13_cmp(.in1 ({2'b00,iu_addr_e[29:13]}),
				 .in2 (brk2a_out[31:13]),
				 .eq  (data_brk2_31_13_eq)
				 );
   cmp_eq_8 data_brk2_11_4_cmp(.in1 (iu_addr_e[11:4]),
			       .in2 (brk2a_out[11:4]),
			       .eq  (data_brk2_11_4_eq)
			       );
   assign data_brk2_misc_eq[4]   = ~(iu_addr_e[12]  ^ brk2a_out[12]);
   assign data_brk2_misc_eq[3:0] = ~(iu_addr_e[3:0] ^ brk2a_out[3:0]);
   cmp_eq_19 inst_brk1_31_13_cmp(.in1 (pc_r[31:13]),
				 .in2 (brk1a_out[31:13]),
				 .eq  (inst_brk1_31_13_eq)
				 );
   cmp_eq_8 inst_brk1_11_4_cmp(.in1 (pc_r[11:4]),
			       .in2 (brk1a_out[11:4]),
			       .eq  (inst_brk1_11_4_eq)
			       );
   assign inst_brk1_misc_eq[4]   = ~(pc_r[12]  ^ brk1a_out[12]);
   assign inst_brk1_misc_eq[3:0] = ~(pc_r[3:0] ^ brk1a_out[3:0]);
   cmp_eq_19 inst_brk2_31_13_cmp(.in1 (pc_r[31:13]),
				 .in2 (brk2a_out[31:13]),
				 .eq  (inst_brk2_31_13_eq)
				 );
   cmp_eq_8 inst_brk2_11_4_cmp(.in1 (pc_r[11:4]),
			       .in2 (brk2a_out[11:4]),
			       .eq  (inst_brk2_11_4_eq)
			       );
   assign inst_brk2_misc_eq[4]   = ~(pc_r[12]  ^ brk2a_out[12]);
   assign inst_brk2_misc_eq[3:0] = ~(pc_r[3:0] ^ brk2a_out[3:0]);

   /****************************************************************************
    * oplim_trap
    ***************************************************************************/
   cmp_32 oplim_cmp(.in1  (optop_c[31:0]),
		    .in2  ({1'b0, oplim_out[30:0]}),
		    .sign (1'b0),
		    .gt   (oplim_gt),
		    .eq   (oplim_eq),
		    .lt   (oplim_lt)
		    );
   ff_se priv_update_optop_reg(.out    (priv_update_optop_e),
			       .din    (priv_update_optop),
			       .enable (~hold_e),
			       .clk    (clk)
			       );
   assign oplim_trap_c = oplim_lt & inst_valid[1] & oplim_out[31] &
			 ~priv_update_optop_e;

   /****************************
    * runtime_NullPtrException *
    ****************************/

   /************************************************************************
    *									   *
    * Lock related exceptions:						   *
    *	LockCountOverflowTrap, LockEnterMissTrap, LockExitMissTrap, and	   *
    *	LockReleaseTrap.						   *
    *									   *
    * Notice: We don't handle the case where objref in data_in equals both *
    *	      lockaddr0 and lockaddr1.					   *
    *									   *
    ************************************************************************/
   
   /******************** monitor caching change  *****************/
      
   compare_zero_32 la0_null_cmp(.in({4'h0, lockaddr0_out[29:2]}),
			.out(la0_null_e));
   compare_zero_32 la1_null_cmp(.in({4'h0, lockaddr1_out[29:2]}),
			.out(la1_null_e));
   
   // data_in in E stage to become objref_c in C stage
   
   ff_se_30 objref_c_reg(.out	(objref_c[29:0]),
   			 .din	(data_in[31:2]),
   			 .enable(~hold_c),
   			 .clk	(clk)
   			 );
   			 
   // muxes to select the din of la0 and la1 registers
   
   assign la0_objref_sel = lock0_cache & ~reg_wr_mux_sel[10];
   
   mux2_30 la0_reg_din_mux(.out	(la0_reg_din[29:0]),
   			   .in1	(objref_c[29:0]),
   			   .in0 (data_in[31:2]),
   			   .sel ({la0_objref_sel, reg_wr_mux_sel[10]})
   			   );
   			 
   assign la1_objref_sel = lock1_cache & ~reg_wr_mux_sel[11];
   
   mux2_30 la1_reg_din_mux(.out	(la1_reg_din[29:0]),
   			   .in1	(objref_c[29:0]),
   			   .in0 (data_in[31:2]),
   			   .sel ({la1_objref_sel, reg_wr_mux_sel[11]})
   			   );
   			 	
   
   comp_eq_32 la0_cmp(.in1 ({4'h0, lockaddr0_out[29:2]}),
		      .in2 ({4'h0, data_in[29:2]}),
		      .eq  (la0_hit)
		      );
   comp_eq_32 la1_cmp(.in1 ({4'h0, lockaddr1_out[29:2]}),
		      .in2 ({4'h0, data_in[29:2]}),
		      .eq  (la1_hit)
		      );
   cmp_eq_8 lc0_cmp(.in1 (lockcount0_out[7:0]),
		    .in2 (8'h00),
		    .eq  (lc0_eq_0)
		    );
   cmp_eq_8 lc1_cmp(.in1 (lockcount1_out[7:0]),
		    .in2 (8'h00),
		    .eq  (lc1_eq_0)
		    );
   // The carry output of these 8-bit adders are not needed
   cla_adder_8 lc0_p1_adder(.in1  (lockcount0_out[7:0]),
			    .in2  (8'h1),
			    .cin  (1'b0),
			    .sum  (lc0_p1[7:0]),
			    .cout (lc0_eq_255)
			    );
   cla_adder_8 lc0_m1_adder(.in1  (lockcount0_out[7:0]),
			    .in2  (8'hff),
			    .cin  (1'b0),
			    .sum  (lc0_m1[7:0]),
			    .cout (lc0_m1_adder_cout)
			    );
   cla_adder_8 lc1_p1_adder(.in1  (lockcount1_out[7:0]),
			    .in2  (8'h1),
			    .cin  (1'b0),
			    .sum  (lc1_p1[7:0]),
			    .cout (lc1_eq_255)
			    );
   cla_adder_8 lc1_m1_adder(.in1  (lockcount1_out[7:0]),
			    .in2  (8'hff),
			    .cin  (1'b0),
			    .sum  (lc1_m1[7:0]),
			    .cout (lc1_m1_adder_cout)
			    );
   cmp_eq_8 lc0_m1_cmp(.in1 (lc0_m1[7:0]),
		       .in2 (8'h0),
		       .eq  (lc0_m1_eq_0)
		       );
   cmp_eq_8 lc1_m1_cmp(.in1 (lc1_m1[7:0]),
		       .in2 (8'h0),
		       .eq  (lc1_m1_eq_0)
		       );
   /******************** monitor caching change  *****************/
   
   mux4_8 lc0_din_mux(.out (lc0_count_din[7:0]),
   		      .in3 (8'h1),
		      .in2 (lc0_p1[7:0]),
		      .in1 (lc0_m1[7:0]),
		      .in0 (data_in[7:0]),
		      .sel (lc0_din_mux_sel[3:0])
		      );
   // set and reset lc0 CO bit
   
   mux2 lc0_cacheon_din_mux(.out (lc0_cacheon_din),
   			    .in1 (1'b1),
   			    .in0 (data_in[15]),
   			    .sel ({lock0_cache, ~lock0_cache})
   			    );

   mux4_8 lc1_din_mux(.out (lc1_count_din[7:0]),
		      .in3 (8'h1),	
		      .in2 (lc1_p1[7:0]),
		      .in1 (lc1_m1[7:0]),
		      .in0 (data_in[7:0]),
		      .sel (lc1_din_mux_sel[3:0])
		      );

   // set and reset lc1 CO bit
   
   mux2 lc1_cacheon_din_mux(.out (lc1_cacheon_din),
   			    .in1 (1'b1),
   			    .in0 (data_in[15]),
   			    .sel ({lock1_cache, ~lock1_cache})
   			    );
endmodule // ex_regs

/*******************************************************************************
 *
 * Module:	mux21_32
 * 
 * This module implements the 21:1 32-bit mux
 * 
 ******************************************************************************/

module mux21_32(out,
		in20,
		in19,
		in18,
		in17,
		in16,
		in15,
		in14,
		in13,
		in12,
		in11,
		in10,
		in9,
		in8,
		in7,
		in6,
		in5,
		in4,
		in3,
		in2,
		in1,
		in0,
		sel);

   input [31:0]	in20;		// Input data bus
   input [31:0] in19;		// Input data bus
   input [31:0] in18;		// Input data bus
   input [31:0] in17;		// Input data bus
   input [31:0] in16;		// Input data bus
   input [31:0] in15;		// Input data bus
   input [31:0] in14;		// Input data bus
   input [31:0] in13;		// Input data bus
   input [31:0]	in12;		// Input data bus
   input [31:0]	in11;		// Input data bus
   input [31:0]	in10;		// Input data bus
   input [31:0]	in9;		// Input data bus
   input [31:0]	in8;		// Input data bus
   input [31:0]	in7;		// Input data bus
   input [31:0]	in6;		// Input data bus
   input [31:0]	in5;		// Input data bus
   input [31:0]	in4;		// Input data bus
   input [31:0]	in3;		// Input data bus
   input [31:0]	in2;		// Input data bus
   input [31:0]	in1;		// Input data bus
   input [31:0] in0;		// Input data bus
   input [20:0] sel;		// Input select signal
   output [31:0] out;		// Output data bus

   wire [31:0] 	mux1_out;	// Output data of the 1st 4:1 mux
   wire [31:0] 	mux2_out;	// Output data of the 2nd 4:1 mux
   wire [31:0] 	mux3_out;	// Output data of the 3rd 4:1 mux
   wire [31:0] 	mux4_out;	// Output data of the 4th 4:1 mux
   wire [31:0] 	mux5_out;	// Output data of the 5th 5:1 mux
   wire 	mux1_sel;	// Select signal for mux1 output
   wire 	mux2_sel;	// Select signal for mux2 output
   wire 	mux3_sel;	// Select signal for mux3 output
   wire 	mux4_sel;	// Select signal for mux4 output
   wire 	mux5_sel;	// Select signal for mux5 output

   /*
    * It's the responsibility of the control logic to ensure that no more than
    * one register select signal is active at a time to protect the muxes.
    * Structure of the mux is: 4:1 4:1 4:1 4:1 5:1
    *				       5:1
    */
   // First stage muxes
   mux4_32 kmux1(.out(mux1_out[31:0]),
		 .in3(in3[31:0]),
		 .in2(in2[31:0]),
		 .in1(in1[31:0]),
		 .in0(in0[31:0]),
		 .sel(sel[3:0]));
   mux4_32 kmux2(.out(mux2_out[31:0]),
		 .in3(in7[31:0]),
		 .in2(in6[31:0]),
		 .in1(in5[31:0]),
		 .in0(in4[31:0]),
		 .sel(sel[7:4]));
   mux4_32 kmux3(.out(mux3_out[31:0]),
		 .in3(in11[31:0]),
		 .in2(in10[31:0]),
		 .in1(in9[31:0]),
		 .in0(in8[31:0]),
		 .sel(sel[11:8]));
   mux4_32 kmux4(.out(mux4_out[31:0]),
		 .in3(in15[31:0]),
		 .in2(in14[31:0]),
		 .in1(in13[31:0]),
		 .in0(in12[31:0]),
		 .sel(sel[15:12]));
   mux5_32 kmux5(.out(mux5_out[31:0]),
		 .in4(in20[31:0]),
		 .in3(in19[31:0]),
		 .in2(in18[31:0]),
		 .in1(in17[31:0]),
		 .in0(in16[31:0]),
		 .sel(sel[20:16]));
   assign mux1_sel = |sel[3:0];
   assign mux2_sel = |sel[7:4];
   assign mux3_sel = |sel[11:8];
   assign mux4_sel = |sel[15:12];
   assign mux5_sel = |sel[20:16];

   // Second stage 5:1 mux
   mux5_32 kmux(.out(out[31:0]),
		.in4(mux5_out[31:0]),
		.in3(mux4_out[31:0]),
		.in2(mux3_out[31:0]),
		.in1(mux2_out[31:0]),
		.in0(mux1_out[31:0]),
		.sel({mux5_sel, mux4_sel, mux3_sel, mux2_sel, mux1_sel}));

endmodule // mux21_32