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    mj_s_ff_snr_d    mj_s_ff_snr_d_13(.out(out[13]), .in(din[13]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_14(.out(out[14]), .in(din[14]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_15(.out(out[15]), .in(din[15]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_16(.out(out[16]), .in(din[16]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_17(.out(out[17]), .in(din[17]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_18(.out(out[18]), .in(din[18]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_19(.out(out[19]), .in(din[19]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_20(.out(out[20]), .in(din[20]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_21(.out(out[21]), .in(din[21]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_22(.out(out[22]), .in(din[22]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_23(.out(out[23]), .in(din[23]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_24(.out(out[24]), .in(din[24]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_25(.out(out[25]), .in(din[25]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_26(.out(out[26]), .in(din[26]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_27(.out(out[27]), .in(din[27]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_28(.out(out[28]), .in(din[28]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_29(.out(out[29]), .in(din[29]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_30(.out(out[30]), .in(din[30]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_31(.out(out[31]), .in(din[31]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_32(.out(out[32]), .in(din[32]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_33(.out(out[33]), .in(din[33]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_34(.out(out[34]), .in(din[34]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_35(.out(out[35]), .in(din[35]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_36(.out(out[36]), .in(din[36]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_37(.out(out[37]), .in(din[37]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_38(.out(out[38]), .in(din[38]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_39(.out(out[39]), .in(din[39]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_40(.out(out[40]), .in(din[40]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_41(.out(out[41]), .in(din[41]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_42(.out(out[42]), .in(din[42]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_43(.out(out[43]), .in(din[43]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_44(.out(out[44]), .in(din[44]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_45(.out(out[45]), .in(din[45]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_46(.out(out[46]), .in(din[46]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_47(.out(out[47]), .in(din[47]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_48(.out(out[48]), .in(din[48]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_49(.out(out[49]), .in(din[49]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_50(.out(out[50]), .in(din[50]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_51(.out(out[51]), .in(din[51]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_52(.out(out[52]), .in(din[52]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_53(.out(out[53]), .in(din[53]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_54(.out(out[54]), .in(din[54]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_55(.out(out[55]), .in(din[55]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_56(.out(out[56]), .in(din[56]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_57(.out(out[57]), .in(din[57]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_58(.out(out[58]), .in(din[58]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_59(.out(out[59]), .in(din[59]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_60(.out(out[60]), .in(din[60]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_61(.out(out[61]), .in(din[61]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_62(.out(out[62]), .in(din[62]), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snr_d    mj_s_ff_snr_d_63(.out(out[63]), .in(din[63]), .reset_l(reset_l),.clk(clk));

endmodule 


[Up: dcram_misc ff4][Up: code_seq_dp rom0_ff][Up: code_seq_dp rom1_ff]
module mj_s_ff_s_d_64 (out, in, clk);
output  [63:0]  out;
input           clk;
input   [63:0]  in;

wire    [63:0]  out;

mj_s_ff_s_d    mj_s_ff_s_d_0(.out(out[0]),.in(in[0]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_1(.out(out[1]),.in(in[1]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_2(.out(out[2]),.in(in[2]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_3(.out(out[3]),.in(in[3]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_4(.out(out[4]),.in(in[4]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_5(.out(out[5]),.in(in[5]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_6(.out(out[6]),.in(in[6]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_7(.out(out[7]),.in(in[7]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_8(.out(out[8]),.in(in[8]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_9(.out(out[9]),.in(in[9]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_10(.out(out[10]),.in(in[10]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_11(.out(out[11]),.in(in[11]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_12(.out(out[12]),.in(in[12]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_13(.out(out[13]),.in(in[13]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_14(.out(out[14]),.in(in[14]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_15(.out(out[15]),.in(in[15]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_16(.out(out[16]),.in(in[16]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_17(.out(out[17]),.in(in[17]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_18(.out(out[18]),.in(in[18]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_19(.out(out[19]),.in(in[19]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_20(.out(out[20]),.in(in[20]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_21(.out(out[21]),.in(in[21]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_22(.out(out[22]),.in(in[22]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_23(.out(out[23]),.in(in[23]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_24(.out(out[24]),.in(in[24]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_25(.out(out[25]),.in(in[25]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_26(.out(out[26]),.in(in[26]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_27(.out(out[27]),.in(in[27]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_28(.out(out[28]),.in(in[28]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_29(.out(out[29]),.in(in[29]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_30(.out(out[30]),.in(in[30]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_31(.out(out[31]),.in(in[31]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_32(.out(out[32]),.in(in[32]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_33(.out(out[33]),.in(in[33]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_34(.out(out[34]),.in(in[34]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_35(.out(out[35]),.in(in[35]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_36(.out(out[36]),.in(in[36]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_37(.out(out[37]),.in(in[37]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_38(.out(out[38]),.in(in[38]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_39(.out(out[39]),.in(in[39]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_40(.out(out[40]),.in(in[40]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_41(.out(out[41]),.in(in[41]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_42(.out(out[42]),.in(in[42]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_43(.out(out[43]),.in(in[43]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_44(.out(out[44]),.in(in[44]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_45(.out(out[45]),.in(in[45]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_46(.out(out[46]),.in(in[46]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_47(.out(out[47]),.in(in[47]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_48(.out(out[48]),.in(in[48]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_49(.out(out[49]),.in(in[49]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_50(.out(out[50]),.in(in[50]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_51(.out(out[51]),.in(in[51]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_52(.out(out[52]),.in(in[52]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_53(.out(out[53]),.in(in[53]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_54(.out(out[54]),.in(in[54]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_55(.out(out[55]),.in(in[55]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_56(.out(out[56]),.in(in[56]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_57(.out(out[57]),.in(in[57]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_58(.out(out[58]),.in(in[58]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_59(.out(out[59]),.in(in[59]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_60(.out(out[60]),.in(in[60]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_61(.out(out[61]),.in(in[61]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_62(.out(out[62]),.in(in[62]),.clk(clk));
mj_s_ff_s_d    mj_s_ff_s_d_63(.out(out[63]),.in(in[63]),.clk(clk));
endmodule




[Up: ff_s_2 ff_s_0][Up: ff_s_2 ff_s_1][Up: ff_s_3 ff_s_0][Up: ff_s_3 ff_s_1][Up: ff_s_3 ff_s_2][Up: ff_s_4 ff_s_0][Up: ff_s_4 ff_s_1][Up: ff_s_4 ff_s_2][Up: ff_s_4 ff_s_3][Up: ff_s_5 ff_s_0][Up: ff_s_5 ff_s_1][Up: ff_s_5 ff_s_2][Up: ff_s_5 ff_s_3][Up: ff_s_5 ff_s_4][Up: ff_s_6 ff_s_0][Up: ff_s_6 ff_s_1][Up: ff_s_6 ff_s_2][Up: ff_s_6 ff_s_3][Up: ff_s_6 ff_s_4][Up: ff_s_6 ff_s_5][Up: ff_s_7 ff_s_0][Up: ff_s_7 ff_s_1][Up: ff_s_7 ff_s_2][Up: ff_s_7 ff_s_3][Up: ff_s_7 ff_s_4][Up: ff_s_7 ff_s_5][Up: ff_s_7 ff_s_6][Up: ff_s_8 ff_s_0][Up: ff_s_8 ff_s_1][Up: ff_s_8 ff_s_2][Up: ff_s_8 ff_s_3][Up: ff_s_8 ff_s_4]... (truncated)
module ff_s (out, din, clk) ;
    output    out;
    input     din;
    input     clk;
 
mj_s_ff_s_d  mj_s_ff_s_d_0 (	.out(out),
				.in(din),
				.clk(clk)
				);
endmodule


[Up: ifu flop_gr_1][Up: ifu flop_gr_2][Up: ifu flop_gr_3][Up: ifu flop_gr_4][Up: ifu flop_gr_5][Up: ifu flop_gr_6][Up: ifu flop_gr_7][Up: ifu flop_gr_8][Up: ifu flop_gr_9][Up: ifu flop_fold][Up: ifu flop_no_fold][Up: ifu flop_valid_rs1][Up: ifu flop_help_rs1][Up: ifu flop_lv_rs1][Up: ifu flop_lv_acc_rs1][Up: ifu flop_rev_ops][Up: ifu flop_st_op][Up: ifu flop_optop][Up: ifu flop_vld_rs2][Up: ifu flop_lv_rs2][Up: ifu flop_lvars_acc_rs2][Up: ifu flop_vld_op_rcu][Up: ifu flop_vld_op_ucode][Up: ifu flop_vld_op_gen][Up: ifu flop_vld_rsd][Up: ifu flop_drty_inst][Up: ifu flop_putfield][Up: ex_ctl wr_optop_e_flop][Up: ex_ctl ifeq_e_flop][Up: ex_ctl if_icmpeq_e_flop][Up: ex_ctl if_acmpeq_e_flop][Up: ex_ctl ifge_e_flop]... (truncated)
module ff_sre(out, din, enable, reset_l, clk) ;
    output   out;
    input    din;
    input    clk;
    input    reset_l;
    input    enable;
 
mj_s_ff_snre_d  mj_s_ff_snre_d_0 (      .out(out),
                                        .in(din), 
                                        .lenable(enable),
                                        .reset_l(reset_l),
                                        .clk(clk)
                                        );
endmodule


[Up: ucode_seq done_reg][Up: ff_se_10 ff_se_0][Up: ff_se_10 ff_se_1][Up: ff_se_10 ff_se_2][Up: ff_se_10 ff_se_3][Up: ff_se_10 ff_se_4][Up: ff_se_10 ff_se_5][Up: ff_se_10 ff_se_6][Up: ff_se_10 ff_se_7][Up: ff_se_10 ff_se_8][Up: ff_se_10 ff_se_9][Up: ff_se_11 ff_se_0][Up: ff_se_11 ff_se_1][Up: ff_se_11 ff_se_2][Up: ff_se_11 ff_se_3][Up: ff_se_11 ff_se_4][Up: ff_se_11 ff_se_5][Up: ff_se_11 ff_se_6][Up: ff_se_11 ff_se_7][Up: ff_se_11 ff_se_8][Up: ff_se_11 ff_se_9][Up: ff_se_11 ff_se_10][Up: ff_se_12 ff_se_0][Up: ff_se_12 ff_se_1][Up: ff_se_12 ff_se_2][Up: ff_se_12 ff_se_3][Up: ff_se_12 ff_se_4][Up: ff_se_12 ff_se_5][Up: ff_se_12 ff_se_6][Up: ff_se_12 ff_se_7][Up: ff_se_12 ff_se_8][Up: ff_se_12 ff_se_9]... (truncated)
module ff_se (out, din, enable, clk) ;
    output    out;
    input     din;
    input     clk;
    input     enable;
 
mj_s_ff_se_d  mj_s_ff_se_d_0 (  .out(out),
                                .in(din),
                                .lenable(enable),
                                .clk(clk)
                                );

endmodule


[Up: ex_ctl ret_optop_update_flop][Up: ex_ctl smu_access_reg][Up: ex_ctl load_buffer_fsm_reg][Up: pipe_cntl vld_w_reg][Up: pipe_cntl hold_e_reg][Up: pipe_cntl kill_dv_reg][Up: pipe_cntl iu_perf_reg][Up: pipe_cntl sc_sticky_reg][Up: pipe_cntl fold_trapped_reg][Up: dcudp_cntl diag_set_sel_reg][Up: dcudp_cntl dcu_addr_c_31_reg][Up: dcudp_cntl flush_set_sel_reg][Up: trap async_err_reg][Up: trap br_c_reg][Up: trap trap_stat_reg][Up: ff_sr_2 ff_sr_0][Up: ff_sr_2 ff_sr_1][Up: ff_sr_3 ff_sr_0][Up: ff_sr_3 ff_sr_1][Up: ff_sr_3 ff_sr_2][Up: ff_sr_4 ff_sr_0][Up: ff_sr_4 ff_sr_1][Up: ff_sr_4 ff_sr_2][Up: ff_sr_4 ff_sr_3][Up: ff_sr_5 ff_sr_0][Up: ff_sr_5 ff_sr_1][Up: ff_sr_5 ff_sr_2][Up: ff_sr_5 ff_sr_3][Up: ff_sr_5 ff_sr_4][Up: ff_sr_6 ff_sr_0][Up: ff_sr_6 ff_sr_1][Up: ff_sr_6 ff_sr_2]... (truncated)
module ff_sr(out, din, reset_l, clk) ;
    output   out;
    input    din;
    input    clk;
    input    reset_l;
 
mj_s_ff_snr_d  mj_s_ff_snr_d_0 (        .out(out),
                                        .in(din),
                                        .reset_l(reset_l),
                                        .clk(clk)
                                        );
endmodule



[Up: b_recoder ff_s_2_a]
module ff_s_2 (out, din, clk) ;
    output  [1:0]  out;
    input   [1:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);

endmodule 


[Up: sign_bit ff_s_3_0][Up: dc_dec flush_c_reg]
module ff_s_3 (out, din, clk) ;
    output  [2:0]  out;
    input   [2:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);

endmodule 


[Up: zero_det ff_s_4_0][Up: dc_dec smu_inst_c_reg][Up: dc_dec diag_c_reg][Up: rcu_ctl flop_global_reg_w]
module ff_s_4 (out, din, clk) ;
    output  [3:0]  out;
    input   [3:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);

endmodule 


[Up: pcsu sync1_reg_4_0][Up: pcsu sync0_reg_4_0]
module ff_s_5 (out, din, clk) ;
    output  [4:0]  out;
    input   [4:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);

endmodule 


module ff_s_6 (out, din, clk) ;
    output  [5:0]  out;
    input   [5:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);

endmodule 


module ff_s_7 (out, din, clk) ;
    output  [6:0]  out;
    input   [6:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);

endmodule 


[Up: dc_dec iu_inst_c_reg]
module ff_s_8 (out, din, clk) ;
    output  [7:0]  out;
    input   [7:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);

endmodule 


module ff_s_9 (out, din, clk) ;
    output  [8:0]  out;
    input   [8:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);

endmodule 


module ff_s_10 (out, din, clk) ;
    output  [9:0]  out;
    input   [9:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);

endmodule 


module ff_s_11 (out, din, clk) ;
    output  [10:0]  out;
    input   [10:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);

endmodule 


module ff_s_12 (out, din, clk) ;
    output  [11:0]  out;
    input   [11:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);

endmodule 


module ff_s_13 (out, din, clk) ;
    output  [12:0]  out;
    input   [12:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);

endmodule 


module ff_s_14 (out, din, clk) ;
    output  [13:0]  out;
    input   [13:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);

endmodule 


module ff_s_15 (out, din, clk) ;
    output  [14:0]  out;
    input   [14:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);

endmodule 


[Up: ucode_reg ff_s_16_1]
module ff_s_16 (out, din, clk) ;
    output  [15:0]  out;
    input   [15:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);

endmodule 


module ff_s_17 (out, din, clk) ;
    output  [16:0]  out;
    input   [16:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);

endmodule 


module ff_s_18 (out, din, clk) ;
    output  [17:0]  out;
    input   [17:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);

endmodule 


module ff_s_19 (out, din, clk) ;
    output  [18:0]  out;
    input   [18:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);

endmodule 


module ff_s_20 (out, din, clk) ;
    output  [19:0]  out;
    input   [19:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);

endmodule 


module ff_s_21 (out, din, clk) ;
    output  [20:0]  out;
    input   [20:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);

endmodule 


module ff_s_22 (out, din, clk) ;
    output  [21:0]  out;
    input   [21:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);

endmodule 


module ff_s_23 (out, din, clk) ;
    output  [22:0]  out;
    input   [22:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);

endmodule 


module ff_s_24 (out, din, clk) ;
    output  [23:0]  out;
    input   [23:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);

endmodule 


module ff_s_25 (out, din, clk) ;
    output  [24:0]  out;
    input   [24:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);

endmodule 


module ff_s_26 (out, din, clk) ;
    output  [25:0]  out;
    input   [25:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);

endmodule 


module ff_s_27 (out, din, clk) ;
    output  [26:0]  out;
    input   [26:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);

endmodule 


module ff_s_28 (out, din, clk) ;
    output  [27:0]  out;
    input   [27:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);
    ff_s    ff_s_27(out[27], din[27], clk);

endmodule 


module ff_s_29 (out, din, clk) ;
    output  [28:0]  out;
    input   [28:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);
    ff_s    ff_s_27(out[27], din[27], clk);
    ff_s    ff_s_28(out[28], din[28], clk);

endmodule 


module ff_s_30 (out, din, clk) ;
    output  [29:0]  out;
    input   [29:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);
    ff_s    ff_s_27(out[27], din[27], clk);
    ff_s    ff_s_28(out[28], din[28], clk);
    ff_s    ff_s_29(out[29], din[29], clk);

endmodule 


module ff_s_31 (out, din, clk) ;
    output  [30:0]  out;
    input   [30:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);
    ff_s    ff_s_27(out[27], din[27], clk);
    ff_s    ff_s_28(out[28], din[28], clk);
    ff_s    ff_s_29(out[29], din[29], clk);
    ff_s    ff_s_30(out[30], din[30], clk);

endmodule 


[Up: smu_dpath data_flop][Up: smu_dpath sbase_e_flop][Up: ucode_reg ff_s_32_1][Up: ucode_reg ff_s_32_2][Up: mx4_clr_reg_32 ff_s_32_a][Up: mx4_clr_reg_nxt_32 ff_s_32_a][Up: ex_regs pc_w_reg][Up: ex_regs vars_w_reg][Up: ex_regs frame_w_reg][Up: ex_regs optop_w_reg][Up: ex_regs oplim_w_reg][Up: ex_regs const_pool_w_reg][Up: ex_regs psr_w_reg][Up: ex_regs trapbase_w_reg][Up: ex_regs lockcount0_w_reg][Up: ex_regs lockcount1_w_reg][Up: ex_regs lockaddr0_w_reg][Up: ex_regs lockaddr1_w_reg][Up: ex_regs userrange1_w_reg][Up: ex_regs gc_config_w_reg][Up: ex_regs brk1a_w_reg][Up: ex_regs brk2a_w_reg][Up: ex_regs brk12c_w_reg][Up: ex_regs userrange2_w_reg][Up: ex_regs versionid_w_reg][Up: ex_regs hcr_w_reg][Up: ex_regs sc_bottom_w_reg][Up: rcu_dpath flop_rs1_data][Up: rcu_dpath flop_rs2_data][Up: pipe_dpath cosimpcreg][Up: ex_dpath rs1_bypass_reg][Up: ex_dpath rs2_bypass_reg]... (truncated)
module ff_s_32 (out, din, clk) ;
    output  [31:0]  out;
    input   [31:0]  din;
    input           clk;

    ff_s    ff_s_0(out[0], din[0], clk);
    ff_s    ff_s_1(out[1], din[1], clk);
    ff_s    ff_s_2(out[2], din[2], clk);
    ff_s    ff_s_3(out[3], din[3], clk);
    ff_s    ff_s_4(out[4], din[4], clk);
    ff_s    ff_s_5(out[5], din[5], clk);
    ff_s    ff_s_6(out[6], din[6], clk);
    ff_s    ff_s_7(out[7], din[7], clk);
    ff_s    ff_s_8(out[8], din[8], clk);
    ff_s    ff_s_9(out[9], din[9], clk);
    ff_s    ff_s_10(out[10], din[10], clk);
    ff_s    ff_s_11(out[11], din[11], clk);
    ff_s    ff_s_12(out[12], din[12], clk);
    ff_s    ff_s_13(out[13], din[13], clk);
    ff_s    ff_s_14(out[14], din[14], clk);
    ff_s    ff_s_15(out[15], din[15], clk);
    ff_s    ff_s_16(out[16], din[16], clk);
    ff_s    ff_s_17(out[17], din[17], clk);
    ff_s    ff_s_18(out[18], din[18], clk);
    ff_s    ff_s_19(out[19], din[19], clk);
    ff_s    ff_s_20(out[20], din[20], clk);
    ff_s    ff_s_21(out[21], din[21], clk);
    ff_s    ff_s_22(out[22], din[22], clk);
    ff_s    ff_s_23(out[23], din[23], clk);
    ff_s    ff_s_24(out[24], din[24], clk);
    ff_s    ff_s_25(out[25], din[25], clk);
    ff_s    ff_s_26(out[26], din[26], clk);
    ff_s    ff_s_27(out[27], din[27], clk);
    ff_s    ff_s_28(out[28], din[28], clk);
    ff_s    ff_s_29(out[29], din[29], clk);
    ff_s    ff_s_30(out[30], din[30], clk);
    ff_s    ff_s_31(out[31], din[31], clk);

endmodule 


[Up: ex_regs brk12c_srcbk2_reg][Up: ex_regs brk12c_srcbk1_reg][Up: ex_dpath for_w_flop]
module ff_se_2 (out, din, enable, clk) ;
    output  [1:0]  out;
    input   [1:0]  din;
    input           clk;
    input           enable;
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This page: Created:Wed Mar 24 09:45:31 1999
From: /import/jet-pj2-sim/rahim/picoJava-II/design/rtl/mj_ffs_behv.v

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