assign iadd = decodeout_1[96];
assign ladd = decodeout_1[97];
assign fadd = decodeout_1[98];
assign dadd = decodeout_1[99];
assign isub = decodeout_1[100];
assign lsub = decodeout_1[101];
assign fsub = decodeout_1[102];
assign dsub = decodeout_1[103];
assign imul = decodeout_1[104];
assign lmul = decodeout_1[105];
assign fmul = decodeout_1[106];
assign dmul = decodeout_1[107];
assign idiv = decodeout_1[108];
assign ldiv = decodeout_1[109];
assign fdiv = decodeout_1[110];
assign ddiv = decodeout_1[111];
assign irem = decodeout_1[112];
assign lrem = decodeout_1[113];
assign frem = decodeout_1[114];
assign drem = decodeout_1[115];
assign ineg = decodeout_1[116];
assign lneg = decodeout_1[117];
assign fneg = decodeout_1[118];
assign dneg = decodeout_1[119];
assign ishl = decodeout_1[120];
assign lshl = decodeout_1[121];
assign ishr = decodeout_1[122];
assign lshr = decodeout_1[123];
assign iushr = decodeout_1[124];
assign lushr = decodeout_1[125];
assign iand = decodeout_1[126];
assign land = decodeout_1[127];
assign ior = decodeout_1[128];
assign lor = decodeout_1[129];
assign ixor = decodeout_1[130];
assign lxor = decodeout_1[131];
assign iinc = decodeout_1[132];
assign i2l = decodeout_1[133];
assign i2f = decodeout_1[134];
assign i2d = decodeout_1[135];
assign l2i = decodeout_1[136];
assign l2f = decodeout_1[137];
assign l2d = decodeout_1[138];
assign f2i = decodeout_1[139];
assign f2l = decodeout_1[140];
assign f2d = decodeout_1[141];
assign d2i = decodeout_1[142];
assign d2l = decodeout_1[143];
assign d2f = decodeout_1[144];
assign int2byte = decodeout_1[145];
assign int2char = decodeout_1[146];
assign int2short = decodeout_1[147];
assign lcmp = decodeout_1[148];
assign fcmpl = decodeout_1[149];
assign fcmpg = decodeout_1[150];
assign dcmpl = decodeout_1[151];
assign dcmpg = decodeout_1[152];
assign ifeq = decodeout_1[153];
assign ifne = decodeout_1[154];
assign iflt = decodeout_1[155];
assign ifge = decodeout_1[156];
assign ifgt = decodeout_1[157];
assign ifle = decodeout_1[158];
assign if_icmpeq = decodeout_1[159];
assign if_icmpne = decodeout_1[160];
assign if_icmplt = decodeout_1[161];
assign if_icmpge = decodeout_1[162];
assign if_icmpgt = decodeout_1[163];
assign if_icmple = decodeout_1[164];
assign if_acmpeq = decodeout_1[165];
assign if_acmpne = decodeout_1[166];
assign goto = decodeout_1[167];
assign jsr = decodeout_1[168];
assign ret = decodeout_1[169];
assign tableswitch = decodeout_1[170];
assign lookupswitch = decodeout_1[171];
assign ireturn = decodeout_1[172];
assign lreturn = decodeout_1[173];
assign freturn = decodeout_1[174];
assign dreturn = decodeout_1[175];
assign areturn = decodeout_1[176];
assign return = decodeout_1[177];
assign getstatic = decodeout_1[178];
assign putstatic = decodeout_1[179];
assign getfield = decodeout_1[180];
assign putfield = decodeout_1[181];
assign invokevirtual = decodeout_1[182];
assign invokenonvirtual = decodeout_1[183];
assign invokestatic = decodeout_1[184];
assign invokeinterface = decodeout_1[185];
// decodeout_1[186] is unused JVM opcode
assign new = decodeout_1[187];
assign newarray = decodeout_1[188];
assign anewarray = decodeout_1[189];
assign arraylength = decodeout_1[190];
assign athrow = decodeout_1[191];
assign checkcast = decodeout_1[192];
assign instanceof = decodeout_1[193];
assign monitorenter = decodeout_1[194];
assign monitorexit = decodeout_1[195];
assign wide = decodeout_1[196];
assign multianewarray = decodeout_1[197];
assign ifnull = decodeout_1[198];
assign ifnonnull = decodeout_1[199];
assign goto_w = decodeout_1[200];
assign jsr_w = decodeout_1[201];
assign breakpoint = decodeout_1[202];
assign ldc_quick = decodeout_1[203];
assign ldc_w_quick = decodeout_1[204];
assign ldc2_w_quick = decodeout_1[205];
assign getfield_quick = decodeout_1[206];
assign putfield_quick = decodeout_1[207];
assign getfield2_quick = decodeout_1[208];
assign putfield2_quick = decodeout_1[209];
assign getstatic_quick = decodeout_1[210];
assign putstatic_quick = decodeout_1[211];
assign getstatic2_quick = decodeout_1[212];
assign putstatic2_quick = decodeout_1[213];
assign invokevirtual_quick = decodeout_1[214];
assign invokenonvirtual_quick = decodeout_1[215];
assign invokesuper_quick = decodeout_1[216];
assign invokestatic_quick = decodeout_1[217];
assign invokeinterface_quick = decodeout_1[218];
assign invokevirtualobject_quick = decodeout_1[219];
// assign invokeignored_quick = decodeout_1[220]; // Check this!
assign aastore_quick = decodeout_1[220];
assign new_quick = decodeout_1[221];
assign anewarray_quick = decodeout_1[222];
assign multianewarray_quick = decodeout_1[223];
assign checkcast_quick = decodeout_1[224];
assign instanceof_quick = decodeout_1[225];
assign invokevirtual_quick_w = decodeout_1[226];
assign getfield_quick_w = decodeout_1[227];
assign putfield_quick_w = decodeout_1[228];
assign nonnull_quick = decodeout_1[229];
assign agetfield_quick = decodeout_1[230];
assign aputfield_quick = decodeout_1[231];
assign agetstatic_quick = decodeout_1[232];
assign aputstatic_quick = decodeout_1[233];
assign aldc_quick = decodeout_1[234];
assign aldc_w_quick = decodeout_1[235];
assign exit_sync_method = decodeout_1[236];
assign sethi = decodeout_1[237];
assign load_word_index = decodeout_1[238];
assign load_short_index = decodeout_1[239];
assign load_char_index = decodeout_1[240];
assign load_byte_index = decodeout_1[241];
assign load_ubyte_index = decodeout_1[242];
assign store_word_index = decodeout_1[243];
assign nastore_word_index = decodeout_1[244];
assign store_short_index = decodeout_1[245];
assign store_byte_index = decodeout_1[246];
assign hardware = decodeout_1[255];
assign load_ubyte = hardware & (decodeout_2[0]);
assign load_byte = hardware & (decodeout_2[1]);
assign load_char = hardware & (decodeout_2[2]);
assign load_short = hardware & (decodeout_2[3]);
assign load_word = hardware & (decodeout_2[4]);
assign priv_ret_from_trap = hardware & (decodeout_2[5]);
assign priv_read_dcache_tag = hardware & (decodeout_2[6]);
assign priv_read_dcache_data = hardware & (decodeout_2[7]);
assign load_char_oe = hardware & (decodeout_2[10]);
assign load_short_oe = hardware & (decodeout_2[11]);
assign load_word_oe = hardware & (decodeout_2[12]);
assign return0 = hardware & (decodeout_2[13]);
assign priv_read_icache_tag = hardware & (decodeout_2[14]);
assign priv_read_icache_data = hardware & (decodeout_2[15]);
assign ncload_ubyte = hardware & (decodeout_2[16]);
assign ncload_byte = hardware & (decodeout_2[17]);
assign ncload_char = hardware & (decodeout_2[18]);
assign ncload_short = hardware & (decodeout_2[19]);
assign ncload_word = hardware & (decodeout_2[20]);
assign iucmp = hardware & (decodeout_2[21]);
assign priv_powerdown = hardware & (decodeout_2[22]);
assign cache_invalidate = hardware & (decodeout_2[23]);
assign ncload_char_oe = hardware & (decodeout_2[26]);
assign ncload_short_oe = hardware & (decodeout_2[27]);
assign ncload_word_oe = hardware & (decodeout_2[28]);
assign return1 = hardware & (decodeout_2[29]);
assign cache_flush = hardware & (decodeout_2[30]);
assign cache_index_flush = hardware & (decodeout_2[31]);
assign store_byte = hardware & (decodeout_2[32]);
assign store_short = hardware & (decodeout_2[34]);
assign store_word = hardware & (decodeout_2[36]);
assign soft_trap = hardware & (decodeout_2[37]);
assign priv_write_dcache_tag = hardware & (decodeout_2[38]);
assign priv_write_dcache_data = hardware & (decodeout_2[39]);
assign store_short_oe = hardware & (decodeout_2[42]);
assign store_word_oe = hardware & (decodeout_2[44]);
assign return2 = hardware & (decodeout_2[45]);
assign priv_write_icache_tag = hardware & (decodeout_2[46]);
assign priv_write_icache_data = hardware & (decodeout_2[47]);
assign ncstore_byte = hardware & (decodeout_2[48]);
assign ncstore_short = hardware & (decodeout_2[50]);
assign ncstore_word = hardware & (decodeout_2[52]);
assign priv_reset = hardware & (decodeout_2[54]);
assign get_current_class = hardware & (decodeout_2[55]);
assign ncstore_short_oe = hardware & (decodeout_2[58]);
assign ncstore_word_oe = hardware & (decodeout_2[60]);
assign call = hardware & (decodeout_2[61]);
assign zero_line = hardware & (decodeout_2[62]);
assign priv_update_optop = hardware & (decodeout_2[63]);
assign read_pc = hardware & (decodeout_2[64]);
assign read_vars = hardware & (decodeout_2[65]);
assign read_frame = hardware & (decodeout_2[66]);
assign read_optop = hardware & (decodeout_2[67]);
assign priv_read_oplim = hardware & (decodeout_2[68]);
assign read_const_pool = hardware & (decodeout_2[69]);
assign priv_read_psr = hardware & (decodeout_2[70]);
assign priv_read_trapbase = hardware & (decodeout_2[71]);
assign priv_read_lockcount0 = hardware & (decodeout_2[72]);
assign priv_read_lockcount1 = hardware & (decodeout_2[73]);
assign priv_read_lockaddr0 = hardware & (decodeout_2[76]);
assign priv_read_lockaddr1 = hardware & (decodeout_2[77]);
assign priv_read_userrange1 = hardware & (decodeout_2[80]);
assign priv_read_gc_config = hardware & (decodeout_2[81]);
assign priv_read_brk1a = hardware & (decodeout_2[82]);
assign priv_read_brk2a = hardware & (decodeout_2[83]);
assign priv_read_brk12c = hardware & (decodeout_2[84]);
assign priv_read_userrange2 = hardware & (decodeout_2[85]);
assign priv_read_versionid = hardware & (decodeout_2[87]);
assign priv_read_hcr = hardware & (decodeout_2[88]);
assign priv_read_sc_bottom = hardware & (decodeout_2[89]);
assign read_global0 = hardware & (decodeout_2[90]);
assign read_global1 = hardware & (decodeout_2[91]);
assign read_global2 = hardware & (decodeout_2[92]);
assign read_global3 = hardware & (decodeout_2[93]);
assign write_pc = hardware & (decodeout_2[96]);
assign write_vars = hardware & (decodeout_2[97]);
assign write_frame = hardware & (decodeout_2[98]);
assign write_optop = hardware & (decodeout_2[99]);
assign priv_write_oplim = hardware & (decodeout_2[100]);
assign write_const_pool = hardware & (decodeout_2[101]);
assign priv_write_psr = hardware & (decodeout_2[102]);
assign priv_write_trapbase = hardware & (decodeout_2[103]);
assign priv_write_lockcount0 = hardware & (decodeout_2[104]);
assign priv_write_lockcount1 = hardware & (decodeout_2[105]);
assign priv_write_lockaddr0 = hardware & (decodeout_2[108]);
assign priv_write_lockaddr1 = hardware & (decodeout_2[109]);
assign priv_write_userrange1 = hardware & (decodeout_2[112]);
assign priv_write_gc_config = hardware & (decodeout_2[113]);
assign priv_write_brk1a = hardware & (decodeout_2[114]);
assign priv_write_brk2a = hardware & (decodeout_2[115]);
assign priv_write_brk12c = hardware & (decodeout_2[116]);
assign priv_write_userrange2 = hardware & (decodeout_2[117]);
assign priv_write_sc_bottom = hardware & (decodeout_2[121]);
assign write_global0 = hardware & (decodeout_2[122]);
assign write_global1 = hardware & (decodeout_2[123]);
assign write_global2 = hardware & (decodeout_2[124]);
assign write_global3 = hardware & (decodeout_2[125]);
// Generate E stage nonnull_quick_e for null pointer exception logic
ff_sre nonnull_quick_reg(.out (nonnull_quick_e),
.din (nonnull_quick),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
// Generate control signals monitorenter and monitorexit
assign monitorenter_r = monitorenter;
ff_sre monitorenter_e_flop (.out(monitorenter_raw_e),
.din(monitorenter_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign monitorenter_e = monitorenter_raw_e & inst_valid[0]&~kill_inst_e;
assign monitorexit_r = monitorexit;
ff_sre monitorexit_e_flop (.out(monitorexit_raw_e),
.din(monitorexit_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign monitorexit_e = monitorexit_raw_e & inst_valid[0]&~kill_inst_e;
// Generate carry_in bit for adder
assign carry_in_r = isub | ineg | (lsub & first_cyc_r) |
(carry_out_e & lsub & second_cyc_r) |
(carry_out_e & ladd & second_cyc_r) |
(lneg & first_cyc_r) |
(carry_out_e & lneg & second_cyc_r);
ff_sre carry_in_e_flop (.out(carry_in_raw_e),
.din(carry_in_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign carry_in_e = (carry_in_raw_e | ucode_busy_e & (
(alu_adder_fn[1] & ~alu_adder_fn[0]) |
(~alu_adder_fn[1] & alu_adder_fn[0])))
& inst_valid[0];
// Generate control signals for mul/div
assign mul_r = imul;
ff_sre mul_e_flop (.out(mul_raw_e),
.din(mul_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign mul_e = mul_raw_e & inst_valid[0];
assign div_r = idiv;
ff_sre div_e_flop (.out(div_raw_e),
.din(div_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign div_e = div_raw_e & inst_valid[0];
assign rem_r = irem;
ff_sre rem_e_flop (.out(rem_raw_e),
.din(rem_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign rem_e = rem_raw_e & inst_valid[0];
assign shift_dir_r = ishr | (lshr & (first_cyc_r | second_cyc_r)) |
iushr | (lushr & (first_cyc_r | second_cyc_r));
ff_sre shift_dir_e_flop (.out(shift_dir_raw_e),
.din(shift_dir_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign shift_dir_e = shift_dir_raw_e & inst_valid[0];
// Control signals for shifter
assign shift_sel_r = ishl | ishr | iushr;
ff_sre shift_sel_flop (.out(shift_sel_raw),
.din(shift_sel_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign shift_sel = shift_sel_raw & inst_valid[0];
assign sign_r = ishr | nonnull_quick | (lcmp & first_cyc_r) |
ifeq | ifne | iflt | ifge | ifgt | ifle | if_icmpeq |
if_icmpne | if_icmplt | if_icmpge | if_icmpgt |
if_icmple | if_icmpeq | if_icmpne | if_acmpeq |
if_acmpne | ifnull | ifnonnull |
(lshr & (first_cyc_r | second_cyc_r));
ff_sre sign_e_flop (.out(sign_raw_e),
.din(sign_r),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
assign sign_e = sign_raw_e & inst_valid[0];
// Generate shift_count_e[5:0] from rs1_bypass_mux_out[5:0]
assign shift_32_r = ishl | ishr | iushr ;
assign shift_64_r = lshl | lshr | lushr ;
ff_sre shift_32_e_flop(.out(shift_32_e),
.din(shift_32_r),
.enable(~hold_e),
.reset_l(reset_l),
.clk(clk)
);
ff_sre shift_64_e_flop(.out(shift_64_e),
.din(shift_64_r),
.enable(~hold_e),
.reset_l(reset_l),
.clk(clk)
);
ff_sre_6 shift_count_e1_flop (.out(shift_count_e1[5:0]),
.din(rs1_bypass_mux_out[5:0]),
.enable(~hold_e),
.reset_l(reset_l),
.clk(clk)
);
assign shift_count_mux_sel[2] = shift_32_e;
assign shift_count_mux_sel[1] = shift_64_e & first_cyc_e;
assign shift_count_mux_sel[0] = shift_64_e & second_cyc_e;
mux3_6 shift_count_mux(.out(shift_count_e[5:0]),
.in2({1'b0, rs1_bypass_mux_out[4:0]}),
.in1(rs1_bypass_mux_out[5:0]),
.in0(shift_count_e1[5:0]),
.sel(shift_count_mux_sel[2:0]));
// Mux select for Bit or Convert outputs
assign bit_cvt_mux_sel_r[1] = iand | ior | ixor | jsr | jsr_w | fneg | dneg |
(lor & (first_cyc_r | second_cyc_r)) |
(lxor & (first_cyc_r | second_cyc_r)) |
(land & (first_cyc_r | second_cyc_r));
assign bit_cvt_mux_sel_r[0] = ~bit_cvt_mux_sel_r[1];
ff_sre_2 bit_cvt_mux_sel_reg (.out(bit_cvt_mux_sel[1:0]),
.din(bit_cvt_mux_sel_r[1:0]),
.clk(clk),
.enable(~hold_e),
.reset_l(reset_l));
// Mux select for ALU output
assign alu_out_mux_sel_r[7] = lcmp | iucmp;
assign alu_out_mux_sel_r[6] = imul | idiv | irem;
assign alu_out_mux_sel_r[5] = read_pc | read_vars |
read_frame | read_optop |
priv_read_oplim | read_const_pool |
priv_read_psr |
priv_read_trapbase | priv_read_lockcount0 |
priv_read_lockcount1 | priv_read_lockaddr0 |
priv_read_lockaddr1 | priv_read_userrange1 |
priv_read_gc_config | priv_read_brk1a |
priv_read_brk2a | priv_read_brk12c |
priv_read_userrange2 | priv_read_versionid |
priv_read_hcr | priv_read_sc_bottom;
assign alu_out_mux_sel_r[4] = iand | ior | ixor | i2l | jsr | jsr_w |
int2byte | int2char | int2short | sethi |
lor | lxor | land | fneg | dneg;
assign alu_out_mux_sel_r[3] = ishl | ishr | iushr | lshr | lushr | lshl ;
assign alu_out_mux_sel_r[2] = iadd | isub | ineg | iinc |
cache_invalidate | cache_flush | cache_index_flush |
ladd | lsub |lneg;
assign alu_out_mux_sel_r[1] = 1'b0;
assign alu_out_mux_sel_r[0] = ~(alu_out_mux_sel_r[7] |
alu_out_mux_sel_r[6] |
alu_out_mux_sel_r[5] |
alu_out_mux_sel_r[4] |
alu_out_mux_sel_r[3] |
alu_out_mux_sel_r[2] |
alu_out_mux_sel_r[1]) ;
ff_sre_8 alu_out_mux_sel_raw_e_reg (.out(alu_out_mux_sel_raw_e[7:0]),
.din(alu_out_mux_sel_r[7:0]),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_e)
);
assign ucode_read_reg_e =ucode_rd_psr_e|ucode_rd_vars_e|ucode_rd_frame_e|
ucode_rd_const_p_e;
assign alu_out_mux_sel[7] = alu_out_mux_sel_raw_e[7]&~ucode_busy_e;
assign alu_out_mux_sel[6] = alu_out_mux_sel_raw_e[6]&~ucode_busy_e;
assign alu_out_mux_sel[5] = alu_out_mux_sel_raw_e[5] | ucode_read_reg_e ;
assign alu_out_mux_sel[4] = alu_out_mux_sel_raw_e[4]&~ucode_busy_e;
assign alu_out_mux_sel[3] = alu_out_mux_sel_raw_e[3]&~ucode_busy_e;
assign alu_out_mux_sel[2] = alu_out_mux_sel_raw_e[2]&~ucode_busy_e;
assign alu_out_mux_sel[1] = ucode_rd_port_c_e;
assign alu_out_mux_sel[0] = ~(alu_out_mux_sel[7] |
alu_out_mux_sel[6] |
alu_out_mux_sel[5] |
alu_out_mux_sel[4] |
alu_out_mux_sel[3] |
alu_out_mux_sel[2] |
alu_out_mux_sel[1]) ;
assign adder2_src1_mux_sel_r = ~ucode_busy_r &
(ret | load_word_index | load_short_index |
load_char_index | load_byte_index |
load_ubyte_index | store_word_index |
nastore_word_index | store_short_index |
store_byte_index | load_ubyte | load_byte |
load_char | load_short | load_word |
priv_read_dcache_tag | priv_read_dcache_data |
load_char_oe | load_short_oe | load_word_oe |
priv_read_icache_tag | priv_read_icache_data |
ncload_ubyte | ncload_byte | ncload_char |
ncload_short | ncload_word | cache_invalidate |
ncload_char_oe | ncload_short_oe | ncload_word_oe |
cache_flush | cache_index_flush | store_byte |
store_short | store_word | priv_write_dcache_tag |
priv_write_dcache_data | store_short_oe |
store_word_oe | priv_write_icache_tag |
priv_write_icache_data | ncstore_byte |
ncstore_short | ncstore_word | ncstore_short_oe |
ncstore_word_oe | zero_line | write_pc);
ff_sre adder2_src1_mux_sel_reg
(.out(adder2_src1_mux_sel),
.din(adder2_src1_mux_sel_r),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_e)
);
// Mux select for source 2 of address adder
// Select offset for branch pc.
assign offset_branch_r = ~ucode_busy_r&(ifeq | ifne | iflt | ifge |
ifgt | ifle | if_icmpeq | if_icmpne |
if_icmplt | if_icmpge | if_icmpgt |
if_icmple | if_acmpeq | if_acmpne | goto |
jsr | ifnull | ifnonnull |goto_w |
jsr_w | load_word_index | load_short_index |
load_char_index | load_byte_index |
load_ubyte_index | store_word_index |
nastore_word_index | store_short_index |
store_byte_index);
ff_sre adder2_src2_mux_sel_reg
(.out(offset_branch_e),
.din(offset_branch_r),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_e)
);
assign adder2_src2_mux_sel[0] = ~sc_dcache_req & mem_adder_fn[1] & ~mem_adder_fn[0];
assign adder2_src2_mux_sel[1] = ~sc_dcache_req & mem_adder_fn[1]& mem_adder_fn[0];
assign adder2_src2_mux_sel[2] = ~sc_dcache_req & offset_branch_e;
assign adder2_src2_mux_sel[3] = ~(adder2_src2_mux_sel[0] | adder2_src2_mux_sel[2]
| adder2_src2_mux_sel[1]);
assign adder2_carry_in = ~sc_dcache_req&mem_adder_fn[1]&~mem_adder_fn[0];
assign wr_optop_mux_sel[1] = ucode_wr_vars_optop_e;
assign wr_optop_mux_sel[0] = ~wr_optop_mux_sel[1];
// Mux select for ucode_portc or rs2_bypass
assign iu_data_mux_sel_r[1] = ucode_busy_r;
assign iu_data_mux_sel_r[0] = ~iu_data_mux_sel_r[1];
ff_sre_2 iu_data_mux_sel_reg
(.out (iu_data_mux_sel[1:0]),
.din (iu_data_mux_sel_r[1:0]),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre iucmp_reg(.out (iucmp_e),
.din (iucmp),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre lcmp_reg(.out (lcmp_e),
.din (lcmp),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre first_cyc_reg(.out (first_cyc_e),
.din (first_cyc_r),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre second_cyc_reg(.out (second_cyc_e),
.din (second_cyc_r),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
assign iucmp_gt = iucmp_e & cmp_gt_e;
assign iucmp_eq = iucmp_e & cmp_eq_e;
assign iucmp_lt = iucmp_e & cmp_lt_e;
ff_sre first_gt_reg(.out (first_gt),
.din (lcmp_e & first_cyc_e & cmp_gt_e),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre first_eq_reg(.out (first_eq),
.din (lcmp_e & first_cyc_e & cmp_eq_e),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre first_lt_reg(.out (first_lt),
.din (lcmp_e & first_cyc_e & cmp_lt_e),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
assign second_gt = lcmp_e & second_cyc_e & first_eq & cmp_gt_e;
assign second_eq = lcmp_e & second_cyc_e & first_eq & cmp_eq_e;
assign second_lt = lcmp_e & second_cyc_e & first_eq & cmp_lt_e;
assign constant_mux_sel[2] = iucmp_gt | first_gt | second_gt;
assign constant_mux_sel[1] = iucmp_eq | second_eq;
assign constant_mux_sel[0] = iucmp_lt | first_lt | second_lt;
/****************************************************************************
* asynchronous_error due to smu access
***************************************************************************/
ff_sr smu_access_reg(.out (smu_access),
.din (smu_ld | smu_st),
.reset_l (reset_l),
.clk (clk)
);
assign mem_prot_stack = (range1_h_cmp2_gt | range1_h_cmp2_eq |
range1_l_cmp2_lt) &
(range2_h_cmp2_gt | range2_h_cmp2_eq |
range2_l_cmp2_lt);
assign async_error = mem_prot_stack & psr_ace & psr_cac & smu_access;
/****************************************************************************
* mem_protection_error
***************************************************************************/
/*
* Because zero_line is not accounted for within iu_inst_e[3] (store) and
* iu_inst_e[2] (load), it is brought to E stage and OR'd into the equation.
*/
/*
* iu_inst_raw[3:2] is checked when PSR.CAC = 0, which is extended ld/st
* only. iu_inst_e[3:2] contains DCU access from ucode.
*/
assign load_store_e = iu_inst_raw_e[3] | iu_inst_raw_e[2] |
psr_cac & (iu_load_e | iu_store_e| iu_zero_e |iu_dcu_flush_e[0]);
ff_sre load_store_c_reg(.out(load_store_c),
.din (load_store_e),
.enable (~hold_c),
.reset_l (reset_l),
.clk (clk)
);
// Removed term iu_load_e.
assign data_st_e = iu_store_e | iu_zero_e |iu_dcu_flush_e[0];
assign mem_prot_ldst = (range1_h_cmp1_gt | range1_h_cmp1_eq |
range1_l_cmp1_lt) &
(range2_h_cmp1_gt | range2_h_cmp1_eq |
range2_l_cmp1_lt);
assign mem_prot_error_c = mem_prot_ldst & psr_ace & load_store_c &
inst_valid[1];
/****************************************************************************
* breakpoint1 and breakpoint2
***************************************************************************/
/*
* Don't need to qualify breakpoints with BRK12C.HALT, because trap logic
* will determine that and it still needs to see breakpoint signals coming
* out.
*/
// Data breakpoint 1
assign data_brk1_eq[6] = data_brk1_31_13_eq | ~brk12c_brkm1[6];
assign data_brk1_eq[5] = data_brk1_misc_eq[4] | ~brk12c_brkm1[5];
assign data_brk1_eq[4] = data_brk1_11_4_eq | ~brk12c_brkm1[4];
assign data_brk1_eq[3:0] = data_brk1_misc_eq[3:0] | ~brk12c_brkm1[3:0];
assign data_brk1_match_e = &data_brk1_eq[6:0];
assign data_brk1_vld_e = (iu_load_e&~brk12c_srcbk1[0]| data_st_e&brk12c_srcbk1[0])&
~(psr_su & brk12c_subk1)&brk12c_brken1&~brk12c_srcbk1[1]&inst_valid[0];
assign data_brk1_e = data_brk1_match_e&data_brk1_vld_e;
// Removed inst_valid term as data_bkpt gets killed during data loads for S$ miss. Also
// included trap_in_progress signal for enable of data_brk_c flop.
assign data_brk1_c = data_brk1_c_int;
ff_sre data_brk1_c_reg(.out(data_brk1_c_int),.din(data_brk1_e),.clk(clk),
.reset_l((reset_l & !pj_resume)),.enable(!hold_c|trap_in_progress));
// Data breakpoint 2
assign data_brk2_eq[6] = data_brk2_31_13_eq | ~brk12c_brkm2[6];
assign data_brk2_eq[5] = data_brk2_misc_eq[4] | ~brk12c_brkm2[5];
assign data_brk2_eq[4] = data_brk2_11_4_eq | ~brk12c_brkm2[4];
assign data_brk2_eq[3:0] = data_brk2_misc_eq[3:0] | ~brk12c_brkm2[3:0];
assign data_brk2_match_e = &data_brk2_eq[6:0];
assign data_brk2_vld_e = (iu_load_e&~brk12c_srcbk2[0]| data_st_e&brk12c_srcbk2[0])&
~(psr_su & brk12c_subk2)&brk12c_brken2&~brk12c_srcbk2[1]&inst_valid[0];
assign data_brk2_e = data_brk2_match_e&data_brk2_vld_e;
assign data_brk2_c = data_brk2_c_int;
ff_sre data_brk2_c_reg(.out(data_brk2_c_int),.din(data_brk2_e),.clk(clk),
.reset_l((reset_l & !pj_resume)),.enable(!hold_c|trap_in_progress));
// Instruction breakpoint 1
assign inst_brk1_eq[6] = inst_brk1_31_13_eq | ~brk12c_brkm1[6];
assign inst_brk1_eq[5] = inst_brk1_misc_eq[4] | ~brk12c_brkm1[5];
assign inst_brk1_eq[4] = inst_brk1_11_4_eq | ~brk12c_brkm1[4];
assign inst_brk1_eq[3:0] = inst_brk1_misc_eq[3:0] | ~brk12c_brkm1[3:0];
assign inst_brk1_match = &inst_brk1_eq[6:0];
assign inst_brk1_taken = inst_brk1_match & valid_op_r &
~(psr_su & brk12c_subk1) & brk12c_srcbk1[1] &
brk12c_srcbk1[0] & brk12c_brken1;
assign inst_brk1_r = inst_brk1_taken & ~psr_fle;
// Instruction breakpoint 2
assign inst_brk2_eq[6] = inst_brk2_31_13_eq | ~brk12c_brkm2[6];
assign inst_brk2_eq[5] = inst_brk2_misc_eq[4] | ~brk12c_brkm2[5];
assign inst_brk2_eq[4] = inst_brk2_11_4_eq | ~brk12c_brkm2[4];
assign inst_brk2_eq[3:0] = inst_brk2_misc_eq[3:0] | ~brk12c_brkm2[3:0];
assign inst_brk2_match = &inst_brk2_eq[6:0];
assign inst_brk2_taken = inst_brk2_match & valid_op_r &
~(psr_su & brk12c_subk2) & brk12c_srcbk2[1] &
brk12c_srcbk2[0] & brk12c_brken2;
assign inst_brk2_r = inst_brk2_taken & ~psr_fle;
/****************************************************************************
* runtime_NullPtrException
***************************************************************************/
assign null_ptr_exception_e = (monitorenter_raw_e | monitorexit_raw_e |
nonnull_quick_e) & null_objref_e & ~kill_inst_e&
inst_valid[0];
/****************************************************************************
* monitorenter/monitorexit
* LockCountOverflowTrap, LockEnterMissTrap, LockExitMissTrap,
* and LockReleaseTrap
***************************************************************************/
// First create some shared signals
assign lock0_enter = monitorenter_e & la0_hit & ~null_objref_e;
assign lock0_exit = monitorexit_e & la0_hit & ~null_objref_e;
assign lock1_enter = monitorenter_e & la1_hit & ~null_objref_e;
assign lock1_exit = monitorexit_e & la1_hit & ~null_objref_e;
// monitorenter/monitorexit
assign lc0_din_mux_sel[3] = lock0_cache; // lc0_p1
assign lc0_din_mux_sel[2] = lock0_enter; // lc0_p1
assign lc0_din_mux_sel[1] = lock0_exit; // lc0_m1
assign lc0_din_mux_sel[0] = ~(|lc0_din_mux_sel[3:1]); // wr_lc0
assign lc0_count_reg_we = (lock0_enter | lock0_exit |reg_wr_mux_sel[8] |
lock0_cache) & ~hold_e;
assign lc1_din_mux_sel[3] = lock1_cache; // lc1_p1
assign lc1_din_mux_sel[2] = lock1_enter; // lc1_p1
assign lc1_din_mux_sel[1] = lock1_exit; // lc1_m1
assign lc1_din_mux_sel[0] = ~(|lc1_din_mux_sel[3:1]); // wr_lc1
assign lc1_count_reg_we = (lock1_enter | lock1_exit | reg_wr_mux_sel[9] |
lock1_cache) & ~hold_e;
// LockCountOverflowTrap
assign lock0_overflow = lock0_enter & lc0_eq_255;
assign lock0_underflow = lock0_exit & lc0_eq_0;
assign lock1_overflow = lock1_enter & lc1_eq_255;
assign lock1_underflow = lock1_exit & lc1_eq_0;
assign lock_count_overflow_e = (lock0_overflow | lock0_underflow |
lock1_overflow | lock1_underflow) &
~hold_e;
// LockEnterMissTrap & LockExitMissTrap
assign lock_miss_valid = ~la0_hit & ~la1_hit & ~null_objref_e;
assign lock_enter_miss_e = lock_miss_valid & (((la0_null_e | la1_null_e) & lockbit) |
(~(la0_null_e | la1_null_e))) & ~hold_e & monitorenter_e;
assign lock_exit_miss_e = monitorexit_e & lock_miss_valid;
// LockReleaseTrap
assign lock0_release = lc0_m1_eq_0 & lock0_exit & lockwant0;
assign lock1_release = lc1_m1_eq_0 & lock1_exit & lockwant1;
assign lock_release_e = (lock0_release | lock1_release) & inst_valid[0];
// lock0_cache and lock1_cache
assign lock0_cache = ~lockbit & ~hold_e & lock_miss_valid & la0_null_e & monitorenter_e;
assign lock1_cache = ~lockbit & ~hold_e & lock_miss_valid & ~la0_null_e & la1_null_e & monitorenter_e;
// lock0_uncache and lock1_uncache
assign lock0_uncache = lock0_exit & lc0_m1_eq_0 & lc0_co_bit & ~lockwant0;
assign lock1_uncache = lock1_exit & lc1_m1_eq_0 & lc1_co_bit & ~lockwant1;
/*
* The load buffer state machine
*/
assign load_buffer_mux_sel[1] = curr_s;
assign load_buffer_mux_sel[0] = ~load_buffer_mux_sel[1];
assign dcu_data_reg_we[0] = ~hold_c & all_load_c&inst_valid[1]&~sc_data_vld;
assign dcu_data_reg_we[1] = iu_data_vld&~sc_data_vld | icu_data_vld;
assign next_s = load_buffer_fsm(curr_s,
dcu_data_reg_we[1],
hold_c
);
ff_sr load_buffer_fsm_reg(.out (curr_s),
.din (next_s),
.reset_l (reset_l),
.clk (clk)
);
function load_buffer_fsm;
input current_state;
input valid;
input hold;
reg next_state;
parameter IDLE = 1'b0,
HOLD = 1'b1;
begin : fsm
case (current_state)
IDLE:
if (hold & valid)
next_state = HOLD;
else
next_state = current_state;
HOLD:
if (~hold & ~valid)
next_state = IDLE;
else
next_state = current_state;
default:
next_state = 1'bx;
endcase // case(current_state)
load_buffer_fsm = next_state;
end // block: fsm
endfunction // load_buffer_fsm
/*
* Now the register mux select for read and write are separated to support
* rd/wr register at the same cycle. This is primarily for ucode.
*/
// Select which register to read from
assign reg_rd_mux_sel_r[20] = priv_read_sc_bottom;
assign reg_rd_mux_sel_r[19] = priv_read_hcr;
assign reg_rd_mux_sel_r[18] = priv_read_versionid;
assign reg_rd_mux_sel_r[17] = priv_read_userrange2;
assign reg_rd_mux_sel_r[16] = priv_read_brk12c;
assign reg_rd_mux_sel_r[15] = priv_read_brk2a;
assign reg_rd_mux_sel_r[14] = priv_read_brk1a;
assign reg_rd_mux_sel_r[13] = priv_read_gc_config;
assign reg_rd_mux_sel_r[12] = priv_read_userrange1;
assign reg_rd_mux_sel_r[11] = priv_read_lockaddr1;
assign reg_rd_mux_sel_r[10] = priv_read_lockaddr0;
assign reg_rd_mux_sel_r[9] = priv_read_lockcount1;
assign reg_rd_mux_sel_r[8] = priv_read_lockcount0;
assign reg_rd_mux_sel_r[7] = priv_read_trapbase;
assign reg_rd_mux_sel_r[6] = priv_read_psr;
assign reg_rd_mux_sel_r[5] = read_const_pool;
assign reg_rd_mux_sel_r[4] = priv_read_oplim;
assign reg_rd_mux_sel_r[3] = read_optop;
assign reg_rd_mux_sel_r[2] = read_frame;
assign reg_rd_mux_sel_r[1] = read_vars;
assign reg_rd_mux_sel_r[0] = ~(|reg_rd_mux_sel_r[20:1]);
ff_sre_21 reg_rd_mux_sel_raw_e_reg(.out (reg_rd_mux_sel_raw_e[20:0]),
.din (reg_rd_mux_sel_r[20:0]),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
// Select which register to write to
assign reg_wr_mux_sel_r[18] = priv_write_sc_bottom;
assign reg_wr_mux_sel_r[17] = priv_write_userrange2;
assign reg_wr_mux_sel_r[16] = priv_write_brk12c;
assign reg_wr_mux_sel_r[15] = priv_write_brk2a;
assign reg_wr_mux_sel_r[14] = priv_write_brk1a;
assign reg_wr_mux_sel_r[13] = priv_write_gc_config;
assign reg_wr_mux_sel_r[12] = priv_write_userrange1;
assign reg_wr_mux_sel_r[11] = priv_write_lockaddr1;
assign reg_wr_mux_sel_r[10] = priv_write_lockaddr0;
assign reg_wr_mux_sel_r[9] = priv_write_lockcount1;
assign reg_wr_mux_sel_r[8] = priv_write_lockcount0;
assign reg_wr_mux_sel_r[7] = priv_write_trapbase;
assign reg_wr_mux_sel_r[6] = priv_write_psr;
assign reg_wr_mux_sel_r[5] = write_const_pool;
assign reg_wr_mux_sel_r[4] = priv_write_oplim |
(priv_update_optop & second_cyc_r);
assign reg_wr_mux_sel_r[3] = write_optop |
(priv_update_optop & first_cyc_r);
assign reg_wr_mux_sel_r[2] = write_frame;
assign reg_wr_mux_sel_r[1] = write_vars;
assign reg_wr_mux_sel_r[0] = ~(|reg_wr_mux_sel_r[18:1]);
ff_sre_19 reg_wr_mux_sel_raw_e_reg(.out (reg_wr_mux_sel_raw_e[18:0]),
.din (reg_wr_mux_sel_r[18:0]),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
// ucode register select
assign ucode_rd_psr_e = ~ucode_reg_rd[2] & ~ucode_reg_rd[1] & ucode_reg_rd[0];
assign ucode_rd_vars_e = ~ucode_reg_rd[2] & ucode_reg_rd[1] & ~ucode_reg_rd[0];
assign ucode_rd_frame_e = ~ucode_reg_rd[2] & ucode_reg_rd[1] & ucode_reg_rd[0];
assign ucode_rd_const_p_e = ucode_reg_rd[2] & ~ucode_reg_rd[1] & ~ucode_reg_rd[0];
assign ucode_rd_port_c_e = ucode_reg_rd[2] & ~ucode_reg_rd[1] & ucode_reg_rd[0];
assign ucode_rd_dcache_e = ucode_reg_rd[2] & ucode_reg_rd[1] & ~ucode_reg_rd[0];
assign ucode_rd_part_dcache_e = ucode_reg_rd[2] & ucode_reg_rd[1] & ucode_reg_rd[0];
ff_sre_2 ucode_rd_part_dcache_c_reg (.out({ucode_rd_dcache_c,ucode_rd_part_dcache_c}),
.din({ucode_rd_dcache_e,ucode_rd_part_dcache_e}),
.clk(clk),
.reset_l(reset_l),
.enable(~hold_c)
);
assign ucode_wr_pc_e = ~ucode_reg_wr[2] & ~ucode_reg_wr[1] & ucode_reg_wr[0];
assign ucode_wr_vars_e = ~ucode_reg_wr[2] & ucode_reg_wr[1] & ~ucode_reg_wr[0];
assign ucode_wr_frame_e = ~ucode_reg_wr[2] & ucode_reg_wr[1] & ucode_reg_wr[0];
assign ucode_wr_const_p_e = ucode_reg_wr[2] & ~ucode_reg_wr[1] & ~ucode_reg_wr[0];
assign ucode_wr_optop_e = ucode_reg_wr[2] & ~ucode_reg_wr[1] & ucode_reg_wr[0];
assign ucode_wr_vars_optop_e = ucode_reg_wr[2] & ucode_reg_wr[1] & ~ucode_reg_wr[0];
assign ucode_wr_psr_e = ucode_reg_wr[2] & ucode_reg_wr[1] & ucode_reg_wr[0];
/*
* Separte the rd/wr register mux select for ucode support
*/
assign reg_rd_mux_sel[20:7] = reg_rd_mux_sel_raw_e[20:7];
assign reg_rd_mux_sel[6] = reg_rd_mux_sel_raw_e[6] | ucode_rd_psr_e;
assign reg_rd_mux_sel[5] = reg_rd_mux_sel_raw_e[5] | ucode_rd_const_p_e;
assign reg_rd_mux_sel[4] = reg_rd_mux_sel_raw_e[4];
assign reg_rd_mux_sel[3] = reg_rd_mux_sel_raw_e[3];
assign reg_rd_mux_sel[2] = reg_rd_mux_sel_raw_e[2] | ucode_rd_frame_e;
assign reg_rd_mux_sel[1] = reg_rd_mux_sel_raw_e[1] | ucode_rd_vars_e;
assign reg_rd_mux_sel[0] = ~(|reg_rd_mux_sel[20:1]);
assign reg_wr1_mux_sel[18:7] = reg_wr_mux_sel_raw_e[18:7];
// write enable to SMU's version of sbase signal whenever there's
// write_sbase opcode - This is done to improve timing on smu_stall
// signal
assign iu_sbase_we = reg_wr_mux_sel[18];
assign reg_wr1_mux_sel[6] = reg_wr_mux_sel_raw_e[6] | ucode_wr_psr_e;
assign reg_wr1_mux_sel[5] = reg_wr_mux_sel_raw_e[5] | ucode_wr_const_p_e;
assign reg_wr1_mux_sel[4] = reg_wr_mux_sel_raw_e[4];
assign reg_wr1_mux_sel[3] = reg_wr_mux_sel_raw_e[3] | ucode_wr_optop_e;
assign reg_wr1_mux_sel[2] = reg_wr_mux_sel_raw_e[2] | ucode_wr_frame_e;
assign reg_wr1_mux_sel[1] = reg_wr_mux_sel_raw_e[1] | ucode_wr_vars_e;
assign reg_wr1_mux_sel[0] = ~(|reg_wr1_mux_sel[18:1]);
// Remember to qualify it with inst_valid[0] and ~iu_trap_c, because there
// is no reg_wr_e anymore.
assign reg_wr_mux_sel[18:0] = reg_wr1_mux_sel[18:0] & {19{inst_valid[0]&~hold_c}} &
{19{~kill_inst_e&~iu_trap_c}};
// This mux is used to select data input for the load buffer.
// Mux to select (icu_diag data ,dcu_dia data, dcu_data)
assign load_data_mux_sel_r[2] = priv_read_icache_tag | priv_read_icache_data;
assign load_data_mux_sel_r[1] = priv_read_dcache_tag | priv_read_dcache_data;
assign load_data_mux_sel_r[0] = ~(|load_data_mux_sel_r[2:1]);
ff_sre_3 load_data_mux_sel_e_reg(.out (load_data_mux_sel_e[2:0]),
.din (load_data_mux_sel_r[2:0]),
.enable (~hold_e),
.reset_l (reset_l),
.clk (clk)
);
ff_sre_3 load_data_mux_sel_reg (.out (load_data_c_mux_sel[2:0]),
.din (load_data_mux_sel_e[2:0]),
.enable (~hold_c),
.reset_l (reset_l),
.clk (clk)
);
assign icu_diag_ld_c = load_data_c_mux_sel[2]&inst_valid[1];
ff_sre fpop_reg(.out (fpu_op_e),
.din (fpu_op_r),
.enable(~hold_e),
.reset_l(reset_l),
.clk (clk)
);
assign fpu_mux_sel[1] = fpu_op_e ;
assign fpu_mux_sel[0] = ~fpu_op_e ;
// Mux to select (output of dcu_hold reg. or output of W stage alu_out reg)
// select dcache data for ucode only if there is either rd_dcache_w or rd_part_dcache_w
// is active. else select the alu_out_w data. Also select dcache data for
// normal loads in the W stage
assign forward_data_w_mux_sel_c[1] = ucode_rd_part_dcache_c | ucode_rd_dcache_c
| all_load_c&~ucode_busy_c;
assign forward_data_w_mux_sel_c[0] = ~forward_data_w_mux_sel_c[1];
// To improve timing on RS1 and RS2, we are moving all the mux selects to ex_dpath
assign forward_w_sel_din = forward_data_w_mux_sel_c;
// Mux sel for output from cmp
assign cmp_mux_sel_r[2] = ifeq | ifne | iflt | ifge | ifgt |
ifle | nonnull_quick | ifnull | ifnonnull;
assign cmp_mux_sel_r[1] = if_acmpeq | if_acmpne ;
assign cmp_mux_sel_r[0] = ~cmp_mux_sel_r[1]&~cmp_mux_sel_r[2];
ff_sre_3 cmp_mux_sel_reg (.out(cmp_mux_sel[2:0]),
.din(cmp_mux_sel_r[2:0]),
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Created: | Wed Mar 24 09:45:03 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/iu/ex/rtl/ex_ctl.v
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