pgnx_fa32 pg_3 ( .gen_l(gi_l[3]), .pro_l(pi_l[3]), .ain(ai[3]), .bin(bi[3]));
pgnx_fa32 pg_2 ( .gen_l(gi_l[2]), .pro_l(pi_l[2]), .ain(ai[2]), .bin(bi[2]));
pgnx_fa32 pg_1 ( .gen_l(gi_l[1]), .pro_l(pi_l[1]), .ain(ai[1]), .bin(bi[1]));
pgnl_fa32 pg_0 ( .gen_l(gi_l[0]), .pro_l(pi_l[0]), .ain(ai[0]), .bin(bi[0]), .carryin(cin));
/* pg2_fa32 stage */
pg2_fa32 pg_31_30 ( .g_u_d(g31_30),
.p_u_d(p30_29),
.g_l_in(gi_l[31:30]),
.p_l_in(pi_l[30:29]));
pg2_fa32 pg_29_28 ( .g_u_d(g2_fa329_28),
.p_u_d(p28_27),
.g_l_in(gi_l[29:28]),
.p_l_in(pi_l[28:27]));
pg2_fa32 pg_27_26 ( .g_u_d(g2_fa327_26),
.p_u_d(p26_25),
.g_l_in(gi_l[27:26]),
.p_l_in(pi_l[26:25]));
pg2_fa32 pg_25_24 ( .g_u_d(g2_fa325_24),
.p_u_d(p24_23),
.g_l_in(gi_l[25:24]),
.p_l_in(pi_l[24:23]));
pg2_fa32 pg_23_22 ( .g_u_d(g2_fa323_22),
.p_u_d(p22_21),
.g_l_in(gi_l[23:22]),
.p_l_in(pi_l[22:21]));
pg2_fa32 pg_21_20 ( .g_u_d(g2_fa321_20),
.p_u_d(p20_19),
.g_l_in(gi_l[21:20]),
.p_l_in(pi_l[20:19]));
pg2_fa32 pg_19_18 ( .g_u_d(g19_18),
.p_u_d(p18_17),
.g_l_in(gi_l[19:18]),
.p_l_in(pi_l[18:17]));
pg2_fa32 pg_17_16 ( .g_u_d(g17_16),
.p_u_d(p16_15),
.g_l_in(gi_l[17:16]),
.p_l_in(pi_l[16:15]));
pg2_fa32 pg_15_14 ( .g_u_d(g15_14),
.p_u_d(p14_13),
.g_l_in(gi_l[15:14]),
.p_l_in(pi_l[14:13]));
pg2_fa32 pg_13_12 ( .g_u_d(g13_12),
.p_u_d(p12_11),
.g_l_in(gi_l[13:12]),
.p_l_in(pi_l[12:11]));
pg2_fa32 pg_11_10 ( .g_u_d(g11_10),
.p_u_d(p10_9),
.g_l_in(gi_l[11:10]),
.p_l_in(pi_l[10:9]));
pg2_fa32 pg_9_8 ( .g_u_d(g9_8),
.p_u_d(p8_7),
.g_l_in(gi_l[9:8]),
.p_l_in(pi_l[8:7]));
pg2_fa32 pg_7_6 ( .g_u_d(g7_6),
.p_u_d(p6_5),
.g_l_in(gi_l[7:6]),
.p_l_in(pi_l[6:5]));
pg2_fa32 pg_5_4 ( .g_u_d(g5_4),
.p_u_d(p4_3),
.g_l_in(gi_l[5:4]),
.p_l_in(pi_l[4:3]));
pg2_fa32 pg_3_2 ( .g_u_d(g3_2),
.p_u_d(p2_1),
.g_l_in(gi_l[3:2]),
.p_l_in(pi_l[2:1]));
g2_fa32 g_1_0 ( .g_u_d(g1_0),
.g_l_in(gi_l[1:0]));
/* b1 stage */
b1aoi_fa32 pg_31_28 ( .ggrp_l(g31_28_l),
.pgrp_l(p30_27_l),
.gu_in(g31_30),
.pu_in(p30_29),
.gd_in(g2_fa329_28),
.pd_in(p28_27));
b1aoi_fa32 pg_27_24 ( .ggrp_l(g2_fa327_24_l),
.pgrp_l(p26_23_l),
.gu_in(g2_fa327_26),
.pu_in(p26_25),
.gd_in(g2_fa325_24),
.pd_in(p24_23));
b1aoi_fa32 pg_23_20 ( .ggrp_l(g2_fa323_20_l),
.pgrp_l(p22_19_l),
.gu_in(g2_fa323_22),
.pu_in(p22_21),
.gd_in(g2_fa321_20),
.pd_in(p20_19));
b1aoi_fa32 pg_19_16 ( .ggrp_l(g19_16_l),
.pgrp_l(p18_15_l),
.gu_in(g19_18),
.pu_in(p18_17),
.gd_in(g17_16),
.pd_in(p16_15));
b1aoi_fa32 pg_15_12 ( .ggrp_l(g15_12_l),
.pgrp_l(p14_11_l),
.gu_in(g15_14),
.pu_in(p14_13),
.gd_in(g13_12),
.pd_in(p12_11));
b1aoi_fa32 pg_11_8 ( .ggrp_l(g11_8_l),
.pgrp_l(p10_7_l),
.gu_in(g11_10),
.pu_in(p10_9),
.gd_in(g9_8),
.pd_in(p8_7));
b1aoi_fa32 pg_7_4 ( .ggrp_l(g7_4_l),
.pgrp_l(p6_3_l),
.gu_in(g7_6),
.pu_in(p6_5),
.gd_in(g5_4),
.pd_in(p4_3));
g1aoi_fa32 g_3_0 ( .ggrp_l(g3_0_l),
.gu_in(g3_2),
.pu_in(p2_1),
.gd_in(g1_0));
/* b2 stage */
b2oai_fa32 pg_31_24 ( .ggrp(g31_24),
.pgrp(p30_23),
.gu_in(g31_28_l),
.pu_in(p30_27_l),
.gd_in(g2_fa327_24_l),
.pd_in(p26_23_l));
b2oai_fa32 pg_27_20 ( .ggrp(g2_fa327_20),
.pgrp(p26_19),
.gu_in(g2_fa327_24_l),
.pu_in(p26_23_l),
.gd_in(g2_fa323_20_l),
.pd_in(p22_19_l));
b2oai_fa32 pg_23_16 ( .ggrp(g2_fa323_16),
.pgrp(p22_15),
.gu_in(g2_fa323_20_l),
.pu_in(p22_19_l),
.gd_in(g19_16_l),
.pd_in(p18_15_l));
b2oai_fa32 pg_19_12 ( .ggrp(g19_12),
.pgrp(p18_11),
.gu_in(g19_16_l),
.pu_in(p18_15_l),
.gd_in(g15_12_l),
.pd_in(p14_11_l));
b2oai_fa32 pg_15_8 ( .ggrp(g15_8),
.pgrp(p14_7),
.gu_in(g15_12_l),
.pu_in(p14_11_l),
.gd_in(g11_8_l),
.pd_in(p10_7_l));
b2oai_fa32 pg_11_4 ( .ggrp(g11_4),
.pgrp(p10_3),
.gu_in(g11_8_l),
.pu_in(p10_7_l),
.gd_in(g7_4_l),
.pd_in(p6_3_l));
g2oai_fa32 g_7_0 ( .ggrp(g7_0),
.gu_in(g7_4_l),
.pu_in(p6_3_l),
.gd_in(g3_0_l));
assign w2_3_0 = ~ g3_0_l;
/* b3 stage */
b3aoi_fa32 pg_31_16 ( .ggrp_l(g31_16_l),
.pgrp_l(p30_15_l),
.gu_in(g31_24),
.pu_in(p30_23),
.gd_in(g2_fa323_16),
.pd_in(p22_15));
b3aoi_fa32 pg_27_12 ( .ggrp_l(g2_fa327_12_l),
.pgrp_l(p26_11_l),
.gu_in(g2_fa327_20),
.pu_in(p26_19),
.gd_in(g19_12),
.pd_in(p18_11));
b3aoi_fa32 pg_23_8 ( .ggrp_l(g2_fa323_8_l),
.pgrp_l(p22_7_l),
.gu_in(g2_fa323_16),
.pu_in(p22_15),
.gd_in(g15_8),
.pd_in(p14_7));
b3aoi_fa32 pg_19_4 ( .ggrp_l(g19_4_l),
.pgrp_l(p18_3_l),
.gu_in(g19_12),
.pu_in(p18_11),
.gd_in(g11_4),
.pd_in(p10_3));
g3aoi_fa32 g_15_0 ( .ggrp_l(g15_0_l),
.gu_in(g15_8),
.pu_in(p14_7),
.gd_in(g7_0));
g3aoi_fa32 g_11_0 ( .ggrp_l(g11_0_l),
.gu_in(g11_4),
.pu_in(p10_3),
.gd_in(w2_3_0));
assign w3i_7_0 = ~ g7_0;
assign w3i_3_0 = ~ w2_3_0;
/* g4 stage */
g4oai_fa32 g_31_0 ( .ggrp(g31_0),
.gu_in(g31_16_l),
.pu_in(p30_15_l),
.gd_in(g15_0_l));
g4oai_fa32 g_27_0 ( .ggrp(g2_fa327_0),
.gu_in(g2_fa327_12_l),
.pu_in(p26_11_l),
.gd_in(g11_0_l));
g4oai_fa32 g_23_0 ( .ggrp(g2_fa323_0),
.gu_in(g2_fa323_8_l),
.pu_in(p22_7_l),
.gd_in(w3i_7_0));
g4oai_fa32 g_19_0 ( .ggrp(g19_0),
.gu_in(g19_4_l),
.pu_in(p18_3_l),
.gd_in(w3i_3_0));
assign w4_15_0 = ~ g15_0_l;
assign w4_11_0 = ~ g11_0_l;
assign w4_7_0 = ~ w3i_7_0;
assign w4_3_0 = ~ w3i_3_0;
/* Local Sum, Carry-select stage */
presum_fa32 psum31_28 (.g1(~gi_l[28]), .g2_fa32(~gi_l[29]), .g3(~gi_l[30]), .g4(~gi_l[31]),
.p0(~pi_l[27]), .p1(~pi_l[28]), .p2(~pi_l[29]), .p3(~pi_l[30]), .p4(~pi_l[31]),
.s1(in[28]), .s2(in[29]), .s3(in[30]), .s4(in[31]),
.s1b(inb[28]), .s2b(inb[29]), .s3b(inb[30]), .s4b(inb[31]));
presum_fa32 psum27_24 (.g1(~gi_l[24]), .g2_fa32(~gi_l[25]), .g3(~gi_l[26]), .g4(~gi_l[27]),
.p0(~pi_l[23]), .p1(~pi_l[24]), .p2(~pi_l[25]), .p3(~pi_l[26]), .p4(~pi_l[27]),
.s1(in[24]), .s2(in[25]), .s3(in[26]), .s4(in[27]),
.s1b(inb[24]), .s2b(inb[25]), .s3b(inb[26]), .s4b(inb[27]));
presum_fa32 psum23_20 (.g1(~gi_l[20]), .g2_fa32(~gi_l[21]), .g3(~gi_l[22]), .g4(~gi_l[23]),
.p0(~pi_l[19]), .p1(~pi_l[20]), .p2(~pi_l[21]), .p3(~pi_l[22]), .p4(~pi_l[23]),
.s1(in[20]), .s2(in[21]), .s3(in[22]), .s4(in[23]),
.s1b(inb[20]), .s2b(inb[21]), .s3b(inb[22]), .s4b(inb[23]));
presum_fa32 psum19_16 (.g1(~gi_l[16]), .g2_fa32(~gi_l[17]), .g3(~gi_l[18]), .g4(~gi_l[19]),
.p0(~pi_l[15]), .p1(~pi_l[16]), .p2(~pi_l[17]), .p3(~pi_l[18]), .p4(~pi_l[19]),
.s1(in[16]), .s2(in[17]), .s3(in[18]), .s4(in[19]),
.s1b(inb[16]), .s2b(inb[17]), .s3b(inb[18]), .s4b(inb[19]));
presum_fa32 psum15_12 (.g1(~gi_l[12]), .g2_fa32(~gi_l[13]), .g3(~gi_l[14]), .g4(~gi_l[15]),
.p0(~pi_l[11]), .p1(~pi_l[12]), .p2(~pi_l[13]), .p3(~pi_l[14]), .p4(~pi_l[15]),
.s1(in[12]), .s2(in[13]), .s3(in[14]), .s4(in[15]),
.s1b(inb[12]), .s2b(inb[13]), .s3b(inb[14]), .s4b(inb[15]));
presum_fa32 psum11_8 (.g1(~gi_l[8]), .g2_fa32(~gi_l[9]), .g3(~gi_l[10]), .g4(~gi_l[11]),
.p0(~pi_l[7]), .p1(~pi_l[8]), .p2(~pi_l[9]), .p3(~pi_l[10]), .p4(~pi_l[11]),
.s1(in[8]), .s2(in[9]), .s3(in[10]), .s4(in[11]),
.s1b(inb[8]), .s2b(inb[9]), .s3b(inb[10]), .s4b(inb[11]));
presum_fa32 psum7_4 (.g1(~gi_l[4]), .g2_fa32(~gi_l[5]), .g3(~gi_l[6]), .g4(~gi_l[7]),
.p0(~pi_l[3]), .p1(~pi_l[4]), .p2(~pi_l[5]), .p3(~pi_l[6]), .p4(~pi_l[7]),
.s1(in[4]), .s2(in[5]), .s3(in[6]), .s4(in[7]),
.s1b(inb[4]), .s2b(inb[5]), .s3b(inb[6]), .s4b(inb[7]));
presum_fa32 psum3_0 (.g1(~gen1_l), .g2_fa32(~gi_l[1]), .g3(~gi_l[2]), .g4(~gi_l[3]),
.p0(1'b1), .p1(~pi_l[0]), .p2(~pi_l[1]), .p3(~pi_l[2]), .p4(~pi_l[3]),
.s1(in[0]), .s2(in[1]), .s3(in[2]), .s4(in[3]),
.s1b(inb[0]), .s2b(inb[1]), .s3b(inb[2]), .s4b(inb[3]));
/* Sum stage */
sum4s_fa32 sum31_28 (.csel(g2_fa327_0), .sin1(in[28]), .sin2(in[29]), .sin3(in[30]), .sin4(in[31]),
.sin1b(inb[28]), .sin2b(inb[29]), .sin3b(inb[30]), .sin4b(inb[31]),
.sum1(sum[28]), .sum2(sum[29]), .sum3(sum[30]), .sum4(sum[31]));
sum4s_fa32 sum27_24 (.csel(g2_fa323_0), .sin1(in[24]), .sin2(in[25]), .sin3(in[26]), .sin4(in[27]),
.sin1b(inb[24]), .sin2b(inb[25]), .sin3b(inb[26]), .sin4b(inb[27]),
.sum1(sum[24]), .sum2(sum[25]), .sum3(sum[26]), .sum4(sum[27]));
sum4s_fa32 sum23_20 (.csel(g19_0), .sin1(in[20]), .sin2(in[21]), .sin3(in[22]), .sin4(in[23]),
.sin1b(inb[20]), .sin2b(inb[21]), .sin3b(inb[22]), .sin4b(inb[23]),
.sum1(sum[20]), .sum2(sum[21]), .sum3(sum[22]), .sum4(sum[23]));
sum4s_fa32 sum19_16 (.csel(w4_15_0), .sin1(in[16]), .sin2(in[17]), .sin3(in[18]), .sin4(in[19]),
.sin1b(inb[16]), .sin2b(inb[17]), .sin3b(inb[18]), .sin4b(inb[19]),
.sum1(sum[16]), .sum2(sum[17]), .sum3(sum[18]), .sum4(sum[19]));
sum4s_fa32 sum15_12 (.csel(w4_11_0), .sin1(in[12]), .sin2(in[13]), .sin3(in[14]), .sin4(in[15]),
.sin1b(inb[12]), .sin2b(inb[13]), .sin3b(inb[14]), .sin4b(inb[15]),
.sum1(sum[12]), .sum2(sum[13]), .sum3(sum[14]), .sum4(sum[15]));
sum4s_fa32 sum11_8 (.csel(w4_7_0), .sin1(in[8]), .sin2(in[9]), .sin3(in[10]), .sin4(in[11]),
.sin1b(inb[8]), .sin2b(inb[9]), .sin3b(inb[10]), .sin4b(inb[11]),
.sum1(sum[8]), .sum2(sum[9]), .sum3(sum[10]), .sum4(sum[11]));
sum4s_fa32 sum7_4 (.csel(w4_3_0), .sin1(in[4]), .sin2(in[5]), .sin3(in[6]), .sin4(in[7]),
.sin1b(inb[4]), .sin2b(inb[5]), .sin3b(inb[6]), .sin4b(inb[7]),
.sum1(sum[4]), .sum2(sum[5]), .sum3(sum[6]), .sum4(sum[7]));
sum4s_fa32 sum3_0 (.csel(cin), .sin1(in[0]), .sin2(in[1]), .sin3(in[2]), .sin4(in[3]),
.sin1b(inb[0]), .sin2b(inb[1]), .sin3b(inb[2]), .sin4b(inb[3]),
.sum1(sum[0]), .sum2(sum[1]), .sum3(sum[2]), .sum4(sum[3]));
assign cout = (~pi_l[31]) & g31_0;
endmodule
/* pgnx_fa32 */
![[Up: fa32 pg_31]](v2html-up.gif)
module pgnx_fa32
(gen_l, pro_l, ain, bin);
output gen_l;
output pro_l;
input ain;
input bin;
assign gen_l = ~ (ain & bin);
assign pro_l = ~ (ain | bin);
endmodule
/* pgnl_fa32 */
module pgnl_fa32 (gen_l, pro_l, ain, bin, carryin);
output gen_l;
output pro_l;
input ain;
input bin;
input carryin;
assign gen_l = ~ ((ain & bin) | (carryin & (ain | bin)));
assign pro_l = ~ (ain | bin);
endmodule
/* pg2_fa32 stage */
module pg2_fa32 (g_u_d, p_u_d, g_l_in, p_l_in);
output g_u_d; // carry_generated.
output p_u_d; // carry_propgated. lower 1-bit
input [1:0] g_l_in; // generate inputs.
input [1:0] p_l_in; // propgate inputs. lower 1-bit
/* Ling modification used here */
assign g_u_d = ~ (g_l_in[1] & g_l_in[0]); // 2-bit pseudo generate.
assign p_u_d = ~ (p_l_in[1] | p_l_in[0]); // 2-bit pseudo propagate.
endmodule
/* g2_fa32 stage */
module g2_fa32 (g_u_d, g_l_in);
output g_u_d; // carry_generated.
input [1:0] g_l_in; // generate inputs.
/* Ling modification used here */
assign g_u_d = ~ (g_l_in[1] & g_l_in[0]); // 2-bit pseudo generate.
endmodule
/* B1AOI stage */
module b1aoi_fa32 (ggrp_l, pgrp_l, gu_in, pu_in, gd_in, pd_in);
output ggrp_l; // group generate.
output pgrp_l; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conventional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
assign pgrp_l = ~ (pu_in & pd_in); // group propagate. lower 1-bit
endmodule
/* G1AOI stage */
module g1aoi_fa32 (ggrp_l, gu_in, pu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
endmodule
/* B3AOI stage */
module b3aoi_fa32 (ggrp_l, pgrp_l, gu_in, pu_in, gd_in, pd_in);
output ggrp_l; // group generate.
output pgrp_l; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
assign pgrp_l = ~ (pu_in & pd_in); // group propagate. lower 1-bit
endmodule
/* G3AOI stage */
module g3aoi_fa32 (ggrp_l, gu_in, pu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | (pu_in & gd_in)); // group generate.
endmodule
/* B2OAI stage */
module b2oai_fa32 (ggrp, pgrp, gu_in, pu_in, gd_in, pd_in);
output ggrp; // group generate.
output pgrp; // group propgate. lower 1-bit
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
input pd_in; // lower propgate input. lower 1-bit
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
assign pgrp = ~ (pu_in | pd_in); // group propagate. lower 1-bit
endmodule
/* G2OAI stage */
module g2oai_fa32 (ggrp, gu_in, pu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
endmodule
/* G4OAI stage */
module g4oai_fa32 (ggrp, gu_in, pu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input pu_in; // upper propgate input. lower 1-bit
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & (pu_in | gd_in)); // group generate.
endmodule
/* Sum stage logic. Carry-select approach is used */
module sum4s_fa32 (csel, sin1, sin2, sin3, sin4, sin1b, sin2b, sin3b, sin4b, sum1, sum2, sum3, sum4);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inputs assuming csel=0
input csel; // global carry input.
/* carry-select approach used here */
assign sum1 = csel == 1 ? sin1 : sin1b;
assign sum2 = csel == 1 ? sin2 : sin2b;
assign sum3 = csel == 1 ? sin3 : sin3b;
assign sum4 = csel == 1 ? sin4 : sin4b;
endmodule
module presum_fa32 (g1, g2_fa32, g3, g4, p0, p1, p2, p3, p4, s1, s2, s3, s4, s1b, s2b, s3b, s4b);
input g1, g2_fa32, g3, g4, p0, p1, p2, p3, p4;
output s1, s2, s3, s4;
output s1b, s2b, s3b, s4b;
assign s1 = (p1 & (~g1)) ^ p0;
assign s2 = (p2 & (~g2_fa32)) ^ (g1 | (p1 & p0));
assign s3 = (p3 & (~g3)) ^ (g2_fa32 | ((g1 | (p1 & p0)) & p2));
assign s4 = (p4 & (~g4)) ^ (g3 | ((g2_fa32 | ((g1 | (p1 & p0)) & p2)) & p3));
assign s1b = p1 & (~g1);
assign s2b = (p2 & (~g2_fa32)) ^ g1;
assign s3b = (p3 & (~g3)) ^ (g2_fa32 | (g1 & p2));
assign s4b = (p4 & (~g4)) ^ (g3 | (g2_fa32 | (g1 & p2)) & p3);
endmodule
// -------------------7) 32-bit bit_wise comparator -----------------------
// ------------- first level 8 4:1 muxs, second level 1 8:1 mux ---------
module cmp3s_32_leg (ai, bi, a_ltn_b, a_eql_b, a_gtn_b);
input [31:0] ai;
input [31:0] bi;
output a_ltn_b; // ai less than bi.
output a_eql_b; // ai equal to bi.
output a_gtn_b; // ai great than bi.
/* Logic
assign a_ltn_b = ( ai[31:0] < bi[31:0] ) ;
assign a_eql_b = ( ai[31:0] == bi[31:0] ) ;
assign a_gtn_b = ( ai[31:0] > bi[31:0] ) ;
*/
wire [31:0] bit_eql_not; // bit-wise equal_not output
reg [2:0] np7; // 7th's nip_equal_great_less output
reg [2:0] np6; // 6th
reg [2:0] np5; // 5th
reg [2:0] np4; // 5th
reg [2:0] np3, np2, np1, np0; // 3~0th
reg [2:0] np_hi, np_lo; // second level.
assign bit_eql_not = ai ^ bi ;
always @ (bit_eql_not or ai or bi)
begin
casex (bit_eql_not[31:28]) // synopsys full_case parallel_case
4'b1xxx: np7 = {1'b0, ai[31], bi[31]} ;
4'b01xx: np7 = {1'b0, ai[30], bi[30]} ;
4'b001x: np7 = {1'b0, ai[29], bi[29]} ;
4'b0001: np7 = {1'b0, ai[28], bi[28]} ;
4'b0000: np7 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np7 = 3'bxxx ;
endcase
casex (bit_eql_not[27:24]) // synopsys full_case parallel_case
4'b1xxx: np6 = {1'b0, ai[27], bi[27]} ;
4'b01xx: np6 = {1'b0, ai[26], bi[26]} ;
4'b001x: np6 = {1'b0, ai[25], bi[25]} ;
4'b0001: np6 = {1'b0, ai[24], bi[24]} ;
4'b0000: np6 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np6 = 3'bxxx ;
endcase
casex (bit_eql_not[23:20]) // synopsys full_case parallel_case
4'b1xxx: np5 = {1'b0, ai[23], bi[23]} ;
4'b01xx: np5 = {1'b0, ai[22], bi[22]} ;
4'b001x: np5 = {1'b0, ai[21], bi[21]} ;
4'b0001: np5 = {1'b0, ai[20], bi[20]} ;
4'b0000: np5 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np5 = 3'bxxx ;
endcase
casex (bit_eql_not[19:16]) // synopsys full_case parallel_case
4'b1xxx: np4 = {1'b0, ai[19], bi[19]} ;
4'b01xx: np4 = {1'b0, ai[18], bi[18]} ;
4'b001x: np4 = {1'b0, ai[17], bi[17]} ;
4'b0001: np4 = {1'b0, ai[16], bi[16]} ;
4'b0000: np4 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np4 = 3'bxxx ;
endcase
casex (bit_eql_not[15:12]) // synopsys full_case parallel_case
4'b1xxx: np3 = {1'b0, ai[15], bi[15]} ;
4'b01xx: np3 = {1'b0, ai[14], bi[14]} ;
4'b001x: np3 = {1'b0, ai[13], bi[13]} ;
4'b0001: np3 = {1'b0, ai[12], bi[12]} ;
4'b0000: np3 = {1'b1,1'b0,1'b0} ; // 4_equal, next
default: np3 = 3'bxxx ;
endcase
casex (bit_eql_not[11:8]) // synopsys full_case parallel_case
4'b1xxx: np2 = {1'b0, ai[11], bi[11]} ;
4'b01xx: np2 = {1'b0, ai[10], bi[10]} ;
4'b001x: np2 = {1'b0, ai[9], bi[9]} ;
4'b0001: np2 = {1'b0, ai[8], bi[8]} ;
4'b0000: np2 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np2 = 3'bxxx ;
endcase
casex (bit_eql_not[7:4]) // synopsys full_case parallel_case
4'b1xxx: np1 = {1'b0, ai[7], bi[7]} ;
4'b01xx: np1 = {1'b0, ai[6], bi[6]} ;
4'b001x: np1 = {1'b0, ai[5], bi[5]} ;
4'b0001: np1 = {1'b0, ai[4], bi[4]} ;
4'b0000: np1 = {1'b1, 1'b0,1'b0} ; // 4_equal, next
default: np1 = 3'bxxx ;
endcase
casex (bit_eql_not[3:0]) // synopsys full_case parallel_case
4'b1xxx: np0 = {1'b0, ai[3], bi[3]} ;
4'b01xx: np0 = {1'b0, ai[2], bi[2]} ;
4'b001x: np0 = {1'b0, ai[1], bi[1]} ;
4'b0001: np0 = {1'b0, ai[0], bi[0]} ;
4'b0000: np0 = {1'b1,1'b0,1'b0 } ; // 4_equal, next
default: np0 = 3'bxxx ;
endcase
end
always @ ( np7 or np6 or np5 or np4 )
begin
casex ({np7[2],np6[2],np5[2],np4[2]}) // synopsys full_case parallel_case
4'b0xxx: np_hi = {1'b0,np7[1:0]} ;
4'b10xx: np_hi = {1'b0,np6[1:0]} ;
4'b110x: np_hi = {1'b0,np5[1:0]} ;
4'b1110: np_hi = {1'b0,np4[1:0]} ;
4'b1111: np_hi = {1'b1,np4[1:0]} ;
default: np_hi = {1'b1,np4[1:0]} ;
endcase
end
always @ ( np3 or np2 or np1 or np0 )
begin
casex ({np3[2],np2[2],np1[2],np0[2]}) // synopsys full_case parallel_case
4'b0xxx: np_lo = {1'b0,np3[1:0]} ;
4'b10xx: np_lo = {1'b0,np2[1:0]} ;
4'b110x: np_lo = {1'b0,np1[1:0]} ;
4'b1110: np_lo = {1'b0,np0[1:0]} ;
4'b1111: np_lo = {1'b1,np0[1:0]} ;
default: np_lo = {1'b1,np0[1:0]} ;
endcase
end
assign a_eql_b = np_hi[2] & np_lo[2] ;
assign {a_gtn_b, a_ltn_b} = (!np_hi[2]) ? np_hi[1:0] : np_lo[1:0] ;
endmodule
// ------------------- 8)16-bit adder (using sum4 stages)-------------------
module fa16 (a, b, c, sum, cout);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input c; // carry in
output cout; // carry out
// -------------------- carry tree level 1 ----------------------------
// produce the generate for the least significant bit (sch: glsbs)
wire g0_l = !(((a[0] | b[0]) & c) | (a[0] &b[0]));
// produce the propagates and generates for the other bits
wire gen0_l, p0_l, g1_l, p1_l, g2_l, p2_l, g3_l, p3_l, g4_l, p4_l,
g5_l, p5_l, g6_l, p6_l, g7_l, p7_l, g8_l, p8_l, g9_l, p9_l,
g10_l, p10_l, g11_l, p11_l, g12_l, p12_l, g13_l, p13_l, g14_l, p14_l,
g15_l, p15_l;
pgnx_fa16 pgnx0 (a[0], b[0], gen0_l, p0_l); // gen0_l is used only for sum[0] calc.
pgnx_fa16 pgnx1 (a[1], b[1], g1_l, p1_l);
pgnx_fa16 pgnx2 (a[2], b[2], g2_l, p2_l);
pgnx_fa16 pgnx3 (a[3], b[3], g3_l, p3_l);
pgnx_fa16 pgnx4 (a[4], b[4], g4_l, p4_l);
pgnx_fa16 pgnx5 (a[5], b[5], g5_l, p5_l);
pgnx_fa16 pgnx6 (a[6], b[6], g6_l, p6_l);
pgnx_fa16 pgnx7 (a[7], b[7], g7_l, p7_l);
pgnx_fa16 pgnx8 (a[8], b[8], g8_l, p8_l);
pgnx_fa16 pgnx9 (a[9], b[9], g9_l, p9_l);
pgnx_fa16 pgnx10 (a[10], b[10], g10_l, p10_l);
pgnx_fa16 pgnx11 (a[11], b[11], g11_l, p11_l);
pgnx_fa16 pgnx12 (a[12], b[12], g12_l, p12_l);
pgnx_fa16 pgnx13 (a[13], b[13], g13_l, p13_l);
pgnx_fa16 pgnx14 (a[14], b[14], g14_l, p14_l);
pgnx_fa16 pgnx15 (a[15], b[15], g15_l, p15_l);
// -------------------- carry tree level 2 ----------------------------
// produce group propagates/generates for sets of 2 bits (sch: pg2)
// this stage contains the ling modification, which simplifies
// this stage, but the outputs are Pseudo-generates, which
// later need to be recovered by anding.
wire g0to1, g2to3, g4to5, g6to7, g8to9, g10to11, g12to13,g14to15,
p1to2, p3to4, p5to6, p7to8, p9to10, p11to12, p13to14;
pg2lg_fa16 pg2lg ( .gd_l(g0_l),
.gu_l(g1_l),
.g(g0to1)); //assign g0to1 = !(g0_l & g1_l);
pg2l_fa16 p2gl0 ( .gd_l(g2_l),
.gu_l(g3_l),
.pd_l(p1_l),
.pu_l(p2_l),
.g(g2to3), //assign g2to3 = !(g2_l & g3_l);
.p(p1to2)); //assign p1to2 = !(p1_l | p2_l);
pg2l_fa16 p2gl1 ( .gd_l(g4_l),
.gu_l(g5_l),
.pd_l(p3_l),
.pu_l(p4_l),
.g(g4to5), //assign g4to5 = !(g4_l & g5_l);
.p(p3to4)); //assign p3to4 = !(p3_l | p4_l);
pg2l_fa16 p2gl2 ( .gd_l(g6_l),
.gu_l(g7_l),
.pd_l(p5_l),
.pu_l(p6_l),
.g(g6to7), //assign g6to7 = !(g6_l & g7_l);
.p(p5to6)); //assign p5to6 = !(p5_l | p6_l);
pg2l_fa16 p2gl3 ( .gd_l(g8_l),
.gu_l(g9_l),
.pd_l(p7_l),
.pu_l(p8_l),
.g(g8to9), //assign g8to9 = !(g8_l & g9_l);
.p(p7to8)); //assign p7to8 = !(p7_l | p8_l);
pg2l_fa16 p2gl4 ( .gd_l(g10_l),
.gu_l(g11_l),
.pd_l(p9_l),
.pu_l(p10_l),
.g(g10to11), //assign g10to11 = !(g10_l & g11_l);
.p(p9to10)); //assign p9to10 = !(p9_l | p10_l);
pg2l_fa16 p2gl5 ( .gd_l(g12_l),
.gu_l(g13_l),
.pd_l(p11_l),
.pu_l(p12_l),
.g(g12to13), //assign g12to13 = !(g12_l & g13_l);
.p(p11to12)); //assign p11to12 = !(p11_l | p12_l);
pg2l_fa16 p2gl6 ( .gd_l(g14_l),
.gu_l(g15_l),
.pd_l(p13_l),
.pu_l(p14_l),
.g(g14to15), //assign g14to15 = !(g14_l & g15_l);
.p(p13to14)); //assign p13to14 = !(p13_l | p14_l);
// -------------------- carry tree level 3 ----------------------------
// use aoi to make group generates
wire g0to3_l, g4to7_l, g8to11_l, g12to15_l,
p3to6_l, p7to10_l, p11to14_l;
aoig_fa16 aoig0 ( .gd(g0to1),
.gu(g2to3),
.pu(p1to2),
.g_l(g0to3_l)); //assign g0to3_l = !((g0to1 & p1to2) | g2to3);
baoi_fa16 baoi0 ( .gd(g4to5),
.gu(g6to7),
.pd(p3to4),
.pu(p5to6),
.g_l(g4to7_l), //assign g4to7_l = !((g4to5 & p5to6) | g6to7);
.p_l(p3to6_l)); //assign p3to6_l = !(p3to4 & p5to6);
baoi_fa16 baoi1 ( .gd(g8to9),
.gu(g10to11),
.pd(p7to8),
.pu(p9to10),
.g_l(g8to11_l), //assign g8to11_l = !((g8to9 & p9to10) | g10to11);
.p_l(p7to10_l)); //assign p7to10_l = !(p7to8 & p9to10);
baoi_fa16 baoi2 ( .gd(g12to13),
.gu(g14to15),
.pd(p11to12),
.pu(p13to14),
.g_l(g12to15_l), //assign g12to15_l = !((g12to13 & p13to14) | g14to15);
.p_l(p11to14_l)); //assign p11to14_l = !(p11to12 & p13to14);
// -------------------- carry tree level 4 ----------------------------
// use oai's since the inputs are active-low.
wire g0to7, g4to11, g8to15,
p3to10, p7to14;
oaig_fa16 oaig0 ( .gd_l(g0to3_l),
.gu_l(g4to7_l),
.pu_l(p3to6_l),
.g(g0to7)); //assign g0to7 = !((g0to3_l | p3to6_l) & g4to7_l);
boai_fa16 boai0 ( .gd_l(g4to7_l),
.gu_l(g8to11_l),
.pd_l(p3to6_l),
.pu_l(p7to10_l),
.g(g4to11), //assign g4to11 = !((g4to7_l | p7to10_l) & g8to11_l);
.p(p3to10)); //assign p3to10 = !(p3to6_l | p7to10_l);
boai_fa16 boai1 ( .gd_l(g8to11_l),
.gu_l(g12to15_l),
.pd_l(p7to10_l),
.pu_l(p11to14_l),
.g(g8to15), //assign g8to15 = !((g8to11_l | p11to14_l) & g12to15_l);
.p(p7to14)); //assign p7to14 = !(p7to10_l | p11to14_l);
// -------------------- carry tree level 5 ----------------------------
// use aoi's to make group generates
wire g0to11_l, g0to15_l;
aoig_fa16 aoig5_0 ( .gd(~g0to3_l),
.gu(g4to11),
.pu(p3to10),
.g_l(g0to11_l)); //assign g0to11_l = !((~g0to3_l & p3to10) | g4to11);
aoig_fa16 aoig5_1 ( .gd(g0to7),
.gu(g8to15),
.pu(p7to14),
.g_l(g0to15_l)); //assign g0to15_l = !((g0to7 & p7to14) | g8to15);
// -------------------- sum, and cout ----------------------------
assign cout = !g0to15_l & !p15_l; // recover cout by anding p15 with the
// pseudo-generate
wire [15:0] suma, sumb; // local sums before carry select mux
sum4_fa16 sum0to3 (.g1(~gen0_l), .g2(~g1_l), .g3(~g2_l), .g4(~g3_l),
.p0(1'b1), .p1(~p0_l), .p2(~p1_l), .p3(~p2_l), .p4(~p3_l),
.sum1a(suma[0]), .sum2a(suma[1]), .sum3a(suma[2]), .sum4a(suma[3]),
.sum1b(sumb[0]), .sum2b(sumb[1]), .sum3b(sumb[2]), .sum4b(sumb[3]));
sum4_fa16 sum4to7 (.g1(~g4_l), .g2(~g5_l), .g3(~g6_l), .g4(~g7_l),
.p0(~p3_l), .p1(~p4_l), .p2(~p5_l), .p3(~p6_l), .p4(~p7_l),
.sum1a(suma[4]), .sum2a(suma[5]), .sum3a(suma[6]), .sum4a(suma[7]),
.sum1b(sumb[4]), .sum2b(sumb[5]), .sum3b(sumb[6]), .sum4b(sumb[7]));
sum4_fa16 sum8to11 (.g1(~g8_l), .g2(~g9_l), .g3(~g10_l), .g4(~g11_l),
.p0(~p7_l), .p1(~p8_l), .p2(~p9_l), .p3(~p10_l), .p4(~p11_l),
.sum1a(suma[8]), .sum2a(suma[9]), .sum3a(suma[10]), .sum4a(suma[11]),
.sum1b(sumb[8]), .sum2b(sumb[9]), .sum3b(sumb[10]), .sum4b(sumb[11]));
sum4_fa16 sum12to15 (.g1(~g12_l), .g2(~g13_l), .g3(~g14_l), .g4(~g15_l),
.p0(~p11_l), .p1(~p12_l), .p2(~p13_l), .p3(~p14_l), .p4(~p15_l),
.sum1a(suma[12]), .sum2a(suma[13]), .sum3a(suma[14]), .sum4a(suma[15]),
.sum1b(sumb[12]), .sum2b(sumb[13]), .sum3b(sumb[14]), .sum4b(sumb[15]));
/********** mux to select sum using G* signals from carry tree *****/
selsum4_fa16 selsum0to3 ( .sum1a(suma[0]), .sum2a(suma[1]), .sum3a(suma[2]), .sum4a(suma[3]),
.sum1b(sumb[0]), .sum2b(sumb[1]), .sum3b(sumb[2]), .sum4b(sumb[3]),
.sel(c),
.sum1(sum[0]), .sum2(sum[1]), .sum3(sum[2]), .sum4(sum[3]));
selsum4_fa16 selsum4to7 ( .sum1a(suma[4]), .sum2a(suma[5]), .sum3a(suma[6]), .sum4a(suma[7]),
.sum1b(sumb[4]), .sum2b(sumb[5]), .sum3b(sumb[6]), .sum4b(sumb[7]),
.sel(~g0to3_l),
.sum1(sum[4]), .sum2(sum[5]), .sum3(sum[6]), .sum4(sum[7]));
selsum4_fa16 selsum8to11 ( .sum1a(suma[8]), .sum2a(suma[9]), .sum3a(suma[10]), .sum4a(suma[11]),
.sum1b(sumb[8]), .sum2b(sumb[9]), .sum3b(sumb[10]), .sum4b(sumb[11]),
.sel(g0to7),
.sum1(sum[8]), .sum2(sum[9]), .sum3(sum[10]), .sum4(sum[11]));
selsum4_fa16 selsum12to15 ( .sum1a(suma[12]), .sum2a(suma[13]), .sum3a(suma[14]), .sum4a(suma[15]),
.sum1b(sumb[12]), .sum2b(sumb[13]), .sum3b(sumb[14]), .sum4b(sumb[15]),
.sel(~g0to11_l),
.sum1(sum[12]), .sum2(sum[13]), .sum3(sum[14]), .sum4(sum[15]));
endmodule
// -------------------- selsum4 -----------------------
// new module just to make synopsys synthesize with a mux at end
module selsum4_fa16 (sel, sum1, sum2, sum3, sum4,
sum1a, sum2a, sum3a, sum4a,
sum1b, sum2b, sum3b, sum4b);
input sum1a, sum2a, sum3a, sum4a,
sum1b, sum2b, sum3b, sum4b, sel;
output sum1, sum2, sum3, sum4;
wire sum1, sum2, sum3, sum4;
assign sum1 = sel ? sum1a : sum1b;
assign sum2 = sel ? sum2a : sum2b;
assign sum3 = sel ? sum3a : sum3b;
assign sum4 = sel ? sum4a : sum4b;
endmodule
// -------------------- sum ----------------------------
// we need to recover the real gernerates
// after the ling modification used in level 2.
// we also are replacing the a,b with p,g to reduce loading
// of the a,b inputs. (a ^ b = p & !g)
// send out two sets of sums to be selected with mux at last stage
module sum4_fa16 (g1, g2, g3, g4, p0, p1, p2, p3, p4,
sum1a, sum2a, sum3a, sum4a,
sum1b, sum2b, sum3b, sum4b);
output sum1a, sum2a, sum3a, sum4a,
sum1b, sum2b, sum3b, sum4b; // sum outputs.
input g1, g2, g3, g4; // individual generate inputs.
input p0, p1, p2, p3, p4; // individual propagate inputs.
//input G; // global carry input. (pseudo-generate)
wire sum1a, sum2a, sum3a, sum4a,
sum1b, sum2b, sum3b, sum4b;
assign sum1a = (p1 & (~g1)) ^ p0;
assign sum2a = (p2 & (~g2)) ^ (g1 | (p1 & p0));
assign sum3a = (p3 & (~g3)) ^ (g2 | ((g1 | (p1 & p0)) & p2));
assign sum4a = (p4 & (~g4)) ^ (g3 | ((g2 | ((g1 | (p1 & p0)) & p2)) & p3));
assign sum1b = p1 & (~g1);
assign sum2b = (p2 & (~g2)) ^ g1;
assign sum3b = (p3 & (~g3)) ^ (g2 | (g1 & p2));
assign sum4b = (p4 & (~g4)) ^ (g3 | (g2 | (g1 & p2)) & p3);
endmodule
// -------------------- pgnx ----------------------------
module pgnx_fa16 (a, b, g_l, p_l); // level 1 propagate and generate signals
input a, b;
output g_l, p_l;
assign g_l = !(a & b); //nand to make 2bit pseudo generate
assign p_l = !(a | b); //nor to make 2bit pseudo propagate
endmodule
// -------------------- pg2lg ----------------------------
// ling modification stage, generate only
module pg2lg_fa16 (gd_l, gu_l, g);
input gd_l, gu_l;
output g;
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Created: | Wed Mar 24 09:43:34 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/custom_cells_behv.v
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