.sel2(~sel[14]),
.data(~bottom[15:0]),
.out(decodeout_l[239:224]));
finalsel finalsel13( .sel(~sel[13]),
.sel2(~sel[13]),
.data(~bottom[15:0]),
.out(decodeout_l[223:208]));
finalsel finalsel12( .sel(~sel[12]),
.sel2(~sel[12]),
.data(~bottom[15:0]),
.out(decodeout_l[207:192]));
finalsel finalsel11( .sel(~sel[11]),
.sel2(~sel[11]),
.data(~bottom[15:0]),
.out(decodeout_l[191:176]));
finalsel finalsel10( .sel(~sel[10]),
.sel2(~sel[10]),
.data(~bottom[15:0]),
.out(decodeout_l[175:160]));
finalsel finalsel9( .sel(~sel[9]),
.sel2(~sel[9]),
.data(~bottom[15:0]),
.out(decodeout_l[159:144]));
finalsel finalsel8( .sel(~sel[8]),
.sel2(~sel[8]),
.data(~bottom[15:0]),
.out(decodeout_l[143:128]));
finalsel finalsel7( .sel(~sel[7]),
.sel2(~sel[7]),
.data(~bottom[15:0]),
.out(decodeout_l[127:112]));
finalsel finalsel6( .sel(~sel[6]),
.sel2(~sel[6]),
.data(~bottom[15:0]),
.out(decodeout_l[111:96]));
finalsel finalsel5( .sel(~sel[5]),
.sel2(~sel[5]),
.data(~bottom[15:0]),
.out(decodeout_l[95:80]));
finalsel finalsel4( .sel(~sel[4]),
.sel2(~sel[4]),
.data(~bottom[15:0]),
.out(decodeout_l[79:64]));
finalsel finalsel3( .sel(~sel[3]),
.sel2(~sel[3]),
.data(~bottom[15:0]),
.out(decodeout_l[63:48]));
finalsel finalsel2( .sel(~sel[2]),
.sel2(~sel[2]),
.data(~bottom[15:0]),
.out(decodeout_l[47:32]));
finalsel finalsel1( .sel(~sel[1]),
.sel2(~sel[1]),
.data(~bottom[15:0]),
.out(decodeout_l[31:16]));
finalsel finalsel0( .sel(~sel[0]),
.sel2(~sel[0]),
.data(~bottom[15:0]),
.out(decodeout_l[15:0]));
assign decodeout = ~decodeout_l;
endmodule
// ***********end of decoder top module ************
// -------------------- finalsel -----------------------
![[Up: mj_s_dcd8to256 finalsel15]](v2html-up.gif)
module finalsel
(sel, sel2, data, out);
input sel, sel2; // sel2 is provided as a 2nd port
// to "help" synopsys synthesize.
// the load here is large and 2 ports
// "adds" fanout.
input [15:0] data;
output [15:0] out;
assign out[15] = ~(data[15] & sel2);
assign out[14] = ~(data[14] & sel2);
assign out[13] = ~(data[13] & sel2);
assign out[12] = ~(data[12] & sel2);
assign out[11] = ~(data[11] & sel2);
assign out[10] = ~(data[10] & sel2);
assign out[9] = ~(data[9] & sel2);
assign out[8] = ~(data[8] & sel2);
assign out[7] = ~(data[7] & sel);
assign out[6] = ~(data[6] & sel);
assign out[5] = ~(data[5] & sel);
assign out[4] = ~(data[4] & sel);
assign out[3] = ~(data[3] & sel);
assign out[2] = ~(data[2] & sel);
assign out[1] = ~(data[1] & sel);
assign out[0] = ~(data[0] & sel);
endmodule
// ------------------- mj_s_dcd4to16 --------------------------
// note output is actually active-low (decodeout_l)
module mj_s_dcd4to16 (data, data_l, decodeout_l);
input [3:0] data, data_l;
output [15:0] decodeout_l;
wire [3:0] sel, bottom;
//wire [15:0] decodeout_l;
// decode top order bits
decode2to4 decodeupper ( .datain(data[3:2]),
.datain_l(data_l[3:2]),
.dataout(sel[3:0]));
// decode lower order bits
decode2to4 decodelower ( .datain(data[1:0]),
.datain_l(data_l[1:0]),
.dataout(bottom[3:0]));
// now use the top order bits to select the proper lower order bits
finalsel4 finalsel4_3( .sel(~sel[3]),
.data(~bottom[3:0]),
.out(decodeout_l[15:12]));
finalsel4 finalsel4_2( .sel(~sel[2]),
.data(~bottom[3:0]),
.out(decodeout_l[11:8]));
finalsel4 finalsel4_1( .sel(~sel[1]),
.data(~bottom[3:0]),
.out(decodeout_l[7:4]));
finalsel4 finalsel4_0( .sel(~sel[0]),
.data(~bottom[3:0]),
.out(decodeout_l[3:0]));
endmodule
// ***********end of decoder top module ************
// -------------------- decode2to4 -----------------------
module decode2to4 (datain, datain_l, dataout);
input [1:0] datain, datain_l;
output [3:0] dataout;
assign dataout[3] = ~( datain[1] & datain[0]); // 11
assign dataout[2] = ~( datain[1] & datain_l[0]); // 10
assign dataout[1] = ~( datain_l[1] & datain[0]); // 01
assign dataout[0] = ~( datain_l[1] & datain_l[0]); // 00
endmodule
// -------------------- finalsel -----------------------
module finalsel4 (sel, data, out);
input sel;
input [3:0] data;
output [3:0] out;
assign out[3] = ~(data[3] & sel);
assign out[2] = ~(data[2] & sel);
assign out[1] = ~(data[1] & sel);
assign out[0] = ~(data[0] & sel);
endmodule
//-------------------------------------------------------------------------
//
// 22) fram32_8.v 32-bit wide, 8 deep fifo ram
//
//-////////////////////////////////////////////////////////////////////-/
module fram32_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter
f_width=32, //fifo data with
p_width=3, //fifo pointer with
f_depth=8; //fifo data depth
input clk;
input write_n;
input [p_width-1:0] write_ptr;
input [p_width-1:0] read_ptr;
input [f_width-1:0] data_in;
output [f_width-1:0] data_out;
reg [f_width-1:0] data_out;
reg [f_width-1:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
wire [p_width-1:0] write_ptr;
// verilint 69 off
// 69: Case statement without default clause
/*
// synopsys translate_off
//-------------------
initial begin
reg0 = 0;
reg1 = 0;
reg2 = 0;
reg3 = 0;
reg4 = 0;
reg5 = 0;
reg6 = 0;
reg7 = 0;
end
//-------------------
// synopsys translate_on
*/
// Continuous output of Read Ptr location
always @(read_ptr or reg0 or reg1 or reg2 or reg3 or reg4 or reg5 or reg6 or reg7)
case (read_ptr)
3'b000 : data_out = reg0;
3'b001 : data_out = reg1;
3'b010 : data_out = reg2;
3'b011 : data_out = reg3;
3'b100 : data_out = reg4;
3'b101 : data_out = reg5;
3'b110 : data_out = reg6;
3'b111 : data_out = reg7;
endcase
// Update RAM on a write pulse
always @(posedge clk)
if( !write_n)
case (write_ptr)
3'b000 : reg0 <= data_in;
3'b001 : reg1 <= data_in;
3'b010 : reg2 <= data_in;
3'b011 : reg3 <= data_in;
3'b100 : reg4 <= data_in;
3'b101 : reg5 <= data_in;
3'b110 : reg6 <= data_in;
3'b111 : reg7 <= data_in;
endcase
// 69: Case statement without default clause
// verilint 69 on
endmodule
//--23) fram37_8.v 37-bit wide, 8 deep fifo ram --
module fram37_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter
f_width=37, //fifo data with
p_width=3, //fifo pointer with
f_depth=8; //fifo data depth
input clk;
input write_n;
input [p_width-1:0] write_ptr;
input [p_width-1:0] read_ptr;
input [f_width-1:0] data_in;
output [f_width-1:0] data_out;
reg [f_width-1:0] data_out;
reg [f_width-1:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
wire [p_width-1:0] write_ptr;
// verilint 69 off
// 69: Case statement without default clause
/*
// synopsys translate_off
//-------------------
initial begin
reg0 = 0;
reg1 = 0;
reg2 = 0;
reg3 = 0;
reg4 = 0;
reg5 = 0;
reg6 = 0;
reg7 = 0;
end
//-------------------
// synopsys translate_on
*/
// Continuous output of Read Ptr location
always @(read_ptr or reg0 or reg1 or reg2 or reg3 or reg4 or reg5 or reg6 or reg7)
case (read_ptr)
3'b000 : data_out = reg0;
3'b001 : data_out = reg1;
3'b010 : data_out = reg2;
3'b011 : data_out = reg3;
3'b100 : data_out = reg4;
3'b101 : data_out = reg5;
3'b110 : data_out = reg6;
3'b111 : data_out = reg7;
endcase
// Update RAM on a write pulse
always @(posedge clk)
if( !write_n)
case (write_ptr)
3'b000 : reg0 <= data_in;
3'b001 : reg1 <= data_in;
3'b010 : reg2 <= data_in;
3'b011 : reg3 <= data_in;
3'b100 : reg4 <= data_in;
3'b101 : reg5 <= data_in;
3'b110 : reg6 <= data_in;
3'b111 : reg7 <= data_in;
endcase
// 69: Case statement without default clause
// verilint 69 on
endmodule
//--24) fram48_8.v 48-bit wide, 8 deep fifo ram --
module fram48_8 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter
f_width=48, //fifo data with
p_width=3, //fifo pointer with
f_depth=8; //fifo data depth
input clk;
input write_n;
input [p_width-1:0] write_ptr;
input [p_width-1:0] read_ptr;
input [f_width-1:0] data_in;
output [f_width-1:0] data_out;
reg [f_width-1:0] data_out;
reg [f_width-1:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
wire [p_width-1:0] write_ptr;
// verilint 69 off
// 69: Case statement without default clause
/*
// synopsys translate_off
//-------------------
initial begin
reg0 = 0;
reg1 = 0;
reg2 = 0;
reg3 = 0;
reg4 = 0;
reg5 = 0;
reg6 = 0;
reg7 = 0;
end
//-------------------
// synopsys translate_on
*/
// Continuous output of Read Ptr location
always @(read_ptr or reg0 or reg1 or reg2 or reg3 or reg4 or reg5 or reg6 or reg7)
case (read_ptr)
3'b000 : data_out = reg0;
3'b001 : data_out = reg1;
3'b010 : data_out = reg2;
3'b011 : data_out = reg3;
3'b100 : data_out = reg4;
3'b101 : data_out = reg5;
3'b110 : data_out = reg6;
3'b111 : data_out = reg7;
endcase
// Update RAM on a write pulse
always @(posedge clk)
if( !write_n)
case (write_ptr)
3'b000 : reg0 <= data_in;
3'b001 : reg1 <= data_in;
3'b010 : reg2 <= data_in;
3'b011 : reg3 <= data_in;
3'b100 : reg4 <= data_in;
3'b101 : reg5 <= data_in;
3'b110 : reg6 <= data_in;
3'b111 : reg7 <= data_in;
endcase
// 69: Case statement without default clause
// verilint 69 on
endmodule
//------------------------------------------------------------------------
//
// 25) @(#)fram58_4.v 32-bit wide, 8 deep fifo ram
//
//-////////////////////////////////////////////////////////////////////-/
module fram58_4 (
clk,
write_n, // Write enable
write_ptr, // Write Address
read_ptr, // Read Address
data_in, // Write Data
data_out // Read Data
);
parameter
f_width=58, //fifo data with
p_width=2, //fifo pointer with
f_depth=4; //fifo data depth
input clk;
input write_n;
input [p_width-1:0] write_ptr;
input [p_width-1:0] read_ptr;
input [f_width-1:0] data_in;
output [f_width-1:0] data_out;
reg [f_width-1:0] data_out;
reg [f_width-1:0] reg0, reg1, reg2, reg3;
wire [p_width-1:0] write_ptr;
// verilint 69 off
// 69: Case statement without default clause
/*
// synopsys translate_off
//-------------------
initial begin
reg0 = 0;
reg1 = 0;
reg2 = 0;
reg3 = 0;
end
//-------------------
// synopsys translate_on
*/
// Continuous output of Read Ptr location
always @(read_ptr or reg0 or reg1 or reg2 or reg3)
case (read_ptr)
2'b00 : data_out = reg0;
2'b01 : data_out = reg1;
2'b10 : data_out = reg2;
2'b11 : data_out = reg3;
endcase
// Update RAM on a write pulse
always @(posedge clk)
if( !write_n)
case (write_ptr)
2'b00 : reg0 <= data_in;
2'b01 : reg1 <= data_in;
2'b10 : reg2 <= data_in;
2'b11 : reg3 <= data_in;
endcase
// 69: Case statement without default clause
// verilint 69 on
endmodule
// -------------------26) 32-bit decrementer ---------------------------------
// ------------------- Kogge-Stone style -----------------------------------
module dec32 (ai, sum);
input [31:0] ai;
output [31:0] sum;
wire [31:0] gi_l; // bit-wise generate carry output
wire gen1_l;
wire g31_30, g29_28, g27_26, g25_24, g23_22, g21_20, g19_18, g17_16, g15_14,
g13_12, g11_10, g9_8, g7_6, g5_4, g3_2, g1_0;
wire g31_28_l, g27_24_l, g23_20_l, g19_16_l, g15_12_l, g11_8_l, g7_4_l, g3_0_l;
wire g31_24, g27_20, g23_16, g19_12, g15_8, g11_4, g7_0;
wire g31_16_l, g27_12_l, g23_8_l, g19_4_l, g15_0_l, g11_0_l;
wire g31_0, g27_0, g23_0, g19_0;
wire w2_3_0, w3i_7_0, w3i_3_0, w4_15_0, w4_11_0, w4_7_0, w4_3_0;
wire [31:0] in, inb;
wire [31:0] sum;
assign gi_l[31:0] = ~ai[31:0];
assign gen1_l = ~ai[0];
/* g0_dec32 stage */
g0_dec32 pg_31_30 ( .g_u_d(g31_30),
.g_l_in(gi_l[31:30]));
g0_dec32 pg_29_28 ( .g_u_d(g29_28),
.g_l_in(gi_l[29:28]));
g0_dec32 pg_27_26 ( .g_u_d(g27_26),
.g_l_in(gi_l[27:26]));
g0_dec32 pg_25_24 ( .g_u_d(g25_24),
.g_l_in(gi_l[25:24]));
g0_dec32 pg_23_22 ( .g_u_d(g23_22),
.g_l_in(gi_l[23:22]));
g0_dec32 pg_21_20 ( .g_u_d(g21_20),
.g_l_in(gi_l[21:20]));
g0_dec32 pg_19_18 ( .g_u_d(g19_18),
.g_l_in(gi_l[19:18]));
g0_dec32 pg_17_16 ( .g_u_d(g17_16),
.g_l_in(gi_l[17:16]));
g0_dec32 pg_15_14 ( .g_u_d(g15_14),
.g_l_in(gi_l[15:14]));
g0_dec32 pg_13_12 ( .g_u_d(g13_12),
.g_l_in(gi_l[13:12]));
g0_dec32 pg_11_10 ( .g_u_d(g11_10),
.g_l_in(gi_l[11:10]));
g0_dec32 pg_9_8 ( .g_u_d(g9_8),
.g_l_in(gi_l[9:8]));
g0_dec32 pg_7_6 ( .g_u_d(g7_6),
.g_l_in(gi_l[7:6]));
g0_dec32 pg_5_4 ( .g_u_d(g5_4),
.g_l_in(gi_l[5:4]));
g0_dec32 pg_3_2 ( .g_u_d(g3_2),
.g_l_in(gi_l[3:2]));
g0_dec32 g_1_0 ( .g_u_d(g1_0),
.g_l_in(gi_l[1:0]));
/* g1 stage */
g1_dec32 pg_31_28 ( .ggrp_l(g31_28_l),
.gu_in(g31_30),
.gd_in(g29_28));
g1_dec32 pg_27_24 ( .ggrp_l(g27_24_l),
.gu_in(g27_26),
.gd_in(g25_24));
g1_dec32 pg_23_20 ( .ggrp_l(g23_20_l),
.gu_in(g23_22),
.gd_in(g21_20));
g1_dec32 pg_19_16 ( .ggrp_l(g19_16_l),
.gu_in(g19_18),
.gd_in(g17_16));
g1_dec32 pg_15_12 ( .ggrp_l(g15_12_l),
.gu_in(g15_14),
.gd_in(g13_12));
g1_dec32 pg_11_8 ( .ggrp_l(g11_8_l),
.gu_in(g11_10),
.gd_in(g9_8));
g1_dec32 pg_7_4 ( .ggrp_l(g7_4_l),
.gu_in(g7_6),
.gd_in(g5_4));
g1_dec32 g_3_0 ( .ggrp_l(g3_0_l),
.gu_in(g3_2),
.gd_in(g1_0));
/* g2 stage */
g2_dec32 pg_31_24 ( .ggrp(g31_24),
.gu_in(g31_28_l),
.gd_in(g27_24_l));
g2_dec32 pg_27_20 ( .ggrp(g27_20),
.gu_in(g27_24_l),
.gd_in(g23_20_l));
g2_dec32 pg_23_16 ( .ggrp(g23_16),
.gu_in(g23_20_l),
.gd_in(g19_16_l));
g2_dec32 pg_19_12 ( .ggrp(g19_12),
.gu_in(g19_16_l),
.gd_in(g15_12_l));
g2_dec32 pg_15_8 ( .ggrp(g15_8),
.gu_in(g15_12_l),
.gd_in(g11_8_l));
g2_dec32 pg_11_4 ( .ggrp(g11_4),
.gu_in(g11_8_l),
.gd_in(g7_4_l));
g2_dec32 g_7_0 ( .ggrp(g7_0),
.gu_in(g7_4_l),
.gd_in(g3_0_l));
assign w2_3_0 = ~ g3_0_l;
/* g3 stage */
g3_dec32 pg_31_16 ( .ggrp_l(g31_16_l),
.gu_in(g31_24),
.gd_in(g23_16));
g3_dec32 pg_27_12 ( .ggrp_l(g27_12_l),
.gu_in(g27_20),
.gd_in(g19_12));
g3_dec32 pg_23_8 ( .ggrp_l(g23_8_l),
.gu_in(g23_16),
.gd_in(g15_8));
g3_dec32 pg_19_4 ( .ggrp_l(g19_4_l),
.gu_in(g19_12),
.gd_in(g11_4));
g3_dec32 g_15_0 ( .ggrp_l(g15_0_l),
.gu_in(g15_8),
.gd_in(g7_0));
g3_dec32 g_11_0 ( .ggrp_l(g11_0_l),
.gu_in(g11_4),
.gd_in(w2_3_0));
assign w3i_7_0 = ~ g7_0;
assign w3i_3_0 = ~ w2_3_0;
/* g4 stage */
g4_dec32 g_31_0 ( .ggrp(g31_0),
.gu_in(g31_16_l),
.gd_in(g15_0_l));
g4_dec32 g_27_0 ( .ggrp(g27_0),
.gu_in(g27_12_l),
.gd_in(g11_0_l));
g4_dec32 g_23_0 ( .ggrp(g23_0),
.gu_in(g23_8_l),
.gd_in(w3i_7_0));
g4_dec32 g_19_0 ( .ggrp(g19_0),
.gu_in(g19_4_l),
.gd_in(w3i_3_0));
assign w4_15_0 = ~ g15_0_l;
assign w4_11_0 = ~ g11_0_l;
assign w4_7_0 = ~ w3i_7_0;
assign w4_3_0 = ~ w3i_3_0;
/* Local Sum, Carry-select stage */
presum_dec32 psum31_28 (.g1(~gi_l[28]), .g2(~gi_l[29]), .g3(~gi_l[30]), .g4(~gi_l[31]),
.s1(in[28]), .s2(in[29]), .s3(in[30]), .s4(in[31]),
.s1b(inb[28]), .s2b(inb[29]), .s3b(inb[30]), .s4b(inb[31]));
presum_dec32 psum27_24 (.g1(~gi_l[24]), .g2(~gi_l[25]), .g3(~gi_l[26]), .g4(~gi_l[27]),
.s1(in[24]), .s2(in[25]), .s3(in[26]), .s4(in[27]),
.s1b(inb[24]), .s2b(inb[25]), .s3b(inb[26]), .s4b(inb[27]));
presum_dec32 psum23_20 (.g1(~gi_l[20]), .g2(~gi_l[21]), .g3(~gi_l[22]), .g4(~gi_l[23]),
.s1(in[20]), .s2(in[21]), .s3(in[22]), .s4(in[23]),
.s1b(inb[20]), .s2b(inb[21]), .s3b(inb[22]), .s4b(inb[23]));
presum_dec32 psum19_16 (.g1(~gi_l[16]), .g2(~gi_l[17]), .g3(~gi_l[18]), .g4(~gi_l[19]),
.s1(in[16]), .s2(in[17]), .s3(in[18]), .s4(in[19]),
.s1b(inb[16]), .s2b(inb[17]), .s3b(inb[18]), .s4b(inb[19]));
presum_dec32 psum15_12 (.g1(~gi_l[12]), .g2(~gi_l[13]), .g3(~gi_l[14]), .g4(~gi_l[15]),
.s1(in[12]), .s2(in[13]), .s3(in[14]), .s4(in[15]),
.s1b(inb[12]), .s2b(inb[13]), .s3b(inb[14]), .s4b(inb[15]));
presum_dec32 psum11_8 (.g1(~gi_l[8]), .g2(~gi_l[9]), .g3(~gi_l[10]), .g4(~gi_l[11]),
.s1(in[8]), .s2(in[9]), .s3(in[10]), .s4(in[11]),
.s1b(inb[8]), .s2b(inb[9]), .s3b(inb[10]), .s4b(inb[11]));
presum_dec32 psum7_4 (.g1(~gi_l[4]), .g2(~gi_l[5]), .g3(~gi_l[6]), .g4(~gi_l[7]),
.s1(in[4]), .s2(in[5]), .s3(in[6]), .s4(in[7]),
.s1b(inb[4]), .s2b(inb[5]), .s3b(inb[6]), .s4b(inb[7]));
presum_dec32 psum3_0 (.g1(~gen1_l), .g2(~gi_l[1]), .g3(~gi_l[2]), .g4(~gi_l[3]),
.s1(in[0]), .s2(in[1]), .s3(in[2]), .s4(in[3]),
.s1b(inb[0]), .s2b(inb[1]), .s3b(inb[2]), .s4b(inb[3]));
/* Sum stage */
sum4s_dec32 sum31_28 (.csel(g27_0), .sin1(in[28]), .sin2(in[29]), .sin3(in[30]), .sin4(in[31]),
.sin1b(inb[28]), .sin2b(inb[29]), .sin3b(inb[30]), .sin4b(inb[31]),
.sum1(sum[28]), .sum2(sum[29]), .sum3(sum[30]), .sum4(sum[31]));
sum4s_dec32 sum27_24 (.csel(g23_0), .sin1(in[24]), .sin2(in[25]), .sin3(in[26]), .sin4(in[27]),
.sin1b(inb[24]), .sin2b(inb[25]), .sin3b(inb[26]), .sin4b(inb[27]),
.sum1(sum[24]), .sum2(sum[25]), .sum3(sum[26]), .sum4(sum[27]));
sum4s_dec32 sum23_20 (.csel(g19_0), .sin1(in[20]), .sin2(in[21]), .sin3(in[22]), .sin4(in[23]),
.sin1b(inb[20]), .sin2b(inb[21]), .sin3b(inb[22]), .sin4b(inb[23]),
.sum1(sum[20]), .sum2(sum[21]), .sum3(sum[22]), .sum4(sum[23]));
sum4s_dec32 sum19_16 (.csel(w4_15_0), .sin1(in[16]), .sin2(in[17]), .sin3(in[18]), .sin4(in[19]),
.sin1b(inb[16]), .sin2b(inb[17]), .sin3b(inb[18]), .sin4b(inb[19]),
.sum1(sum[16]), .sum2(sum[17]), .sum3(sum[18]), .sum4(sum[19]));
sum4s_dec32 sum15_12 (.csel(w4_11_0), .sin1(in[12]), .sin2(in[13]), .sin3(in[14]), .sin4(in[15]),
.sin1b(inb[12]), .sin2b(inb[13]), .sin3b(inb[14]), .sin4b(inb[15]),
.sum1(sum[12]), .sum2(sum[13]), .sum3(sum[14]), .sum4(sum[15]));
sum4s_dec32 sum11_8 (.csel(w4_7_0), .sin1(in[8]), .sin2(in[9]), .sin3(in[10]), .sin4(in[11]),
.sin1b(inb[8]), .sin2b(inb[9]), .sin3b(inb[10]), .sin4b(inb[11]),
.sum1(sum[8]), .sum2(sum[9]), .sum3(sum[10]), .sum4(sum[11]));
sum4s_dec32 sum7_4 (.csel(w4_3_0), .sin1(in[4]), .sin2(in[5]), .sin3(in[6]), .sin4(in[7]),
.sin1b(inb[4]), .sin2b(inb[5]), .sin3b(inb[6]), .sin4b(inb[7]),
.sum1(sum[4]), .sum2(sum[5]), .sum3(sum[6]), .sum4(sum[7]));
sum4s_dec32 sum3_0 (.csel(1'b0), .sin1(in[0]), .sin2(in[1]), .sin3(in[2]), .sin4(in[3]),
.sin1b(inb[0]), .sin2b(inb[1]), .sin3b(inb[2]), .sin4b(inb[3]),
.sum1(sum[0]), .sum2(sum[1]), .sum3(sum[2]), .sum4(sum[3]));
endmodule
/* g0_dec32 stage */
module g0_dec32 (g_u_d, g_l_in);
output g_u_d; // carry_generated.
input [1:0] g_l_in; // generate inputs.
/* Ling modification used here */
assign g_u_d = ~ (g_l_in[1] & g_l_in[0]); // 2-bit pseudo generate.
endmodule
/* G1AOI stage */
module g1_dec32 (ggrp_l, gu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | gd_in); // group generate.
endmodule
/* G3AOI stage */
module g3_dec32 (ggrp_l, gu_in, gd_in);
output ggrp_l; // group generate.
input gu_in; // upper generate input.
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp_l = ~ (gu_in | gd_in); // group generate.
endmodule
/* G2OAI stage */
module g2_dec32 (ggrp, gu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & gd_in); // group generate.
endmodule
/* G4OAI stage */
module g4_dec32 (ggrp, gu_in, gd_in);
output ggrp; // group generate.
input gu_in; // upper generate input.
input gd_in; // lower generate input.
/* conevntional approach used here */
assign ggrp = ~ (gu_in & gd_in); // group generate.
endmodule
/* Sum stage logic. Carry-select approach is used */
module sum4s_dec32 (csel, sin1, sin2, sin3, sin4, sin1b, sin2b, sin3b, sin4b, sum1, sum2, sum3, sum4);
output sum1, sum2, sum3, sum4; // sum outputs.
input sin1, sin2, sin3, sin4; // sel inputs assuming csel=1
input sin1b, sin2b, sin3b, sin4b; // sel_l inputs assuming csel=0
input csel; // global carry input.
/* carry-select approach used here */
assign sum1 = csel == 1 ? sin1 : sin1b;
assign sum2 = csel == 1 ? sin2 : sin2b;
assign sum3 = csel == 1 ? sin3 : sin3b;
assign sum4 = csel == 1 ? sin4 : sin4b;
endmodule
module presum_dec32 (g1, g2, g3, g4, s1, s2, s3, s4, s1b, s2b, s3b, s4b);
input g1, g2, g3, g4;
output s1, s2, s3, s4;
output s1b, s2b, s3b, s4b;
assign s1 = g1;
assign s2 = g2;
assign s3 = g3;
assign s4 = g4;
assign s1b = (~g1);
assign s2b = (~g2) ^ g1;
assign s3b = (~g3) ^ (g2 | g1);
assign s4b = (~g4) ^ (g3 | g2 | g1);
endmodule
// ------------------- 27 ) 10-bit incrementer --------------------------
module inc10 (data, sum);
input [9:0] data;
output [9:0] sum;
// use Kogge-Stone to design the logic
// -------------------- and tree level 1 ----------------------------
wire p0to2_l, p3to5_l;
lev1and lev1a (data[0], data[1], data[2], p0to2_l);
lev1and lev1b (data[3], data[4], data[5], p3to5_l);
// -------------------- and tree level 2 ----------------------------
wire p0to5;
lev2and lev2a (p0to2_l, p3to5_l, p0to5);
// -------------------- local propagates ---------------------------
wire [9:0] outa;
local3_inc10 local0to2 ( .in1(data[0]),
.in2(data[1]),
.in3(data[2]),
.out1a(outa[0]),
.out2a(outa[1]),
.out3a(outa[2]));
local3_inc10 local3to5 ( .in1(data[3]),
.in2(data[4]),
.in3(data[5]),
.out1a(outa[3]),
.out2a(outa[4]),
.out3a(outa[5]));
local4_inc10 local6to9 (.in1(data[6]),
.in2(data[7]),
.in3(data[8]),
.in4(data[9]),
.out1a(outa[6]),
.out2a(outa[7]),
.out3a(outa[8]),
.out4a(outa[9]));
// -------------------- select output ---------------------------
selout3_inc10 selout0to2 ( .sel_l(1'b0),
.out1(sum[0]), .out2(sum[1]), .out3(sum[2]),
.out1a(outa[0]), .out2a(outa[1]), .out3a(outa[2]),
.out1b(data[0]), .out2b(data[1]), .out3b(data[2]));
selout3_inc10 selout3to5 ( .sel_l(p0to2_l),
.out1(sum[3]), .out2(sum[4]), .out3(sum[5]),
.out1a(outa[3]), .out2a(outa[4]), .out3a(outa[5]),
.out1b(data[3]), .out2b(data[4]), .out3b(data[5]));
selout4_inc10 selout6to9 ( .sel_l(~p0to5),
.out1(sum[6]), .out2(sum[7]), .out3(sum[8]), .out4(sum[9]),
.out1a(outa[6]), .out2a(outa[7]), .out3a(outa[8]), .out4a(outa[9]),
.out1b(data[6]), .out2b(data[7]), .out3b(data[8]), .out4b(data[9]));
endmodule
// ***********end of inccrementer top module ************
// -------------------- lev1and -----------------------
module lev1and (in1, in2, in3, out);
input in1, in2, in3;
output out;
wire out;
assign out = ~(in1 & in2 & in3);
endmodule
// -------------------- lev2and -----------------------
module lev2and (in1, in2, out);
input in1, in2;
output out;
wire out;
assign out = ~(in1 | in2);
endmodule
// -------------------- local3_inc10 -----------------------
module local3_inc10 (in1, in2, in3,
out1a, out2a, out3a);
input in1, in2, in3;
output out1a, out2a, out3a;
| This page: |
Created: | Wed Mar 24 09:43:41 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/custom_cells_behv.v
|