.sel_l(slb[7:0])
                                );
 
mj_p_mux8_32  mj_p_mux8_32_lo ( .mx_out(in14_7),
                                .in7(in14),
                                .in6(in13),
                                .in5(in12),
                                .in4(in11),
                                .in3(in10),
                                .in2(in9),
                                .in1(in8),
                                .in0(in7),
                                .sel(sl[15:8]),
                                .sel_l(slb[15:8])
                                );
 
endmodule


module mx2_32 (inp1, inp0, sel, out);
 
input  [31:0]  inp1;
input  [31:0]  inp0;
input          sel;
output [31:0]  out;
 
wire   [31:0]  out;

  assign out = (sel ? inp1 : inp0);

endmodule


module mx2_33 (inp1, inp0, sel, out);
 
input  [32:0]  inp1;
input  [32:0]  inp0;
input          sel;
output [32:0]  out;
 
wire   [32:0]  out;
 
  assign out = (sel ? inp1 : inp0);

endmodule


module mx2i_32 (inp1, inp0, sel, out_);
 
input  [31:0]  inp1;
input  [31:0]  inp0;
input          sel;
output [31:0]  out_;
 
wire   [31:0]  out_;
 
  assign out_ = ~(sel ? inp1 : inp0);

endmodule


module mx2i_b_32 (inp1, inp0, sel, out_);
 
input  [31:0]  inp1;
input  [31:0]  inp0;
input          sel;
output [31:0]  out_;
 
wire   [31:0]  out_;
 
  assign out_ = ~(sel ? inp1 : inp0);

endmodule


module mx2i_33 (inp1, inp0, sel, out_);
 
input  [32:0]  inp1;
input  [32:0]  inp0;
input          sel;
output [32:0]  out_;
 
wire   [32:0]  out_;
 
  assign out_ = ~(sel ? inp1 : inp0);

endmodule


module mx2i_b_33 (inp1, inp0, sel, out_);
 
input  [32:0]  inp1;
input  [32:0]  inp0;
input          sel;
output [32:0]  out_;
 
wire   [32:0]  out_;
 
  assign out_ = ~(sel ? inp1 : inp0);

endmodule


module mx4_1 (inp, sel, out);
 
input   [3:0]  inp;
input   [1:0]  sel;
output         out;
 
reg            out;
 
  always @(inp or sel)
    case (sel)
      2'b00: out = inp[0];
      2'b01: out = inp[1];
      2'b10: out = inp[2];
      2'b11: out = inp[3];
    endcase

endmodule


module mx16_1 (i15, i14, i13, i12,
               i11, i10, i9,  i8,
               i7,  i6,  i5,  i4,
               i3,  i2,  i1,  i0,
               sel, out);
 
input          i15, i14, i13, i12;
input          i11, i10, i9,  i8;
input          i7,  i6,  i5,  i4;
input          i3,  i2,  i1,  i0;
input   [3:0]  sel;
output         out;
 
wire           o_0, o_1, o_2, o_3;
 
  mx4_1 mx4_1_3 (.inp({i15,i14,i13,i12}), .sel(sel[1:0]), .out(o_3));
  mx4_1 mx4_1_2 (.inp({i11,i10,i9, i8}),  .sel(sel[1:0]), .out(o_2));
  mx4_1 mx4_1_1 (.inp({i7, i6, i5, i4}),  .sel(sel[1:0]), .out(o_1));
  mx4_1 mx4_1_0 (.inp({i3, i2, i1, i0}),  .sel(sel[1:0]), .out(o_0));
 
  mx4_1 mx4_1_4 (.inp({o_3,o_2,o_1,o_0}), .sel(sel[3:2]), .out(out));
 
endmodule


module mx16_2 (i15, i14, i13, i12,
               i11, i10, i9,  i8,
               i7,  i6,  i5,  i4,
               i3,  i2,  i1,  i0,
               sel, out);
 
input   [1:0]  i15, i14, i13, i12;
input   [1:0]  i11, i10, i9,  i8;
input   [1:0]  i7,  i6,  i5,  i4;
input   [1:0]  i3,  i2,  i1,  i0;
input   [3:0]  sel;
output  [1:0]  out;
 
  mx16_1 mx16_1_1 (
                   .i15(i15[1]), .i14(i14[1]), .i13(i13[1]), .i12(i12[1]),
                   .i11(i11[1]), .i10(i10[1]), .i9(i9[1]),   .i8(i8[1]),
                   .i7(i7[1]),   .i6(i6[1]),   .i5(i5[1]),   .i4(i4[1]),
                   .i3(i3[1]),   .i2(i2[1]),   .i1(i1[1]),   .i0(i0[1]),
                   .sel(sel),    .out(out[1]));

  mx16_1 mx16_1_0 (
                   .i15(i15[0]), .i14(i14[0]), .i13(i13[0]), .i12(i12[0]),
                   .i11(i11[0]), .i10(i10[0]), .i9(i9[0]),   .i8(i8[0]),
                   .i7(i7[0]),   .i6(i6[0]),   .i5(i5[0]),   .i4(i4[0]),
                   .i3(i3[0]),   .i2(i2[0]),   .i1(i1[0]),   .i0(i0[0]),
                   .sel(sel),    .out(out[0]));
 
endmodule 


module mx4_32 (inp0, inp1, inp2, inp3, sel, out);
 
input  [31:0]  inp0;
input  [31:0]  inp1;
input  [31:0]  inp2;
input  [31:0]  inp3;
input   [1:0]  sel;
output [31:0]  out;
 
reg    [31:0]  out;
 
  always @(inp0 or inp1 or inp2 or inp3 or sel)
    case (sel)
      2'b00: out = inp0;
      2'b01: out = inp1;
      2'b10: out = inp2;
      2'b11: out = inp3;
    endcase

endmodule


module mx4_33 (inp0, inp1, inp2, inp3, sel, out);
 
input  [32:0]  inp0;
input  [32:0]  inp1;
input  [32:0]  inp2;
input  [32:0]  inp3;
input   [1:0]  sel;
output [32:0]  out;
 
reg    [32:0]  out;
 
  always @(inp0 or inp1 or inp2 or inp3 or sel)
    case (sel)
      2'b00: out = inp0;
      2'b01: out = inp1;
      2'b10: out = inp2;
      2'b11: out = inp3;
    endcase

endmodule


module mj_p_muxpri2(sl,slb);
output[1:0] slb;
input [1:0] sl;

assign slb[1] = ~sl[1];
assign slb[0] = ~(~sl[1] & sl[0]);

endmodule



module mj_p_muxpri3(sl,slb);
output[2:0] slb;
input [2:0] sl;

assign slb[2] = ~sl[2];
assign slb[1] = ~(~sl[2] & sl[1]);
assign slb[0] = ~(~sl[2] & ~sl[1] & sl[0]);

endmodule



module mj_p_muxpri4(sl,slb);
output[3:0] slb;
input [3:0] sl;

assign slb[3] = ~sl[3];
assign slb[2] = ~(~sl[3] & sl[2]);
assign slb[1] = ~(~sl[3] & ~sl[2] & sl[1]);
// assign slb[0] = ~(~sl[3] & ~sl[2] & ~sl[1] & sl[0]);
assign slb[0] = ~(~sl[3] & ~sl[2] & ~sl[1]);

endmodule


module mj_p_muxpri6(sl,slb);
output[5:0] slb;
input [5:0] sl;
wire x00;
wire y00;

assign slb[5] = ~sl[5];
assign slb[4] = ~(~sl[5] & sl[4]);
assign slb[3] = ~(~sl[5] & ~sl[4] & sl[3]);
assign slb[2] = ~(~sl[5] & ~sl[4] & ~sl[3] & sl[2]);
assign x00 = (~sl[5] & ~sl[4] & ~sl[3] & ~sl[2]);
assign slb[1] = ~(x00 & sl[1] );
assign slb[0] = ~(x00 & ~sl[1] & sl[0]);

endmodule


module mj_p_muxpri8(sl,slb);
output[7:0] slb;
input [7:0] sl;
wire x00;
wire y00;

assign slb[7] = ~sl[7];
assign slb[6] = ~(~sl[7] & sl[6]);
assign slb[5] = ~(~sl[7] & ~sl[6] & sl[5]);
assign slb[4] = ~(~sl[7] & ~sl[6] & ~sl[5] & sl[4]);
assign x00 = (~sl[7] & ~sl[6] & ~sl[5]);
assign y00 = (~sl[4] & ~sl[3] & ~sl[2]);
assign slb[3] = ~(x00 & sl[3] & ~sl[4]);
assign slb[2] = ~(x00 & ~sl[3] & sl[2] & ~sl[4]);
assign slb[1] = ~(x00 &  y00 & sl[1]);
assign slb[0] = ~(x00 &  y00 & ~sl[1] & sl[0]);


endmodule





module mj_s_mux4l_d_32 (mx_out, sel, in0, in1,in2,in3);
output [31:0] mx_out;
input [1:0] sel;
input  [31:0] in3;
input  [31:0] in2; 
input  [31:0] in1; 
input  [31:0] in0; 
wire [3:0] sl;
wire [3:0] slb;

mj_p_muxdec4_32 i_mj_p_muxdec4 (   .decb(slb),
                                   .dec(sl),
                                   .sel(sel)
                                   );

mj_p_mux4l_32	mj_p_mux4_32_0 (  .mx_out(mx_out),
    .in3(in3), 
    .in2(in2),	
    .in1(in1),
    .in0(in0),
    .sel(sl) ,.sel_l(slb) );

endmodule


module mj_p_mux4l_32 (mx_out, in3, in2, in1, in0, sel, sel_l);
    output [31:0] mx_out;
    input  [31:0] in3; 
    input  [31:0] in2; 
    input  [31:0] in1; 
    input  [31:0] in0; 
    input  [3:0] sel; input  [3:0] sel_l;

    mj_p_mux4l  mux_0 (.mx_out(mx_out[0]), .in3(in3[0]), .in2(in2[0]), .in1(in1[0]), .in0(in0[0]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_1 (.mx_out(mx_out[1]), .in3(in3[1]), .in2(in2[1]), .in1(in1[1]), .in0(in0[1]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_2 (.mx_out(mx_out[2]), .in3(in3[2]), .in2(in2[2]), .in1(in1[2]), .in0(in0[2]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_3 (.mx_out(mx_out[3]), .in3(in3[3]), .in2(in2[3]), .in1(in1[3]), .in0(in0[3]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_4 (.mx_out(mx_out[4]), .in3(in3[4]), .in2(in2[4]), .in1(in1[4]), .in0(in0[4]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_5 (.mx_out(mx_out[5]), .in3(in3[5]), .in2(in2[5]), .in1(in1[5]), .in0(in0[5]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_6 (.mx_out(mx_out[6]), .in3(in3[6]), .in2(in2[6]), .in1(in1[6]), .in0(in0[6]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_7 (.mx_out(mx_out[7]), .in3(in3[7]), .in2(in2[7]), .in1(in1[7]), .in0(in0[7]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_8 (.mx_out(mx_out[8]), .in3(in3[8]), .in2(in2[8]), .in1(in1[8]), .in0(in0[8]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_9 (.mx_out(mx_out[9]), .in3(in3[9]), .in2(in2[9]), .in1(in1[9]), .in0(in0[9]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_10 (.mx_out(mx_out[10]), .in3(in3[10]), .in2(in2[10]), .in1(in1[10]), .in0(in0[10]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_11 (.mx_out(mx_out[11]), .in3(in3[11]), .in2(in2[11]), .in1(in1[11]), .in0(in0[11]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_12 (.mx_out(mx_out[12]), .in3(in3[12]), .in2(in2[12]), .in1(in1[12]), .in0(in0[12]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_13 (.mx_out(mx_out[13]), .in3(in3[13]), .in2(in2[13]), .in1(in1[13]), .in0(in0[13]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_14 (.mx_out(mx_out[14]), .in3(in3[14]), .in2(in2[14]), .in1(in1[14]), .in0(in0[14]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_15 (.mx_out(mx_out[15]), .in3(in3[15]), .in2(in2[15]), .in1(in1[15]), .in0(in0[15]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_16 (.mx_out(mx_out[16]), .in3(in3[16]), .in2(in2[16]), .in1(in1[16]), .in0(in0[16]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_17 (.mx_out(mx_out[17]), .in3(in3[17]), .in2(in2[17]), .in1(in1[17]), .in0(in0[17]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_18 (.mx_out(mx_out[18]), .in3(in3[18]), .in2(in2[18]), .in1(in1[18]), .in0(in0[18]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_19 (.mx_out(mx_out[19]), .in3(in3[19]), .in2(in2[19]), .in1(in1[19]), .in0(in0[19]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_20 (.mx_out(mx_out[20]), .in3(in3[20]), .in2(in2[20]), .in1(in1[20]), .in0(in0[20]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_21 (.mx_out(mx_out[21]), .in3(in3[21]), .in2(in2[21]), .in1(in1[21]), .in0(in0[21]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_22 (.mx_out(mx_out[22]), .in3(in3[22]), .in2(in2[22]), .in1(in1[22]), .in0(in0[22]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_23 (.mx_out(mx_out[23]), .in3(in3[23]), .in2(in2[23]), .in1(in1[23]), .in0(in0[23]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_24 (.mx_out(mx_out[24]), .in3(in3[24]), .in2(in2[24]), .in1(in1[24]), .in0(in0[24]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_25 (.mx_out(mx_out[25]), .in3(in3[25]), .in2(in2[25]), .in1(in1[25]), .in0(in0[25]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_26 (.mx_out(mx_out[26]), .in3(in3[26]), .in2(in2[26]), .in1(in1[26]), .in0(in0[26]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_27 (.mx_out(mx_out[27]), .in3(in3[27]), .in2(in2[27]), .in1(in1[27]), .in0(in0[27]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_28 (.mx_out(mx_out[28]), .in3(in3[28]), .in2(in2[28]), .in1(in1[28]), .in0(in0[28]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_29 (.mx_out(mx_out[29]), .in3(in3[29]), .in2(in2[29]), .in1(in1[29]), .in0(in0[29]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_30 (.mx_out(mx_out[30]), .in3(in3[30]), .in2(in2[30]), .in1(in1[30]), .in0(in0[30]), .sel(sel), .sel_l(sel_l));
    mj_p_mux4l  mux_31 (.mx_out(mx_out[31]), .in3(in3[31]), .in2(in2[31]), .in1(in1[31]), .in0(in0[31]), .sel(sel), .sel_l(sel_l));

endmodule 


module mj_p_mux4l (
    mx_out, 
    in3,
    in2,
    in1,
    in0,
    sel,
    sel_l ) ;

    output mx_out;
    input in3;
    input in2;
    input in1;
    input in0;
    input [3:0] sel;
    input [3:0] sel_l;


reg mx_out;
always @(sel or in2 or in1 or in0 or in3)
begin
     case (sel)
    4'b1000: mx_out = ~in3;
    4'b0100: mx_out = ~in2;
    4'b0010: mx_out = ~in1;
    4'b0001: mx_out = ~in0;
    default: mx_out = 1'bx;
    endcase
end

endmodule