mj_p_mux4 mux_15 (.mx_out(mx_out[15]), .in3(in3[15]), .in2(in2[15]), .in1(in1[15]), .in0(in0[15]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_16 (.mx_out(mx_out[16]), .in3(in3[16]), .in2(in2[16]), .in1(in1[16]), .in0(in0[16]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_17 (.mx_out(mx_out[17]), .in3(in3[17]), .in2(in2[17]), .in1(in1[17]), .in0(in0[17]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_18 (.mx_out(mx_out[18]), .in3(in3[18]), .in2(in2[18]), .in1(in1[18]), .in0(in0[18]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_19 (.mx_out(mx_out[19]), .in3(in3[19]), .in2(in2[19]), .in1(in1[19]), .in0(in0[19]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_20 (.mx_out(mx_out[20]), .in3(in3[20]), .in2(in2[20]), .in1(in1[20]), .in0(in0[20]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_21 (.mx_out(mx_out[21]), .in3(in3[21]), .in2(in2[21]), .in1(in1[21]), .in0(in0[21]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_22 (.mx_out(mx_out[22]), .in3(in3[22]), .in2(in2[22]), .in1(in1[22]), .in0(in0[22]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_23 (.mx_out(mx_out[23]), .in3(in3[23]), .in2(in2[23]), .in1(in1[23]), .in0(in0[23]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_24 (.mx_out(mx_out[24]), .in3(in3[24]), .in2(in2[24]), .in1(in1[24]), .in0(in0[24]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_25 (.mx_out(mx_out[25]), .in3(in3[25]), .in2(in2[25]), .in1(in1[25]), .in0(in0[25]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_26 (.mx_out(mx_out[26]), .in3(in3[26]), .in2(in2[26]), .in1(in1[26]), .in0(in0[26]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_27 (.mx_out(mx_out[27]), .in3(in3[27]), .in2(in2[27]), .in1(in1[27]), .in0(in0[27]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_28 (.mx_out(mx_out[28]), .in3(in3[28]), .in2(in2[28]), .in1(in1[28]), .in0(in0[28]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_29 (.mx_out(mx_out[29]), .in3(in3[29]), .in2(in2[29]), .in1(in1[29]), .in0(in0[29]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_30 (.mx_out(mx_out[30]), .in3(in3[30]), .in2(in2[30]), .in1(in1[30]), .in0(in0[30]), .sel(sel), .sel_l(sel_l));
mj_p_mux4 mux_31 (.mx_out(mx_out[31]), .in3(in3[31]), .in2(in2[31]), .in1(in1[31]), .in0(in0[31]), .sel(sel), .sel_l(sel_l));
endmodule
![[Up: mj_s_mux6_d_32 mj_p_mux6_32_0]](v2html-up.gif)
module mj_p_mux6_32
(mx_out, in5, in4, in3, in2, in1, in0, sel, sel_l);
output [31:0] mx_out;
input [31:0] in5;
input [31:0] in4;
input [31:0] in3;
input [31:0] in2;
input [31:0] in1;
input [31:0] in0;
input [5:0] sel; input [5:0] sel_l;
mj_p_mux6 mux_0 (.mx_out(mx_out[0]), .in5(in5[0]), .in4(in4[0]), .in3(in3[0]), .in2(in2[0]), .in1(in1[0]), .in0(in0[0]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_1 (.mx_out(mx_out[1]), .in5(in5[1]), .in4(in4[1]), .in3(in3[1]), .in2(in2[1]), .in1(in1[1]), .in0(in0[1]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_2 (.mx_out(mx_out[2]), .in5(in5[2]), .in4(in4[2]), .in3(in3[2]), .in2(in2[2]), .in1(in1[2]), .in0(in0[2]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_3 (.mx_out(mx_out[3]), .in5(in5[3]), .in4(in4[3]), .in3(in3[3]), .in2(in2[3]), .in1(in1[3]), .in0(in0[3]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_4 (.mx_out(mx_out[4]), .in5(in5[4]), .in4(in4[4]), .in3(in3[4]), .in2(in2[4]), .in1(in1[4]), .in0(in0[4]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_5 (.mx_out(mx_out[5]), .in5(in5[5]), .in4(in4[5]), .in3(in3[5]), .in2(in2[5]), .in1(in1[5]), .in0(in0[5]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_6 (.mx_out(mx_out[6]), .in5(in5[6]), .in4(in4[6]), .in3(in3[6]), .in2(in2[6]), .in1(in1[6]), .in0(in0[6]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_7 (.mx_out(mx_out[7]), .in5(in5[7]), .in4(in4[7]), .in3(in3[7]), .in2(in2[7]), .in1(in1[7]), .in0(in0[7]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_8 (.mx_out(mx_out[8]), .in5(in5[8]), .in4(in4[8]), .in3(in3[8]), .in2(in2[8]), .in1(in1[8]), .in0(in0[8]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_9 (.mx_out(mx_out[9]), .in5(in5[9]), .in4(in4[9]), .in3(in3[9]), .in2(in2[9]), .in1(in1[9]), .in0(in0[9]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_10 (.mx_out(mx_out[10]), .in5(in5[10]), .in4(in4[10]), .in3(in3[10]), .in2(in2[10]), .in1(in1[10]), .in0(in0[10]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_11 (.mx_out(mx_out[11]), .in5(in5[11]), .in4(in4[11]), .in3(in3[11]), .in2(in2[11]), .in1(in1[11]), .in0(in0[11]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_12 (.mx_out(mx_out[12]), .in5(in5[12]), .in4(in4[12]), .in3(in3[12]), .in2(in2[12]), .in1(in1[12]), .in0(in0[12]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_13 (.mx_out(mx_out[13]), .in5(in5[13]), .in4(in4[13]), .in3(in3[13]), .in2(in2[13]), .in1(in1[13]), .in0(in0[13]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_14 (.mx_out(mx_out[14]), .in5(in5[14]), .in4(in4[14]), .in3(in3[14]), .in2(in2[14]), .in1(in1[14]), .in0(in0[14]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_15 (.mx_out(mx_out[15]), .in5(in5[15]), .in4(in4[15]), .in3(in3[15]), .in2(in2[15]), .in1(in1[15]), .in0(in0[15]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_16 (.mx_out(mx_out[16]), .in5(in5[16]), .in4(in4[16]), .in3(in3[16]), .in2(in2[16]), .in1(in1[16]), .in0(in0[16]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_17 (.mx_out(mx_out[17]), .in5(in5[17]), .in4(in4[17]), .in3(in3[17]), .in2(in2[17]), .in1(in1[17]), .in0(in0[17]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_18 (.mx_out(mx_out[18]), .in5(in5[18]), .in4(in4[18]), .in3(in3[18]), .in2(in2[18]), .in1(in1[18]), .in0(in0[18]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_19 (.mx_out(mx_out[19]), .in5(in5[19]), .in4(in4[19]), .in3(in3[19]), .in2(in2[19]), .in1(in1[19]), .in0(in0[19]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_20 (.mx_out(mx_out[20]), .in5(in5[20]), .in4(in4[20]), .in3(in3[20]), .in2(in2[20]), .in1(in1[20]), .in0(in0[20]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_21 (.mx_out(mx_out[21]), .in5(in5[21]), .in4(in4[21]), .in3(in3[21]), .in2(in2[21]), .in1(in1[21]), .in0(in0[21]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_22 (.mx_out(mx_out[22]), .in5(in5[22]), .in4(in4[22]), .in3(in3[22]), .in2(in2[22]), .in1(in1[22]), .in0(in0[22]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_23 (.mx_out(mx_out[23]), .in5(in5[23]), .in4(in4[23]), .in3(in3[23]), .in2(in2[23]), .in1(in1[23]), .in0(in0[23]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_24 (.mx_out(mx_out[24]), .in5(in5[24]), .in4(in4[24]), .in3(in3[24]), .in2(in2[24]), .in1(in1[24]), .in0(in0[24]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_25 (.mx_out(mx_out[25]), .in5(in5[25]), .in4(in4[25]), .in3(in3[25]), .in2(in2[25]), .in1(in1[25]), .in0(in0[25]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_26 (.mx_out(mx_out[26]), .in5(in5[26]), .in4(in4[26]), .in3(in3[26]), .in2(in2[26]), .in1(in1[26]), .in0(in0[26]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_27 (.mx_out(mx_out[27]), .in5(in5[27]), .in4(in4[27]), .in3(in3[27]), .in2(in2[27]), .in1(in1[27]), .in0(in0[27]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_28 (.mx_out(mx_out[28]), .in5(in5[28]), .in4(in4[28]), .in3(in3[28]), .in2(in2[28]), .in1(in1[28]), .in0(in0[28]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_29 (.mx_out(mx_out[29]), .in5(in5[29]), .in4(in4[29]), .in3(in3[29]), .in2(in2[29]), .in1(in1[29]), .in0(in0[29]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_30 (.mx_out(mx_out[30]), .in5(in5[30]), .in4(in4[30]), .in3(in3[30]), .in2(in2[30]), .in1(in1[30]), .in0(in0[30]), .sel(sel), .sel_l(sel_l));
mj_p_mux6 mux_31 (.mx_out(mx_out[31]), .in5(in5[31]), .in4(in4[31]), .in3(in3[31]), .in2(in2[31]), .in1(in1[31]), .in0(in0[31]), .sel(sel), .sel_l(sel_l));
endmodule
module mj_p_mux8_32 (mx_out, in7, in6, in5, in4, in3, in2, in1, in0, sel, sel_l);
output [31:0] mx_out;
input [31:0] in7;
input [31:0] in6;
input [31:0] in5;
input [31:0] in4;
input [31:0] in3;
input [31:0] in2;
input [31:0] in1;
input [31:0] in0;
input [7:0] sel; input [7:0] sel_l;
mj_p_mux8 mux_0 (.mx_out(mx_out[0]), .in7(in7[0]), .in6(in6[0]), .in5(in5[0]), .in4(in4[0]), .in3(in3[0]), .in2(in2[0]), .in1(in1[0]), .in0(in0[0]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_1 (.mx_out(mx_out[1]), .in7(in7[1]), .in6(in6[1]), .in5(in5[1]), .in4(in4[1]), .in3(in3[1]), .in2(in2[1]), .in1(in1[1]), .in0(in0[1]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_2 (.mx_out(mx_out[2]), .in7(in7[2]), .in6(in6[2]), .in5(in5[2]), .in4(in4[2]), .in3(in3[2]), .in2(in2[2]), .in1(in1[2]), .in0(in0[2]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_3 (.mx_out(mx_out[3]), .in7(in7[3]), .in6(in6[3]), .in5(in5[3]), .in4(in4[3]), .in3(in3[3]), .in2(in2[3]), .in1(in1[3]), .in0(in0[3]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_4 (.mx_out(mx_out[4]), .in7(in7[4]), .in6(in6[4]), .in5(in5[4]), .in4(in4[4]), .in3(in3[4]), .in2(in2[4]), .in1(in1[4]), .in0(in0[4]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_5 (.mx_out(mx_out[5]), .in7(in7[5]), .in6(in6[5]), .in5(in5[5]), .in4(in4[5]), .in3(in3[5]), .in2(in2[5]), .in1(in1[5]), .in0(in0[5]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_6 (.mx_out(mx_out[6]), .in7(in7[6]), .in6(in6[6]), .in5(in5[6]), .in4(in4[6]), .in3(in3[6]), .in2(in2[6]), .in1(in1[6]), .in0(in0[6]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_7 (.mx_out(mx_out[7]), .in7(in7[7]), .in6(in6[7]), .in5(in5[7]), .in4(in4[7]), .in3(in3[7]), .in2(in2[7]), .in1(in1[7]), .in0(in0[7]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_8 (.mx_out(mx_out[8]), .in7(in7[8]), .in6(in6[8]), .in5(in5[8]), .in4(in4[8]), .in3(in3[8]), .in2(in2[8]), .in1(in1[8]), .in0(in0[8]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_9 (.mx_out(mx_out[9]), .in7(in7[9]), .in6(in6[9]), .in5(in5[9]), .in4(in4[9]), .in3(in3[9]), .in2(in2[9]), .in1(in1[9]), .in0(in0[9]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_10 (.mx_out(mx_out[10]), .in7(in7[10]), .in6(in6[10]), .in5(in5[10]), .in4(in4[10]), .in3(in3[10]), .in2(in2[10]), .in1(in1[10]), .in0(in0[10]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_11 (.mx_out(mx_out[11]), .in7(in7[11]), .in6(in6[11]), .in5(in5[11]), .in4(in4[11]), .in3(in3[11]), .in2(in2[11]), .in1(in1[11]), .in0(in0[11]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_12 (.mx_out(mx_out[12]), .in7(in7[12]), .in6(in6[12]), .in5(in5[12]), .in4(in4[12]), .in3(in3[12]), .in2(in2[12]), .in1(in1[12]), .in0(in0[12]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_13 (.mx_out(mx_out[13]), .in7(in7[13]), .in6(in6[13]), .in5(in5[13]), .in4(in4[13]), .in3(in3[13]), .in2(in2[13]), .in1(in1[13]), .in0(in0[13]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_14 (.mx_out(mx_out[14]), .in7(in7[14]), .in6(in6[14]), .in5(in5[14]), .in4(in4[14]), .in3(in3[14]), .in2(in2[14]), .in1(in1[14]), .in0(in0[14]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_15 (.mx_out(mx_out[15]), .in7(in7[15]), .in6(in6[15]), .in5(in5[15]), .in4(in4[15]), .in3(in3[15]), .in2(in2[15]), .in1(in1[15]), .in0(in0[15]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_16 (.mx_out(mx_out[16]), .in7(in7[16]), .in6(in6[16]), .in5(in5[16]), .in4(in4[16]), .in3(in3[16]), .in2(in2[16]), .in1(in1[16]), .in0(in0[16]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_17 (.mx_out(mx_out[17]), .in7(in7[17]), .in6(in6[17]), .in5(in5[17]), .in4(in4[17]), .in3(in3[17]), .in2(in2[17]), .in1(in1[17]), .in0(in0[17]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_18 (.mx_out(mx_out[18]), .in7(in7[18]), .in6(in6[18]), .in5(in5[18]), .in4(in4[18]), .in3(in3[18]), .in2(in2[18]), .in1(in1[18]), .in0(in0[18]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_19 (.mx_out(mx_out[19]), .in7(in7[19]), .in6(in6[19]), .in5(in5[19]), .in4(in4[19]), .in3(in3[19]), .in2(in2[19]), .in1(in1[19]), .in0(in0[19]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_20 (.mx_out(mx_out[20]), .in7(in7[20]), .in6(in6[20]), .in5(in5[20]), .in4(in4[20]), .in3(in3[20]), .in2(in2[20]), .in1(in1[20]), .in0(in0[20]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_21 (.mx_out(mx_out[21]), .in7(in7[21]), .in6(in6[21]), .in5(in5[21]), .in4(in4[21]), .in3(in3[21]), .in2(in2[21]), .in1(in1[21]), .in0(in0[21]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_22 (.mx_out(mx_out[22]), .in7(in7[22]), .in6(in6[22]), .in5(in5[22]), .in4(in4[22]), .in3(in3[22]), .in2(in2[22]), .in1(in1[22]), .in0(in0[22]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_23 (.mx_out(mx_out[23]), .in7(in7[23]), .in6(in6[23]), .in5(in5[23]), .in4(in4[23]), .in3(in3[23]), .in2(in2[23]), .in1(in1[23]), .in0(in0[23]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_24 (.mx_out(mx_out[24]), .in7(in7[24]), .in6(in6[24]), .in5(in5[24]), .in4(in4[24]), .in3(in3[24]), .in2(in2[24]), .in1(in1[24]), .in0(in0[24]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_25 (.mx_out(mx_out[25]), .in7(in7[25]), .in6(in6[25]), .in5(in5[25]), .in4(in4[25]), .in3(in3[25]), .in2(in2[25]), .in1(in1[25]), .in0(in0[25]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_26 (.mx_out(mx_out[26]), .in7(in7[26]), .in6(in6[26]), .in5(in5[26]), .in4(in4[26]), .in3(in3[26]), .in2(in2[26]), .in1(in1[26]), .in0(in0[26]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_27 (.mx_out(mx_out[27]), .in7(in7[27]), .in6(in6[27]), .in5(in5[27]), .in4(in4[27]), .in3(in3[27]), .in2(in2[27]), .in1(in1[27]), .in0(in0[27]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_28 (.mx_out(mx_out[28]), .in7(in7[28]), .in6(in6[28]), .in5(in5[28]), .in4(in4[28]), .in3(in3[28]), .in2(in2[28]), .in1(in1[28]), .in0(in0[28]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_29 (.mx_out(mx_out[29]), .in7(in7[29]), .in6(in6[29]), .in5(in5[29]), .in4(in4[29]), .in3(in3[29]), .in2(in2[29]), .in1(in1[29]), .in0(in0[29]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_30 (.mx_out(mx_out[30]), .in7(in7[30]), .in6(in6[30]), .in5(in5[30]), .in4(in4[30]), .in3(in3[30]), .in2(in2[30]), .in1(in1[30]), .in0(in0[30]), .sel(sel), .sel_l(sel_l));
mj_p_mux8 mux_31 (.mx_out(mx_out[31]), .in7(in7[31]), .in6(in6[31]), .in5(in5[31]), .in4(in4[31]), .in3(in3[31]), .in2(in2[31]), .in1(in1[31]), .in0(in0[31]), .sel(sel), .sel_l(sel_l));
endmodule
/************* Encoded Muxes *************/
module mj_s_mux2_d (mx_out, sel, in0, in1);
output mx_out;
input sel;
input in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = (mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
assign selb = ~sel;
mj_p_mux2 mj_p_mux2_0 (
.mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel) ,
.sel_l(selb)) ;
endmodule
module mj_s_mux2l_d (mx_out, sel, in0, in1);
output mx_out;
input sel;
input in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = ~(mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
assign selb = ~sel;
mj_p_mux2l mj_p_mux2l_0 (
.mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel) ,
.sel_l(selb)) ;
endmodule
module mj_s_mux3_d (mx_out, sel, in0, in1,in2);
output mx_out;
input [1:0] sel;
input in0 , in1, in2 ;
/*
reg mx_out;
// synopsys infer_mux "mx31"
always @(in2 or in1 or in0 or sel)
begin : mx31
case (sel)
2'b10 : mx_out= in2;
2'b01 : mx_out= in1;
2'b00 : mx_out= in0;
default :begin
mx_out = 1'bx;
$display("Invalid Input");
end
endcase
end
*/
//wire [2:0] select;
reg [2:0] sl;
wire [2:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
2'b00: sl = 3'b001;
2'b01: sl = 3'b010;
2'b10: sl = 3'b100;
default: sl = 3'b100;
endcase
end
assign slb = ~sl;
mj_p_mux3 mj_p_mux3_0 ( .mx_out(mx_out),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl),
.sel_l(slb)
);
endmodule
module mj_s_mux4_d (mx_out, sel, in0, in1,in2,in3);
output mx_out;
input [1:0] sel;
input in0 , in1, in2, in3 ;
/*
reg mx_out;
// synopsys infer_mux "mx41"
always @(in3 or in2 or in1 or in0 or sel)
begin : mx41
case (sel)
2'b11 : mx_out= in3;
2'b10 : mx_out= in2;
2'b01 : mx_out= in1;
2'b00 : mx_out= in0;
default :begin
mx_out = 1'bx;
$display("Invalid Input");
end
endcase
end
*/
//wire [3:0] select;
reg [3:0] sl;
wire [3:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
2'b00: sl = 4'h1;
2'b01: sl = 4'h2;
2'b10: sl = 4'h4;
2'b11: sl = 4'h8;
default: sl = 4'h8;
endcase
end
assign slb = ~sl;
mj_p_mux4 mj_p_mux4_0 ( .mx_out(mx_out),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl),
.sel_l(slb)
);
endmodule
module mj_s_mux6_d (mx_out, sel, in0, in1,in2,in3,in4,in5);
output mx_out;
input [2:0] sel;
input in0 , in1, in2, in3, in4 ,in5;
/*
reg mx_out;
// synopsys infer_mux "mx61"
always @(in5 or in4 or in3 or in2 or in1 or in0 or sel)
begin : mx61
case (sel)
3'b101 : mx_out= in5;
3'b100 : mx_out= in4;
3'b011 : mx_out= in3;
3'b010 : mx_out= in2;
3'b001 : mx_out= in1;
3'b000 : mx_out= in0;
default :begin
mx_out = 1'bx;
$display("Invalid Input");
end
endcase
end
*/
//wire [5:0] select;
reg [5:0] sl;
wire [5:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
3'b000: sl = 6'b000001;
3'b001: sl = 6'b000010;
3'b010: sl = 6'b000100;
3'b011: sl = 6'b001000;
3'b100: sl = 6'b010000;
3'b101: sl = 6'b100000;
default: sl = 6'b100000;
endcase
end
assign slb = ~sl;
mj_p_mux6 mj_p_mux6_0 ( .mx_out(mx_out),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl),
.sel_l(slb)
);
endmodule
module mj_s_mux8_d (mx_out, sel, in0, in1,in2,in3,in4,in5,in6,in7);
output mx_out;
input [2:0] sel;
input in0 , in1, in2, in3, in4 ,in5,in6,in7;
/*
reg mx_out;
// synopsys infer_mux "mx81"
always @(in7 or in6 or in5 or in4 or in3 or in2 or in1 or in0 or sel)
begin : mx81
case (sel)
3'b111 : mx_out= in7;
3'b110 : mx_out= in6;
3'b101 : mx_out= in5;
3'b100 : mx_out= in4;
3'b011 : mx_out= in3;
3'b010 : mx_out= in2;
3'b001 : mx_out= in1;
3'b000 : mx_out= in0;
default :begin
mx_out = 1'bx;
$display("Invalid Input");
end
endcase
end
*/
//wire [7:0] select;
reg [7:0] sl;
wire [7:0] slb;
always @(sel) begin
case (sel) // synopsys full_case parallel_case
3'b000: sl = 8'h1;
3'b001: sl = 8'h2;
3'b010: sl = 8'h4;
3'b011: sl = 8'h8;
3'b100: sl = 8'h10;
3'b101: sl = 8'h20;
3'b110: sl = 8'h40;
3'b111: sl = 8'h80;
default: sl = 8'h80;
endcase
end
assign slb = ~sl;
mj_p_mux8 mj_p_mux8_0 ( .mx_out(mx_out),
.in7(in7),
.in6(in6),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl),
.sel_l(slb)
);
endmodule
module mj_s_mux2_d_2 (mx_out, sel, in0, in1);
output [1:0] mx_out;
input sel;
input [1:0] in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = (mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
wire sel1;
assign selb = ~sel;
assign sel1 = ~selb;
mj_p_mux2_2 mj_p_mux2_2_0 (
.mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel1) ,
.sel_l(selb)) ;
endmodule
module mj_s_mux3_d_2 (mx_out, sel, in0, in1,in2);
output [1:0] mx_out;
input [1:0] sel;
input [1:0] in2;
input [1:0] in1;
input [1:0] in0;
//wire [2:0] select;
reg [2:0] sl;
wire [2:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
2'b00: sl = 3'b001;
2'b01: sl = 3'b010;
2'b10: sl = 3'b100;
default: sl = 3'b100;
endcase
end
assign slb = ~sl;
mj_p_mux3_2 mj_p_mux3_2_0 ( .mx_out(mx_out),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux4_d_2 (mx_out, sel, in0, in1,in2,in3);
output [1:0] mx_out;
input [1:0] sel;
input [1:0] in3;
input [1:0] in2;
input [1:0] in1;
input [1:0] in0;
//wire [3:0] select;
reg [3:0] sl;
wire [3:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
2'b00: sl = 4'h1;
2'b01: sl = 4'h2;
2'b10: sl = 4'h4;
2'b11: sl = 4'h8;
default: sl = 4'h8;
endcase
end
assign slb = ~sl;
mj_p_mux4_2 mj_p_mux4_2_0 ( .mx_out(mx_out),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux6_d_2 (mx_out, sel, in0, in1,in2,in3,in4,in5);
output [1:0] mx_out;
input [2:0] sel;
input [1:0] in5;
input [1:0] in4;
input [1:0] in3;
input [1:0] in2;
input [1:0] in1;
input [1:0] in0;
//wire [5:0] select;
reg [5:0] sl;
wire [5:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
3'b000: sl = 6'b000001;
3'b001: sl = 6'b000010;
3'b010: sl = 6'b000100;
3'b011: sl = 6'b001000;
3'b100: sl = 6'b010000;
3'b101: sl = 6'b100000;
default: sl = 6'b100000;
endcase
end
assign slb = ~sl;
mj_p_mux6_2 mj_p_mux6_2_0 ( .mx_out(mx_out),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux8_d_2 (mx_out, sel, in0, in1,in2,in3,in4,in5,in6,in7);
output [1:0] mx_out;
input [2:0] sel;
input [1:0] in7;
input [1:0] in6;
input [1:0] in5;
input [1:0] in4;
input [1:0] in3;
input [1:0] in2;
input [1:0] in1;
input [1:0] in0;
//wire [7:0] select;
reg [7:0] sl;
wire [7:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
3'b000: sl = 8'h1;
3'b001: sl = 8'h2;
3'b010: sl = 8'h4;
3'b011: sl = 8'h8;
3'b100: sl = 8'h10;
3'b101: sl = 8'h20;
3'b110: sl = 8'h40;
3'b111: sl = 8'h80;
default: sl = 8'h80;
endcase
end
assign slb = ~sl;
mj_p_mux8_2 mj_p_mux8_2_0 ( .mx_out(mx_out),
.in7(in7),
.in6(in6),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux2_d_3 (mx_out, sel, in0, in1);
output [2:0] mx_out;
input sel;
input [2:0] in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = (mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
wire sel1;
assign selb = ~sel;
assign sel1 = ~selb;
mj_p_mux2_3 mj_p_mux2_3_0 ( .mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel1) ,
.sel_l(selb)
) ;
endmodule
module mj_s_mux3_d_3 (mx_out, sel, in0, in1,in2);
output [2:0] mx_out;
input [1:0] sel;
input [2:0] in2;
input [2:0] in1;
input [2:0] in0;
//wire [2:0] select;
reg [2:0] sl;
wire [2:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
2'b00: sl = 3'b001;
2'b01: sl = 3'b010;
2'b10: sl = 3'b100;
default: sl = 3'b100;
endcase
end
assign slb = ~sl;
mj_p_mux3_3 mj_p_mux3_3_0 ( .mx_out(mx_out),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux4_d_3 (mx_out, sel, in0, in1,in2,in3);
output [2:0] mx_out;
input [1:0] sel;
input [2:0] in3;
input [2:0] in2;
input [2:0] in1;
input [2:0] in0;
//wire [3:0] select;
reg [3:0] sl;
wire [3:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
2'b00: sl = 4'h1;
2'b01: sl = 4'h2;
2'b10: sl = 4'h4;
2'b11: sl = 4'h8;
default: sl = 4'h8;
endcase
end
assign slb = ~sl;
mj_p_mux4_3 mj_p_mux4_3_0 ( .mx_out(mx_out),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux6_d_3 (mx_out, sel, in0, in1,in2,in3,in4,in5);
output [2:0] mx_out;
input [2:0] sel;
input [2:0] in5;
input [2:0] in4;
input [2:0] in3;
input [2:0] in2;
input [2:0] in1;
input [2:0] in0;
//wire [5:0] select;
reg [5:0] sl;
wire [5:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
3'b000: sl = 6'b000001;
3'b001: sl = 6'b000010;
3'b010: sl = 6'b000100;
3'b011: sl = 6'b001000;
3'b100: sl = 6'b010000;
3'b101: sl = 6'b100000;
default: sl = 6'b100000;
endcase
end
assign slb = ~sl;
mj_p_mux6_3 mj_p_mux6_3_0 ( .mx_out(mx_out),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux8_d_3 (mx_out, sel, in0, in1,in2,in3,in4,in5,in6,in7);
output [2:0] mx_out;
input [2:0] sel;
input [2:0] in7;
input [2:0] in6;
input [2:0] in5;
input [2:0] in4;
input [2:0] in3;
input [2:0] in2;
input [2:0] in1;
input [2:0] in0;
//wire [7:0] select;
reg [7:0] sl;
wire [7:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
3'b000: sl = 8'h1;
3'b001: sl = 8'h2;
3'b010: sl = 8'h4;
3'b011: sl = 8'h8;
3'b100: sl = 8'h10;
3'b101: sl = 8'h20;
3'b110: sl = 8'h40;
3'b111: sl = 8'h80;
default: sl = 8'h80;
endcase
end
assign slb = ~sl;
mj_p_mux8_3 mj_p_mux8_3_0 ( .mx_out(mx_out),
.in7(in7),
.in6(in6),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,
.sel_l(slb)
);
endmodule
module mj_s_mux2_d_4 (mx_out, sel, in0, in1);
output [3:0] mx_out;
input sel;
input [3:0] in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = (mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
wire sel1;
assign selb = ~sel;
assign sel1 = ~selb;
mj_p_mux2_4 mj_p_mux2_4_0 (
.mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel1) ,
.sel_l(selb)) ;
endmodule
module mj_s_mux3_d_4 (mx_out, sel, in0, in1,in2);
output [3:0] mx_out;
input [1:0] sel;
input [3:0] in2;
input [3:0] in1;
input [3:0] in0;
//wire [2:0] select;
reg [2:0] sl;
wire [2:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
2'b00: sl = 3'b001;
2'b01: sl = 3'b010;
2'b10: sl = 3'b100;
default: sl = 3'b100;
endcase
end
assign slb = ~sl;
mj_p_mux3_4 mj_p_mux3_4_0 ( .mx_out(mx_out),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux4_d_4 (mx_out, sel, in0, in1,in2,in3);
output [3:0] mx_out;
input [1:0] sel;
input [3:0] in3;
input [3:0] in2;
input [3:0] in1;
input [3:0] in0;
//wire [3:0] select;
reg [3:0] sl;
wire [3:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
2'b00: sl = 4'h1;
2'b01: sl = 4'h2;
2'b10: sl = 4'h4;
2'b11: sl = 4'h8;
default: sl = 4'h8;
endcase
end
assign slb = ~sl;
mj_p_mux4_4 mj_p_mux4_4_0 ( .mx_out(mx_out),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux6_d_4 (mx_out, sel, in0, in1,in2,in3,in4,in5);
output [3:0] mx_out;
input [2:0] sel;
input [3:0] in5;
input [3:0] in4;
input [3:0] in3;
input [3:0] in2;
input [3:0] in1;
input [3:0] in0;
//wire [5:0] select;
reg [5:0] sl;
wire [5:0] slb;
always @(sel) begin
case(sel) // synopsys parallel_case
3'b000: sl = 6'b000001;
3'b001: sl = 6'b000010;
3'b010: sl = 6'b000100;
3'b011: sl = 6'b001000;
3'b100: sl = 6'b010000;
3'b101: sl = 6'b100000;
default: sl = 6'b100000;
endcase
end
assign slb = ~sl;
mj_p_mux6_4 mj_p_mux6_4_0 ( .mx_out(mx_out),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux8_d_4 (mx_out, sel, in0, in1,in2,in3,in4,in5,in6,in7);
output [3:0] mx_out;
input [2:0] sel;
input [3:0] in7;
input [3:0] in6;
input [3:0] in5;
input [3:0] in4;
input [3:0] in3;
input [3:0] in2;
input [3:0] in1;
input [3:0] in0;
//wire [7:0] select;
reg [7:0] sl;
wire [7:0] slb;
always @(sel) begin
case(sel) // synopsys full_case parallel_case
3'b000: sl = 8'h1;
3'b001: sl = 8'h2;
3'b010: sl = 8'h4;
3'b011: sl = 8'h8;
3'b100: sl = 8'h10;
3'b101: sl = 8'h20;
3'b110: sl = 8'h40;
3'b111: sl = 8'h80;
default: sl = 8'h80;
endcase
end
assign slb = ~sl;
mj_p_mux8_4 mj_p_mux8_4_0 ( .mx_out(mx_out),
.in7(in7),
.in6(in6),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux2_d_6 (mx_out, sel, in0, in1);
output [5:0] mx_out;
input sel;
input [5:0] in0 , in1 ;
/*
wire sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel = sel;
assign mx_out = (mux_sel & in1 | sel_not & in0) ;
*/
wire selb;
wire sel1;
wire sel1b;
assign selb = ~sel;
assign sel1 = ~selb;
assign sel1b = ~sel1;
mj_p_mux2_6 mj_p_mux2_6_0 (
.mx_out(mx_out),
.in1(in1),
.in0(in0),
.sel(sel1) ,
.sel_l(sel1b)) ;
endmodule
module mj_s_mux3_d_6 (mx_out, sel, in0, in1,in2);
output [5:0] mx_out;
input [1:0] sel;
input [5:0] in2;
input [5:0] in1;
input [5:0] in0;
//wire [2:0] select;
wire [2:0] sl;
wire [2:0] slb;
mj_p_muxdec3_8 i_mj_p_muxdec3 ( .decb(slb),
.dec(sl),
.sel(sel)
);
mj_p_mux3_6 mj_p_mux3_6_0 ( .mx_out(mx_out),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux4_d_6 (mx_out, sel, in0, in1,in2,in3);
output [5:0] mx_out;
input [1:0] sel;
input [5:0] in3;
input [5:0] in2;
input [5:0] in1;
input [5:0] in0;
//wire [3:0] select;
wire [3:0] sl;
wire [3:0] slb;
mj_p_muxdec4_8 i_mj_p_muxdec4 ( .decb(slb),
.dec(sl),
.sel(sel)
);
mj_p_mux4_6 mj_p_mux4_6_0 ( .mx_out(mx_out),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
.sel(sl) ,.sel_l(slb) );
endmodule
module mj_s_mux6_d_6 (mx_out, sel, in0, in1,in2,in3,in4,in5);
output [5:0] mx_out;
input [2:0] sel;
input [5:0] in5;
input [5:0] in4;
input [5:0] in3;
input [5:0] in2;
input [5:0] in1;
input [5:0] in0;
//wire [5:0] select;
wire [5:0] sl;
wire [5:0] slb;
mj_p_muxdec6_8 i_mj_p_muxdec6 ( .decb(slb),
.dec(sl),
.sel(sel)
);
mj_p_mux6_6 mj_p_mux6_6_0 ( .mx_out(mx_out),
.in5(in5),
.in4(in4),
.in3(in3),
.in2(in2),
.in1(in1),
.in0(in0),
| This page: |
Created: | Wed Mar 24 09:44:29 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/rtl/mj_muxes_behv.v
|