/****************************************************************
---------------------------------------------------------------
Copyright 1999 Sun Microsystems, Inc., 901 San Antonio
Road, Palo Alto, CA 94303, U.S.A. All Rights Reserved.
The contents of this file are subject to the current
version of the Sun Community Source License, picoJava-II
Core ("the License"). You may not use this file except
in compliance with the License. You may obtain a copy
of the License by searching for "Sun Community Source
License" on the World Wide Web at http://www.sun.com.
See the License for the rights, obligations, and
limitations governing use of the contents of this file.
Sun, Sun Microsystems, the Sun logo, and all Sun-based
trademarks and logos, Java, picoJava, and all Java-based
trademarks and logos are trademarks or registered trademarks
of Sun Microsystems, Inc. in the United States and other
countries.
----------------------------------------------------------------
******************************************************************/
module ucode_rom
(
nxt_ucode_cnt,
rom_fxx
);
// `include "../../common/ucode.h"
input [8:0] nxt_ucode_cnt; // next_state of_the ucode sequencer
output [(`USED_BITS-1):0] rom_fxx; // actual used rom data_out
// ------------- declarations ---------------------------------------------
// synopsys translate_off
reg [1:0] f00; // field_00: IU_zero_comparator
reg [2:0] f01; // Field_01: Ucode and StacK WT
reg [1:0] f02; // Field_02: Ucode and Stack RD
reg [1:0] f03; // Field_03: Ucode and Data_cache
reg [6:0] f04; // Field_04: Ucode and Architech_reg RD
reg [2:0] f05; // Field_05: Ucode and Architech_reg WT
reg [3:0] f06; // Field_06: Integer Unit ALU a_operand
reg [2:0] f07; // Field_07: Integer Unit ALU b_operand
reg [2:0] f08; // Field_08: Read_port_A of temp_regs
reg [2:0] f09; // Field_09: Read_port_B of temp_regs
reg [2:0] f10; // Field_10: Write_port_A of temp_reg SEL
reg [2:0] f11; // Field_11: Write_port_A of temp_reg WT
reg [1:0] f12; // Field_12: Write_port_B0 of temp_reg SEL
reg [1:0] f13; // Field_13: Write_port_B1 of temp_reg SEL
reg [1:0] f14; // Field_14: Write_port_B0 of temp_reg WT
reg f15; // Field_15: Write_port_B1 of temp_reg WT
reg [1:0] f16; // Field_16: Sel reg2/3/6->dat/stk cache
reg [1:0] f17; // field_17: IU_adder operations
reg [11:0] f18; // field_18: Branching in ucode
reg [3:0] f19; // field_19: Mem_adder a_operand
reg [3:0] f20; // field_20: Mem_adder b_operand
reg [1:0] f21; // field_21: Mem_adder operations
reg f22; // field_22: Sel stack_cache address
reg [1:0] f23; // field_23: Sel alu_adder input port_a
wire [(`USED_BITS-1):0] rom_fxx; // actual used rom data_out
assign rom_fxx = {f00,f01,f02,f03,f04,f05,f06,f07,
f08,f09,f10,f11,f12,f13,f14,f15,
f16,f17,f18,f19,f20,f21,f22,f23};
// ------------- state machine --------------------------------------------
always @(nxt_ucode_cnt
) begin
f00 = `F00_DEFAULT;
f01 = `F01_DEFAULT;
f02 = `F02_DEFAULT;
f03 = `F03_DEFAULT;
f04 = `F04_DEFAULT;
f05 = `F05_DEFAULT;
f06 = `F06_DEFAULT;
f07 = `F07_DEFAULT;
f08 = `F08_DEFAULT;
f09 = `F09_DEFAULT;
f10 = `F10_DEFAULT;
f11 = `F11_DEFAULT;
f12 = `F12_DEFAULT;
f13 = `F13_DEFAULT;
f14 = `F14_DEFAULT;
f15 = `F15_DEFAULT;
f16 = `F16_DEFAULT;
f17 = `F17_DEFAULT;
f18 = `F18_DEFAULT;
f19 = `F19_DEFAULT;
f20 = `F20_DEFAULT;
f21 = `F21_DEFAULT;
f22 = `F22_DEFAULT;
f23 = `F23_DEFAULT;
case (nxt_ucode_cnt) //synopsys parallel_case
`U_IDLE: begin
end
// ####### Ucode Operations ######################################
// ---- 9'd1 ~1/3 of arraylength ------------- Offset 9'd0 ------
// ------- start "arraylength" -----------------------------------
9'd1: begin
f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f01 = `F01_WT_DREG_STK_M8;
f06 = `F06_A_CONST_04;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f22 = `F22_SEL_IALU;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_1CYC_LENG;
end
9'd2: begin
end
9'd3: begin
f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f01 = `F01_WT_DREG_STK_M8;
f18 = `F18_U_LAST;
end
// ======= end of "arraylength" ==================================
// ---- 9'd1 ~3/5 of baload ------------------ Offset 9'd3 ------
// ------- start "baload" ----------------------------------------
9'd4: begin
f19 = `F19_SEL_RS2_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f06 = `F06_A_CONST_01;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
f08 = `F08_RD_RS2_A;
f00 = `F00_RS2_COMP_ZERO;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd5: begin
f18 = `F18_CHK_ARY_NEG;
end
9'd6: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
end
9'd7: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
f18 = `F18_CHK_ARY_NEG;
end
9'd8: begin
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_03;
f21 = `F21_MADD_pApB;
f03 = `F03_ARY_LD;
f01 = `F01_WT_DREG_STK;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF;
end
// ======= end of "baload" =======================================
// ---- 9'd1 ~3/5 of caload ------------------ Offset 9'd8 ------
// ------- start "caload" ----------------------------------------
9'd9: begin
f19 = `F19_SEL_RS2_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f06 = `F06_A_CONST_01;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
f08 = `F08_RD_RS2_A;
f00 = `F00_RS2_COMP_ZERO;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd10: begin
f18 = `F18_CHK_ARY_NEG;
end
9'd11: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
end
9'd12: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG1_A;
f06 = `F06_A_LSH1;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
f18 = `F18_CHK_ARY_NEG;
end
9'd13: begin
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_02;
f21 = `F21_MADD_pApB;
f03 = `F03_ARY_LD;
f01 = `F01_WT_DREG_STK;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF;
end
// ======= end of "caload" =======================================
// ---- 9'd1 ~3/5 of iaload ------------------ Offset 9'd13 -----
// ------- start "iaload" ----------------------------------------
9'd14: begin
f19 = `F19_SEL_RS2_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f06 = `F06_A_CONST_01;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
f08 = `F08_RD_RS2_A;
f00 = `F00_RS2_COMP_ZERO;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd15: begin
f18 = `F18_CHK_ARY_NEG;
end
9'd16: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
end
9'd17: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG1_A;
f06 = `F06_A_LSH2;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
f18 = `F18_CHK_ARY_NEG;
end
9'd18: begin
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f01 = `F01_WT_DREG_STK;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF;
end
// ======= end of "iaload" =======================================
// ---- 9'd1 ~4/6 of laload ------------------ Offset 9'd18 -----
// ------- start "laload" ----------------------------------------
9'd19: begin
f19 = `F19_SEL_RS2_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f06 = `F06_A_CONST_01;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
f08 = `F08_RD_RS2_A;
f00 = `F00_RS2_COMP_ZERO;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd20: begin
f18 = `F18_CHK_ARY_NEG;
end
9'd21: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
end
9'd22: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG1_A;
f06 = `F06_A_LSH3;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
f18 = `F18_CHK_ARY_NEG;
end
9'd23: begin
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f01 = `F01_WT_DREG_STK;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_CHK_ARY_OVF;
end
9'd24: begin
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f22 = `F22_SEL_IALU;
f01 = `F01_WT_DREG_STK;
f18 = `F18_U_LAST;
end
// ======= end of "laload" =======================================
// ---- 9'd1 ~5/7 of bastore ----------------- Offset 9'd24 -----
// ------- start "bastore" ---------------------------------------
9'd25: begin
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_RS2_A;
f11 = `F11_WT_REG2_A;
f12 = `F12_SEL_RS2_B0;
f14 = `F14_WT_REG5_B0;
end
9'd26: begin
f02 = `F02_RD_STK;
f10 = `F10_SEL_RS1_A;
f11 = `F11_WT_REG3_A;
end
9'd27: begin
f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_08;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1_M2;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd28: begin
end
9'd29: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_DCACHE_BM2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f18 = `F18_CHK_ARY_NEG;
end
9'd30: begin
f08 = `F08_RD_REG2_A;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_01;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;
end
9'd31: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R3_CACHE;
f03 = `F03_WT_DCACHE;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF | `F18_CHK_ARY_NEG;
end
// ======= end of "bastore" ======================================
// ---- 9'd1 ~5/7 of castore ----------------- Offset 9'd31 -----
// ------- start "castore" ---------------------------------------
9'd32: begin
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_RS2_A;
f11 = `F11_WT_REG2_A;
f12 = `F12_SEL_RS2_B0;
f14 = `F14_WT_REG5_B0;
end
9'd33: begin
f02 = `F02_RD_STK;
f10 = `F10_SEL_RS1_A;
f11 = `F11_WT_REG3_A;
end
9'd34: begin
f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_08;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1_M2;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd35: begin
end
9'd36: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_DCACHE_BM2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f18 = `F18_CHK_ARY_NEG;
end
9'd37: begin
f08 = `F08_RD_REG2_A;
f06 = `F06_A_LSH1;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_01;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;
end
9'd38: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R3_CACHE;
f03 = `F03_WT_DCACHE;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF | `F18_CHK_ARY_NEG;
end
// ======= end of "castore" ======================================
// ---- 9'd1 ~5/7 of iastore ----------------- Offset 9'd38 -----
// ------- start "iastore" ---------------------------------------
9'd39: begin
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_RS2_A;
f11 = `F11_WT_REG2_A;
f12 = `F12_SEL_RS2_B0;
f14 = `F14_WT_REG5_B0;
end
9'd40: begin
f02 = `F02_RD_STK;
f10 = `F10_SEL_RS1_A;
f11 = `F11_WT_REG3_A;
end
9'd41: begin
f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_08;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1_M2;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd42: begin
end
9'd43: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_DCACHE_BM2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f18 = `F18_CHK_ARY_NEG;
end
9'd44: begin
f08 = `F08_RD_REG2_A;
f06 = `F06_A_LSH2;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_01;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;
end
9'd45: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R3_CACHE;
f03 = `F03_WT_DCACHE;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_U_LAST | `F18_CHK_ARY_OVF | `F18_CHK_ARY_NEG;
end
// ======= end of "iastore" ======================================
// ---- 9'd1 ~6/8 of lastore ----------------- Offset 9'd45 -----
// ------- start "lastore" ---------------------------------------
9'd46: begin
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f12 = `F12_SEL_RS2_B0;
f14 = `F14_WT_REG6_B0;
end
9'd47: begin
f02 = `F02_RD_STK;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_RS1_A;
f11 = `F11_WT_REG3_A;
end
9'd48: begin
f02 = `F02_RD_STK;
f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_08;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1_M2;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;
end
9'd49: begin
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
end
9'd50: begin
f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_DCACHE_BM2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f18 = `F18_CHK_ARY_NEG;
end
9'd51: begin
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_RS1_LH3_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f19 = `F19_SEL_RS1_MA;
f20 = `F20_MB_CONST_01;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG5_B0;
end
9'd52: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R3_CACHE;
f03 = `F03_WT_DCACHE;
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_CHK_ARY_OVF | `F18_CHK_ARY_NEG;
end
9'd53: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R6_CACHE;
f03 = `F03_WT_DCACHE;
f18 = `F18_U_LAST;
end
// ======= end of "lastore" ======================================
// ---- 9'd1 ~ 11 of invoke_static_quick ----- Offset 9'd53 -----
// ------- start "invoke_static_quick" ---------------------------
9'd54: begin
f04 = `F04_RD_CONST_P;
f19 = `F19_SEL_ARCH_MA;
f20 = `F20_RD_I16_LSH2_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
end
9'd55: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_20;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG6_B0;
end
9'd56: begin
f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_DCACHE_A;
f11 = `F11_WT_REG3_A;
end
9'd57: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_03;
f04 = `F04_RD_PC;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
end
9'd58: begin
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_SEL_DCACHE_MB;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f08 = `F08_RD_REG0_A;
f09 = `F09_RD_DCACHE_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pAsB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;
end
9'd59: begin
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_PASS_A_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_OPTOP;
end
| This page: |
Created: | Wed Mar 24 09:43:47 1999 |
| From: |
/import/jet-pj2-sim/rahim/picoJava-II/design/iu/ucode/rtl/ucode_rom.v
|