9'd60: begin 
 
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_DCACHE_A;
f06 = `F06_EXTR_16_RSH0;
f09 = `F09_RD_REG6_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd61: begin

f16 = `F16_SEL_R3_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;

               end

        9'd62: begin 
 
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG0_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd63: begin

f06 = `F06_A_CONST_04; 
f09 = `F09_RD_AREG0_B; 
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB; 
f17 = `F17_IALU_sApB; 
f13 = `F13_SEL_ALU_B1; 
f15 = `F15_WT_AREG0_B1; 
f01 = `F01_WT_CONST_P_STK;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_VARS;

               end

        9'd64: begin

f16 = `F16_SEL_R3_CACHE;
f01 = `F01_WT_R236_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_CONST_P;
f18 = `F18_U_LAST;

               end

// ======= end of "invoke_static_quick" ==========================

// ---- 9'd1 ~ 13 of invoke_nonvirtual_quick - Offset  9'd64 -----

// ------- start "invoke_nonvirtual_quick" -----------------------

        9'd65: begin
 
f04 = `F04_RD_CONST_P;
f19 = `F19_SEL_ARCH_MA;
f20 = `F20_RD_I16_LSH2_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd66: begin

f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_20;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A; 
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG6_B0;

               end

        9'd67: begin

f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_DCACHE_A;
f11 = `F11_WT_REG3_A;

               end

        9'd68: begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_03;
f04 = `F04_RD_PC;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd69: begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f08 = `F08_RD_DCACHE_A;
f06 = `F06_EXTR_16_RSH0;
f09 = `F09_RD_REG6_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;

               end

        9'd70: begin

f02 = `F02_RD_STK;
f19 = `F19_SEL_OPTOP_MA; 
f20 = `F20_SEL_DCACHE_MB;
f21 = `F21_MADD_pAsB;   
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f08 = `F08_RD_REG0_A;
f09 = `F09_RD_DCACHE_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pAsB; 
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;

               end

        9'd71: begin 

f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL;

               end

        9'd72: begin 

f13 = `F13_SEL_PASS_A_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_OPTOP;

               end

        9'd73: begin 
 
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd74: begin

f16 = `F16_SEL_R3_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;

               end

        9'd75: begin 
 
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG0_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd76: begin

f06 = `F06_A_CONST_04; 
f09 = `F09_RD_AREG0_B; 
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB; 
f17 = `F17_IALU_sApB; 
f13 = `F13_SEL_ALU_B1; 
f15 = `F15_WT_AREG0_B1; 
f01 = `F01_WT_CONST_P_STK;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_VARS;

               end

        9'd77: begin

f16 = `F16_SEL_R3_CACHE;
f01 = `F01_WT_R236_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_CONST_P;
f18 = `F18_U_LAST;

               end

// ======= end of "invoke_nonvirtual_quick" ======================

// ---- 9'd1 ~ 15 of invoke_virtual_quick ---- Offset  9'd77 -----

// ------- start "invoke_virtual_quick" --------------------------

        9'd78: begin
 
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_RD_A8_LSH2_MB;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;

               end

        9'd79: begin

f02 = `F02_RD_STK;

               end

        9'd80: begin

f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL;

               end

        9'd81: begin
 
f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_20;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;

               end

        9'd82: begin
 
f19 = `F19_SEL_DCACHE_MA3;
f20 = `F20_RD_I8_LSH2_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd83: begin

f06 = `F06_A_CONST_03;
f04 = `F04_RD_PC;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd84: begin
 
f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_DCACHE_A;
f11 = `F11_WT_REG3_A;

               end

        9'd85: begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;

               end

        9'd86: begin

f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_SEL_DCACHE_MB;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f08 = `F08_RD_REG0_A;
f09 = `F09_RD_DCACHE_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pAsB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;

               end

        9'd87: begin
 
f13 = `F13_SEL_PASS_A_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_OPTOP;
 
               end

        9'd88: begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd89: begin

f16 = `F16_SEL_R3_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;

               end

        9'd90: begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG0_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd91: begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_CONST_P_STK;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_VARS;

               end

        9'd92: begin
 
f16 = `F16_SEL_R3_CACHE;
f01 = `F01_WT_R236_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_CONST_P;
f18 = `F18_U_LAST;
 
               end
 
// ======= end of "invoke_virtual_quick" =========================

// ---- 9'd1 ~ 19 of invoke_virtual_quick_w -- Offset  9'd92 -----

// ------- start "invoke_virtual_quick_w" ------------------------

        9'd93: begin

f04 = `F04_RD_CONST_P;
f19 = `F19_SEL_ARCH_MA;
f20 = `F20_RD_I16_LSH2_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd94: begin

f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_20;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;

               end

        9'd95: begin

f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd96: begin

               end

        9'd97: begin
 
f08 = `F08_RD_DCACHE_A;
f06 = `F06_EXTR_16_RSH0;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;

               end

        9'd98: begin

f02 = `F02_RD_STK;
f08 = `F08_RD_DCACHE_A;
f06 = `F06_EXTR_16_RSH16;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_CONST_00;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd99: begin

f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL;

               end

        9'd100:begin
 
f08 = `F08_RD_REG2_A;
f06 = `F06_A_LSH2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_CONST_00;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd101:begin
 
f19 = `F19_SEL_DCACHE_MA3;
f16 = `F16_SEL_R2_CACHE;
f20 = `F20_SEL_PORTC_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd102:begin

f06 = `F06_A_CONST_03;
f04 = `F04_RD_PC;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd103:begin
 
f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_DCACHE_A;
f11 = `F11_WT_REG3_A;

               end

        9'd104:begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;

               end

        9'd105:begin

f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_SEL_DCACHE_MB;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f08 = `F08_RD_REG0_A;
f09 = `F09_RD_DCACHE_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pAsB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;

               end

        9'd106:begin
 
f13 = `F13_SEL_PASS_A_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_OPTOP;
 
               end

        9'd107:begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd108:begin

f16 = `F16_SEL_R3_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;

               end

        9'd109:begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG0_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd110:begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_CONST_P_STK;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_VARS;

               end

        9'd111:begin
 
f16 = `F16_SEL_R3_CACHE;
f01 = `F01_WT_R236_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_CONST_P;
f18 = `F18_U_LAST;
 
               end
 
// ======= end of "invoke_virual_quick_w" ========================

// ---- 9'd1 ~ 21 of invoke_super_quick ------ Offset  9'd111 ----

// ------- start "invoke_super_quick" ----------------------------

        9'd112:begin

f06 = `F06_A_CONST_16;
f04 = `F04_RD_FRAME;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;

               end

        9'd113:begin
 
f02 = `F02_RD_STK;
f06 = `F06_A_CONST_32;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_CONST_00;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;
 
               end
 
        9'd114:begin
 
f19 = `F19_SEL_RS1_MA;
f16 = `F16_SEL_R2_CACHE;
f20 = `F20_SEL_PORTC_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
 
               end

        9'd115:begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_REG5_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd116:begin

f19 = `F19_SEL_DCACHE_MA;
f16 = `F16_SEL_R2_CACHE;
f20 = `F20_SEL_PORTC_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd117:begin

f06 = `F06_A_CONST_32;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_CONST_00;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd118:begin

f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd119:begin

f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_RD_I16_LSH2_MB;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG2_A;

               end

        9'd120:begin
 
f19 = `F19_SEL_DCACHE_MA2;
f16 = `F16_SEL_R2_CACHE;
f20 = `F20_SEL_PORTC_MB;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;

               end

        9'd121:begin

f19 = `F19_SEL_OPTOP_MA;
f20 = `F20_MB_CONST_20;
f21 = `F21_MADD_pAsB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A; 
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG6_B0;

               end

        9'd122:begin

f19 = `F19_SEL_DCACHE_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_DCACHE_A;
f11 = `F11_WT_REG3_A;

               end

        9'd123:begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_03;
f04 = `F04_RD_PC;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_pApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG2_A;

               end

        9'd124:begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f08 = `F08_RD_DCACHE_A;
f06 = `F06_EXTR_16_RSH0;
f09 = `F09_RD_REG6_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;

               end

        9'd125:begin

f02 = `F02_RD_STK;
f19 = `F19_SEL_OPTOP_MA; 
f20 = `F20_SEL_DCACHE_MB;
f21 = `F21_MADD_pAsB;   
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG0_A;
f08 = `F08_RD_REG0_A;
f09 = `F09_RD_DCACHE_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pAsB; 
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;

               end

        9'd126:begin 

f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL;

               end

        9'd127:begin 

f13 = `F13_SEL_PASS_A_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_OPTOP;

               end

        9'd128:begin 
 
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd129:begin

f16 = `F16_SEL_R3_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_28;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;

               end

        9'd130:begin 
 
f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG0_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd131:begin

f06 = `F06_A_CONST_04; 
f09 = `F09_RD_AREG0_B; 
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB; 
f17 = `F17_IALU_sApB; 
f13 = `F13_SEL_ALU_B1; 
f15 = `F15_WT_AREG0_B1; 
f01 = `F01_WT_CONST_P_STK;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_VARS;

               end

        9'd132:begin

f16 = `F16_SEL_R3_CACHE;
f01 = `F01_WT_R236_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_CONST_P;
f18 = `F18_U_LAST;

               end

// ======= end of "invoke_super_quick" ===========================

// ---- 9'd1 ~  8 of return ------------------ Offset  9'd132 ----

// ------- start "return" ----------------------------------------

        9'd133:begin
 
f06 = `F06_A_CONST_16;
f04 = `F04_RD_FRAME;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_ARCH;
f17 = `F17_IALU_sApB;
f10 = `F10_SEL_ALU_A;
f11 = `F11_WT_REG1_A;
 
               end

        9'd134:begin
 
f04 = `F04_RD_FRAME;
f19 = `F19_SEL_ARCH_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_REG1_A;
f05 = `F05_WT_A_OPTOP;
 
               end
 
        9'd135:begin

f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_08;
f21 = `F21_MADD_pAsB;
f13 = `F13_SEL_MA_B1;
f15 = `F15_WT_AREG0_B1;
f02 = `F02_RD_STK;
 
               end