f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG2_A;

               end

        9'd281:begin 

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f04 = `F04_RD_PSR;
f19 = `F19_SEL_ARCH_MA_54; 
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB; 
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG3_A;
f12 = `F12_SEL_ALU_B0;
f14 = `F14_WT_REG5_B0;
f01 = `F01_WT_PSR_STK;
 
               end

        9'd282:begin 

f06 = `F06_A_CONST_08;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f04 = `F04_RD_TBR;
f19 = `F19_SEL_ARCH_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pAsB;
f03 = `F03_RD_DCACHE;
f08 = `F08_RD_REG3_A;
f05 = `F05_WT_A_PSR;
f16 = `F16_SEL_R2_CACHE;
f01 = `F01_WT_R236_STK;

               end

        9'd283:begin

f06 = `F06_A_CONST_04;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f01 = `F01_WT_FRAME_STK;
f08 = `F08_RD_REG5_A;
f05 = `F05_WT_A_FRAME;

               end

        9'd284:begin 
 
f01 = `F01_WT_VARS_STK;
f08 = `F08_RD_DCACHE_A;
f05 = `F05_WT_A_PC;
f18 = `F18_U_LAST;

               end

// ======= end of "iu_trap_r" ====================================

// ---- 9'd1 ~  8 of "aastore_quick" --------- Offset  9'd284 ----

// ------- start "aastore_quick" ---------------------------------

        9'd285:begin
 
f06 = `F06_A_CONST_00;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_OPTOP;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f10 = `F10_SEL_RS2_A;
f11 = `F11_WT_REG2_A;
f12 = `F12_SEL_RS2_B0;
f14 = `F14_WT_REG5_B0;

               end                                  
 
        9'd286:begin
 
f02 = `F02_RD_STK;
f10 = `F10_SEL_RS1_A;
f11 = `F11_WT_REG3_A;
f12 = `F12_SEL_RS1_B0;
f14 = `F14_WT_REG6_B0;
 
               end
 
        9'd287:begin

f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_04;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_08;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_RS1_M2;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f08 = `F08_RD_RS1_A;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_NULL | `F18_CHK_HANDLE;

               end

        9'd288:begin
               end

        9'd289:begin

f19 = `F19_SEL_DCACHE_MA2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f06 = `F06_A_CONST_04;
f09 = `F09_RD_DCACHE_BM2;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f18 = `F18_CHK_ARY_NEG;
 
               end

        9'd290:begin
 
f08 = `F08_RD_REG2_A;
f06 = `F06_A_LSH2;
f09 = `F09_RD_AREG0_B;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_pApB;
f13 = `F13_SEL_ALU_B1;
f15 = `F15_WT_AREG0_B1;
f16 = `F16_SEL_R2_CACHE;
f19 = `F19_SEL_PORTC_MA;
f20 = `F20_MB_CONST_01;
f21 = `F21_MADD_pApB;
f10 = `F10_SEL_MA_A;
f11 = `F11_WT_REG1_A;
 
               end

        9'd291:begin
 
f08 = `F08_RD_REG1_A;
f09 = `F09_RD_DCACHE_BM8;
f23 = `F23_SEL_IALU_A;
f07 = `F07_B_U_PORTB;
f17 = `F17_IALU_sApB;
f18 = `F18_CHK_ARY_OVF | `F18_CHK_ARY_NEG;
 
               end

        9'd292:begin
 
f19 = `F19_SEL_AREG0_MA;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f16 = `F16_SEL_R3_CACHE;
f03 = `F03_WT_DCACHE;
f08 = `F08_RD_RS1_A;
f09 = `F09_RD_REG6_B;
f04 = `F04_RD_GC_CONF;
f18 = `F18_U_LAST | `F18_CHK_GC;
 
               end

// ======= end of "aastore_quick" ================================

// ---- 9'd1 ~  3 of "monitorenter" ---------- Offset  9'd292 ----
 
// ------- start "monitorenter" -----------------------------------

        9'd293:begin

f19 = `F19_SEL_RS1_MA_M2;
f20 = `F20_MB_CONST_00;
f21 = `F21_MADD_pApB;
f03 = `F03_RD_DCACHE;
f00 = `F00_RS1_COMP_ZERO;
f18 = `F18_CHK_EQ_BRANCH;

               end

        9'd294:begin
               end

        9'd295:begin

f18 = `F18_U_LAST;

               end

// ======= end of "monitorenter" =================================

// ---- 9'd1 ~  8 of "return2" --------------- Offset  9'd295 ----

// ------- start "return2" ---------------------------------------

        9'd296:begin 
                 // next new instruction
               end

// ======= end of "return2" ======================================


// ####### Final Default #########################################
        default: begin
          f00 = `F00_DEFAULT;
          f01 = `F01_DEFAULT;
          f02 = `F02_DEFAULT;
          f03 = `F03_DEFAULT;
          f04 = `F04_DEFAULT;
          f05 = `F05_DEFAULT;
          f06 = `F06_DEFAULT;
          f07 = `F07_DEFAULT;
          f08 = `F08_DEFAULT;
          f09 = `F09_DEFAULT;
          f10 = `F10_DEFAULT;
          f11 = `F11_DEFAULT;
          f12 = `F12_DEFAULT;
          f13 = `F13_DEFAULT;
          f14 = `F14_DEFAULT;
          f15 = `F15_DEFAULT;
          f16 = `F16_DEFAULT;
          f17 = `F17_DEFAULT;
          f18 = `F18_DEFAULT;
          f19 = `F19_DEFAULT;
          f20 = `F20_DEFAULT;
          f21 = `F21_DEFAULT;
          f22 = `F22_DEFAULT;
          f23 = `F23_DEFAULT;

          $display("Warning: at%d, rom_ucode.v, UNknown nxt_ucode_cnt=%d",
                    $time, nxt_ucode_cnt);
                 end
      endcase

  end // end the state machine's always

// synopsys translate_on

endmodule