assign	opcode_sel_rsd[1] = (group_8 | group_9);
assign	opcode_sel_rsd[0] = !(|opcode_sel_rsd[3:1]);

mux8_24		mux_op_4 (.out({opcode_inst4_1,opcode_inst4_2,opcode_inst4_3}),
				.in0(24'b0),
				.in1({ibuff_1,ibuff_2,ibuff_3}),
				.in2({ibuff_2,ibuff_3,ibuff_4}),
				.in3({ibuff_3,ibuff_4,ibuff_5}),
				.in4({ibuff_4,ibuff_5,ibuff_6}),
				.in5({ibuff_5,ibuff_6,8'b0}),
				.in6({ibuff_6,16'b0}),
				.in7({24'b0}),
				.sel(accum_len2) );

mux4_24		mux_op_rsd (.out({opcode_1_rsd,opcode_2_rsd,opcode_3_rsd}),
				.in0({ibuff_0,ibuff_1,ibuff_2}),
				.in1({opcode_inst2_1,opcode_inst2_2,opcode_inst2_3}),
				.in2({opcode_inst3_1,opcode_inst3_2,opcode_inst3_3}),
				.in3({opcode_inst4_1,opcode_inst4_2,opcode_inst4_3}),
				.sel(opcode_sel_rsd) );

ff_se_8		flop_opcode_1_rsd (.out(opcode_1_rsd_r),
					.din(opcode_1_rsd),
					.clk(clk),
					.enable(!hold_r));

ff_se_8		flop_opcode_2_rsd (.out(opcode_2_rsd_r),
					.din(opcode_2_rsd),
					.clk(clk),
					.enable(!hold_r));


// Generate offset_rsd_ctl
// This is used to select appropriate offset_sel_rsd
// Essentially this will tell which Instruction should be used
// to derive offset_sel_rsd. The same signal is used to derive
// the 1 byte offset for rsd stage

assign	offset_rsd_ctl[1] = group_8 | group_9;
assign	offset_rsd_ctl[2] = group_4;
assign	offset_rsd_ctl[3] = group_1;
assign	offset_rsd_ctl[0] = !(|offset_rsd_ctl[3:1]);

// valid for RSd

// Whenever there's a mem op in the fisrt inst or if it is any of the following
// groups, valid for rsd should be high

// Whenever there's a kill_vld_d signal is there, kill all valids
// Also propogate these valids even in presence of hold_r
assign	valid_rsd = (mem_op_rs1 | group_1 | group_4 | group_8 | group_9) & !kill_vld_d;

ff_sre	flop_vld_rsd (.out(valid_rsd_r),
			.din(valid_rsd),
			.reset_l(reset_l),
			.enable(!(hold_r & !kill_vld_d)),
			.clk(clk));

// rsd offset logic

// Select the 2nd byte of the appropriate instruction for
// determining the offset

mux4_8		mux_offset_rsd_int(.out(offset_rsd_int),
				.in0(ibuff_1),
				.in1(opcode_inst2_2),
				.in2(opcode_inst3_2),
				.in3(opcode_inst4_2),
				.sel(offset_rsd_ctl) );

mux5_8		mux_offset_rsd(.out(offset_rsd),
				.in0(8'd0),
				.in1(8'd1),
				.in2(8'd2),
				.in3(8'd3),
				.in4(offset_rsd_int),
				.sel(offset_sel_rsd) );
		
ff_se_8		flop_offset_rsd(.out(offset_rsd_r),
				.din(offset_rsd),
				.enable(!hold_r),
				.clk(clk) );

// Whenever there's a dirty bit in the first instruction, assert drty_inst_r

assign	drty_inst_1 = fetch_drty[0];
assign	drty_inst_2 = |(fetch_drty[1:0]);
assign	drty_inst_3 = |(fetch_drty[2:0]);
assign	drty_inst_4 = |(fetch_drty[3:0]);
assign	drty_inst_5 = |(fetch_drty[4:0]);

mux6	mux_drty_inst(.out(drty_inst),
			.in0(1'b0),
			.in1(drty_inst_1),
			.in2(drty_inst_2),
			.in3(drty_inst_3),
			.in4(drty_inst_4),
			.in5(drty_inst_5),
			.sel(ex_len_first_inst) );

ff_sre	flop_drty_inst(.out(drty_inst_r),
			.din((drty_inst & !kill_vld_d)),
			.clk(clk),
			.enable(!(hold_r & !kill_vld_d)),
			.reset_l(reset_l));
				
// Whenever there's putfield2_quick,we need to provide top3 item 
// from scache for RS2 instead of teh default top2

assign	put_field2_quick = (ibuff_0 == 8'd209) & fetch_valid[0] ;

ff_sre	flop_putfield(.out(put_field2_quick_r),
			.din((put_field2_quick & !kill_vld_d)),
			.clk(clk),
			.enable(!(hold_r & !kill_vld_d)),
			.reset_l(reset_l));
				

mj_spare spare1( .clk(clk),
                .reset_l(reset_l));

mj_spare spare2( .clk(clk),
                .reset_l(reset_l));
 


// Misc. Logic
// COSIM SIGNALS
// synopsys translate_off
// Provide number of instructions folded info.  to cosim
mux5_3		mux_inst_fold(.out(instrs_folded),
			.in0(3'd0),
			.in1(3'd1),
			.in2(3'd2),
			.in3(3'd3),
			.in4(3'd4),
			.sel( {fold_4_inst,fold_3_inst,fold_2_inst,
				fold_1_inst,not_valid}) );

ff_sre_3	flop_inst_fold_r(.out(instrs_folded_r),
				.din((instrs_folded & {3{!kill_vld_d}})),
				.clk(clk),
				.reset_l(reset_l),
				.enable(!(hold_r & !kill_vld_d)));

ff_sre_3	flop_inst_fold_e(.out(instrs_folded_e),
				.din(instrs_folded_r),
				.clk(clk),
				.reset_l(reset_l),
				.enable(!hold_e));

ff_sre_3	flop_inst_fold_c(.out(instrs_folded_c),
				.din(instrs_folded_e),
				.clk(clk),
				.reset_l(reset_l),
				.enable(!hold_c));

ff_sr_3		flop_inst_fold_w(.out(instrs_folded_w),
				.din(instrs_folded_c),
				.clk(clk),
				.reset_l(reset_l));

// synopsys translate_on
endmodule