/*****************************
    *				*
    *		W stage		*
    *				*
    *****************************/

// Because of timing reasons, we have moved the mux selects for 
// Rs1 and Rs2 into data path only 

   ff_se_2 for_w_flop(.out (forward_data_w_mux_sel[1:0]),
                                      .din (forward_w_sel_din[1:0]),
                                      .enable (~hold_c),
                                      .clk (clk)
                                       );

   mux2_32 forward_data_w_mux(.out (forward_data_w[31:0]),
			      .in1 (dcu_data_w[31:0]),
			      .in0 (alu_out_c_d1[31:0]),
			      .sel (forward_data_w_mux_sel[1:0])
			      );
   assign alu_out_w = forward_data_w;
   ff_s_32 forward_data_w_reg(.out (forward_data_w1[31:0]),
			      .din (forward_data_w[31:0]),
			      .clk (clk)
			      );

   /*****************************
    *				*
    *		W1 stage	*
    *				*
    *****************************/

endmodule // ex_dpath