// squash_inst and stall out of sync. 
// no need for data valid signal. stall is asserted only for loads
// or an iu inst coming to dcu while dcu is processing a miss.
// dcu-smu-iu hold : for this to happen, iu issues a ld/st to dcu and in the same cycle,
// there is a smu-hold. to avoid this deadlock, dcu services the ld/st from iu and changes
// priority to smu. but, data of the ld is lost by iu bcos it doesnt use data_vlds.
// so, for loads, we redo the instruction by asserting stall for an extra cycle..

// ****************************************************************************************************

wire stall_pipe0,stall_pipe1,special_c ;
assign	cache_miss	= !(dcu_hit0|dcu_hit1);
assign	iu_stall	=  cache_miss&qualify_miss | stall_pipe; //bubble betn store followed by load
assign	qualify_miss	=  iu_ld_c | iu_anyinst_e&dc_inst_c;
assign	stall_pipe0	=  iu_ld_c&iu_nc_c|
			   iu_miss_ld & iu_miss_sustain |       // load waiting for data
                           iu_miss_stall_ld             |       // load waiting for data
			   squash_iu_inst ;

assign stall_pipe1      =  iu_anyinst_e& special_c |
			   special_raw_e&(req_outstanding | dc_inst_c) ;

assign special_c = 	non_cacheable_c | repl_busy |fill_cyc_active|
                           stall_valid | zeroline_c_raw |  smu_na_st_miss_cyc |
                           zeroline_busy | iu_flush_cmp_c | iu_flush_index_c |iu_flush_inv_c ;

assign stall_pipe = iu_ld_e & store_c | stall_pipe0 | stall_pipe1 ;

			 
assign	iu_data_vld	= dcu_hit_c & iu_ld_c& !iu_nc_c &iu_valid_c | iu_miss_ld&first_fill_cyc_d1| diag_ld_c ;
assign	smu_data_vld	= dcu_hit_c & smu_ld_c&!smu_nc_c   | smu_miss_ld&first_fill_cyc_d1 ;
 
assign smu_stall        =cache_miss&dc_inst_c    |       // SMU inst misses in C stage
			non_cacheable_c		|	// noncacheable instruction in C stage
                        smu_miss_sustain         |      // miss cycle in progress
                        smu_ld & any_store_c         |      // bubble betwn store followed by load
                        stall_valid     |		// there is a miss pending
                        smu_ld_st & (repl_busy | smu_na_st_miss_cyc)  |	// replacing dirty line or na store
			fill_cyc_active |			// cache fill occurring
                        zeroline_c   |				// zeroline inst execution
			zeroline_busy |
                        iu_anyinst_e_smu  | 
			smu_prty&~squash_iu_inst |	// Hold smu for one cycle during smu_hold- timing reason
                        iu_flush_inv_c | iu_flush_cmp_c | iu_flush_index_c       ;
 

// Performance Monitors:

assign	dcu_perf_mon[0]	=	dc_inst_c&~iu_recirculating_c&~smu_recirculating_c;	// D$ accesses
assign	dcu_perf_mon[1]	=	smu_st_c&~smu_recirculating_c;	// SMU D$ stores
assign	dcu_perf_mon[2]	=	smu_ld_c&~smu_recirculating_c;	// SMU D$ loads

ff_sr_3		dcu_perf_reg(.out(dcu_perf_sgnl[2:0]),
				.din(dcu_perf_mon[2:0]),
				.clk(clk),
				.reset_l(reset_l));
endmodule