Avoid Gate Clock and Asyn Reset

• Move gating to non-clock pin to prevent glitch from affecting logic. Example:

Carry-1

Q0

Q1

Q2

Binary Counter

TC

CK

Improved Design:

TC will not glitch during the transition of Qɘ:2> from 011 to 100

TC and Q may glitch during the transition of Qɘ:2> from 011 to 100

Poor Design:

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