Global Clock Buffers
Clock Buffers are low-skew, high-drive buffers
- Also known as Global Buffers
- Drive low-skew, high-speed long line resources
- Drive all Flip-Flops and Latches in FPGA
- Can also be used for high-fanout non-clock signals
Instantiation: if the BUFG component is instantiated, software will select one of these buffers based on the design
Synthesis: Clocks are identified by different means depending on Vendor
- Example: Synopsys FPGA compiler connects clock buffers to all fan-in of clock pins
- Control clock buffer insertion with separate commands
- Consult Synthesis interface guide or vendor