Flip-Flop Clock Enable

• Dedicated CE pin

  • Both Flip-Flops in a CLB must use same clock enable
  • Flip-Flops with Asynchronous Clear or Preset
  • Examples: FDCE, FDCPE

• CE implemented in the Look Up Table

  • Flip-Flops in CLB can have a separate clock enable
  • Flip-Flops with Synchronous Set or Reset
  • Examples: FDRE, FDSE, FDSRE

• Comparison of the two types of Flip Flops:

  • Dedicated version is faster and allows more functionality in the LUT (Look Up Table)
  • LUT version allows higher utilization of an FPGA with many clock enables

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