Programmable Logic Training Course FPGA Combinatorial Logic
Xilinx FPGA Architecture
Configurable Logic Blocks
Look-Up Table Review
9 input AND Example
4-to-1 MUX Example (1)
4-to-1 MUX Example (2)
Three-State Buffers
BUFTs for Multiplexers
Carry Logic
PPT 슬라이드
CLB Registers
Set and Reset Capabilities
Global Reset
Specify Asyn Initialization Value
Flip-Flop Clock Enable
Global Clock Buffers
Generating Clock On-Chip
Flip-Flop and Latch Components
Naming Conventions
Shift Register & Counter
16 Bit Counter Examples
Pipeline for Speed
Counter Tips
State Machine Design Tips(1)
State Machine Design Tips(2)
State Machine Design Tips(3)
Avoid Gate Clock and Asyn Reset
Use Clock Enables
Programmable Logic Training Course FPGA Memory
ROM and RAM components
LUT Provides 16X Flip-Flops
RAM Guidelines
128X1 RAM Example
128 X 1 RAM with Tri-State
How to Generate Memory
Initializing Memory (1)
Initializing Memory (2)
Programmable Logic Training Course FPGA I/O
IOB Block Diagram
Instantiation of IO Blocks (1)
Instantiation of IO Blocks (2)
Locking Down I/O Locations
Output Three-State Control
I/O Combinatorial Logic
IOB Flip-Flops and Latches
Use Pull-ups/Pull-downs to Prevent Floating
Slew Rate Control
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