Design Flow Programs (2)

• TRCE

  • Analyzes Timing
    • Use before PAR to analyze constraints

• PAR

  • Places COMPS on FPGA
  • Routes the FPGA

• TRCE

  • Analyzes Timing
    • Use after PAR to check delays

• NGDANNO

  • Back-annotate timing delays for Simulation

• BITGEN

  • Create file to configure FPGA

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