Design Flow Programs (1)
NGDBUILD
- Merges hierarchical EDIF or XNF files into one hierarchical file on the Flow Engine
- Creates internal netlist .ngd(Native Generic Design) files
- Contains logical components: combinatorial gates, RAMS, flip-flops, etc.
MAP
- Maps logical components to physical components found in Xilinx FPGA: look up tables, Flip-Flops, three state buffers, etc into the device
- Packs physical components into COMPS
- Creates internal .ncd (Native Circuit Design) file