Copyright: HH Bridge(c) Bristol Technology Inc. 1993


Timing Analyzer Overview
Overview

The Timing Analyzer performs static timing analysis of an FPGA or CPLD design. The FPGA design must be mapped and can be partially or completely placed, routed, or both. The CPLD design must be completely placed and routed. A static timing analysis is a point-to-point analysis of a design network. It does not include insertion of stimulus vectors.

The Timing Analyzer verifies that the delay along a given path or paths meets your specified timing requirements. It organizes and displays data that allows you to analyze the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths, and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the same design.

The Timing Analyzer works with synchronous systems composed of flip-flops and combinatorial logic. In synchronous design, the Timing Analyzer takes into account all path delays, including clock-to-Q and setup requirements, while calculating the worst-case timing of the design. However, the Timing Analyzer does not perform setup and hold checks; you must use a simulation tool to perform these checks.

The Timing Analyzer creates timing analysis reports, which you customize by applying filters with the Path Filters menu commands.

There are several ways to issue commands to the Timing Analyzer. You can select menus, click toolbar buttons, type keyboard commands in the console window, and run macros. For descriptions of Timing Analyzer commands, see Help Topics.


Timing Analyzer Window

The main window is the background against which all other windows are displayed. This window consists of the following parts.

Note:  Menus, dialog boxes, and parts of the application window are documented as they appear on a UNIX workstation. Differences between the PC and workstation applications are documented if there is a difference in operation between the two platforms.

Title Bar

This area displays the program name followed by the name of the currently loaded design.

Menu Bar

This area contains the menus that control the operation of the Timing Analyzer.

Toolbar

This area contains toolbar buttons that provide access to frequently used commands.

Status Bar

The status bar displays command and processing information.


Using Dialog Boxes

Many menu commands display dialog boxes in which you can enter information and set options.

Common Fields

The fields shown in the following table are common to most dialog boxes.

Dialog Box Field	Function
OK	Closes the dialog box and implements the intended action according to the settings in the dialog box
Cancel	Closes the dialog box without effecting any action
Help	Displays information on that particular dialog box
Moving Items within List Boxes

Many of the dialog boxes feature list boxes. You can select and move items from one list box to another using either the mouse or the keyboard, or a combination of these methods.

Use the mouse to select items in list boxes as follows.

•	To move an item to a list box on the right, select it with the left mouse button. Click the > button. To move an item to a list box on the left, select it, then click the < button.

•	To move all items to a list box on the right, click the >> button. To move all items to a list box on the left, click the << button.

•	To move sequential items, select the first one with the left mouse button. Hold down the Shift key. Select the last item and release the Shift key. Click the > or < button to move the selected items to the right or left list box, respectively.

You can also select the first item; drag the mouse up or down until all the desired items are highlighted; and then click the > or < button.

•	To move multiple items in any order, hold down the Ctrl key while clicking individual items. When finished selecting, release the Ctrl key and click the > or < button.

Use the keyboard to select items in list boxes as follows.

•	To move an item in a list box, press the Tab key until the first item in the list box is highlighted. Press the down arrow key to select the desired item. Tab to the > or < button to move it to the right or left list box, respectively. Press Enter.

•	To move all items to a list box on the right, tab to the >> button and press Enter. To move all items to a list box on the left, tab to the << button and press Enter.

•	To move consecutive items, tab to the first item in the list box. Use the down arrow key to highlight the first desired item. Press and hold the Shift key while using the down arrow key to select the other items in the sequence. Tab to the > button. Press Enter.

•	On workstations only: To move multiple items in any order, tab to the list box and press Shift F8. Use the up and down arrow keys to navigate within the list box. Press the space bar to select each item. Tab to the > button. Press the Enter key. This method applies only to workstations.

Using Filters with Commands

Many menu commands have dialog boxes that allow you to filter a list of choices, that is, display a subset of the listed items. These dialog boxes contain a filter field, Apply buttons, and Clear or Reset buttons.

In filter fields, you can enter a text string consisting of characters and wildcards. You cannot enter a range of items in filter fields.

•	Characters can be any alphanumeric characters, text spaces, and the characters that appear on the top of the number keys on a keyboard. Alphabetic characters are case-sensitive. Control characters are not permitted.

•	A wildcard can be an asterisk (*), which can represent any number of characters, or a question mark (?), which represents a single character.

The software does not strictly match patterns; it matches entire text strings. It does not find a string if it is embedded in a larger string unless you use wildcards. For example, it does not find $1N36 if it is embedded in ABC$1N36XYZ. However, if you searched for *$1N36*, it would find that string in ABC$1N36XYZ.

To use the Filter dialog boxes, follow these steps.

1.	Specify the pattern to include in your list by typing the characters.

2.	Include one or more wildcards (*) to do a global search on the specified string.

Precede the character string with a wildcard to retrieve all signal names that end with the string of specified characters.

Append the wildcard to the character string to retrieve all signal names that start with the specified character string.

3.	Click Apply.

The list displays only the choices that match the selection criteria.

4.	To clear the filter, click Clear or Reset or backspace over the information specified in the filter text box.


How to Use Help

This page is a quick reference guide to the Timing Analyzer Help.

Help Topics Organization

Getting Started	An overview of the Timing Analyzer and instructions for using the interface
Procedures	Step-by-step instructions for performing tasks
Commands	Descriptions of commands available from menus and buttons
Help on Help	Instructions for using help and how to access it
Reference	Glossary, trademark, technical support, and additional resource information
Summary of Help Operations

To	Do this
Go to related topics	Click underlined words
Go to the Help Topics	Click Help Topics
Search in the Help	Click Index or Find, select a topic
Scroll in the Help window	Move the scroll bars with the mouse
Return to the previous topic	Click Back
Return to any previous topic	From the Options menu, select Display History Window and select a topic
Browse forward	Click Browse>>
Browse backward	Click <<Browse
Get detailed help on Help	On the workstation, select How to Use Help from the Help menu
Close the Help window	Select Exit from the Help File menu
Printing Help Topics	On the workstation, select How to Use Help from the Help menu, and select Configure a Printer from the How To list


Obtaining Help

You can obtain help on commands and procedures by clicking the Help button in the toolbar, clicking the Help button in dialog boxes, or pressing the F1 key. The Help button in the toolbar and in some menu command dialog boxes provides context-sensitive help.

Help Menu

The Help menu displays the following commands.

•	Help Topics lists the online help topics available. From the opening screen, you can jump to command information or step-by-step instructions. After you open help, you can click the Help Topics button (first button on the left) in the Help window whenever you want to return to the help topics list.

•	About Timing Analyzer displays a popup window that shows the version number of the software.

Toolbar

You can obtain context-sensitive help from the toolbar.

1.	Click the Help button.

The cursor changes to a question mark.

2.	Click once with the left mouse button on the menu item or toolbar button for which you want information.

Online help information about the selected command appears in a popup window.

Help Button in Dialog Boxes

Many of the dialog boxes have a Help button that you can click to obtain help on that dialog box. A window opens that displays information.

F1 Key

Pressing the F1 key when the cursor is placed on a dialog box displays help on that dialog box. The F1 key functions the same as selecting Help Topics from the Help menu, if no dialog boxes are displayed.


Opening a Design

To open a design

1.	Select Open Design from the File menu, or click the Open Design button.

The Open Design dialog box appears.

2.	In the Look in list box, click on the directory containing the NCD (FPGA) or VM6 (CPLD) file to load.

3.	Under Files of Type/List Files of Type, select FPGA Designs (*.ncd) or CPLD Designs (*.vm6).

All the available NCD or VM6 files are now displayed in the list box.

4.	Select a mapped NCD (FPGA) or a completely placed and routed VM6 (CPLD) design file from the list box, or type the name in the field below File Name. The mapped FPGA design can be partially or completely place, routed, or both. (*.ncd appears as the default; backspace over the asterisk before typing in the design file name.)

5.	Click OK.

The Timing Analyzer reads your design and device information, processes any timing constraints, and then loads your design. For FPGA designs, the Timing Analyzer also reads the .pcf physical constraints file with the same name as the design file, if one exists in the same directory as the design file.

When your design is loaded, the path name and design file name appear at the top of the Timing Analyzer main window, as in this example.

/ta/designs/checkers.ncd

You can now create a timing report.

Warning:  If you open a design when another design is open, the Timing Analyzer resets the current settings to the defaults. If you re-open a design that is already open, the Timing Analyzer also resets the current settings to the defaults and opens the default PCF, if it exists.


Opening a Physical Constraints File

This procedure applies only to FPGAs, because timing constraint information for CPLDs is contained in the (VM6) design file itself. The order of the timing constraints in the PCF file is reflected by the Timing Analyzer.

To automatically open a physical constraints file

When you open a design using the Open Design command in the File menu, the Timing Analyzer automatically loads the default Physical Constraints File if it exists. The default Physical Constraints File is a file with the same name as the design in the same directory as the design file.

A message similar to the following appears on the right side of the status bar at the bottom of the Timing Analyzer window.

/home/user/ta/designs/design10.pcf

If there is no default physical constraints file, a message box appears with a message similar to the following.

No default Physical Constraints File found for design "/home/user/ta/designs/design10.ncd"

To manually open a physical constraints file

If you already have a design open and wish to load a different Physical Constraints File for use with the current design, follow these steps.

1.	Select Open Physical Constraints from the File menu.

The Open Physical Constraints dialog box appears.

2.	In the Look in list box, click on the directory containing the PCF file to load.

3.	Under Files of Type/List Files of Type, Physical Constraints (*.pcf) is the default and is the only file type you can select.

All the available PCF files are displayed in the list box.

4.	Select a PCF file from the list box, or type the name in the field below File Name. (*.pcf appears by default; backspace over the asterisk before typing in the physical constraints file name.)

5.	Click OK.

The Timing Analyzer reads the .pcf file and the path name appears on the right side of the status bar at the bottom of the Timing Analyzer main window.


Displaying the Toolbar

By default, the Timing Analyzer toolbar is displayed. The toolbar appears below the pull-down menu bar.

To disable the toolbar

To prevent display of the toolbar, select Toolbar from the View menu.

If the toolbar is already visible, a box to the left of Toolbar is selected. (Re)selecting Toolbar deselects the box and does not display the toolbar.


Viewing Status

The Timing Analyzer displays descriptions of menu commands and the name of the current physical constraints file in the Status Bar at the bottom of the Timing Analyzer main window. By default, the Status Bar is displayed.

To disable status bar

To prevent display of the current state, select Status Bar from the View menu.

If the status bar is already visible, a box to the left of Status Bar is selected. (Re)selecting Status Bar deselects the box and does not display the status.


Viewing Clocks in a Design

To view clocks in the current design

Select Clocks from the View menu.

The Timing Analyzer displays a pop-up window listing all the clocks in the current design.


viewing Timing Analyzer settings
Viewing Settings

To view the Timing Analyzer current settings

Select Settings from the View menu.

The Timing Analyzer displays a pop-up window with the current settings and options. When you change an option setting or a path filter, the change is immediately reflected in the window.


Querying for Information

You can obtain information about the timing of particular nets or members of a time group, using the Query command.

Note:  The Query command only supports FPGA designs.

To perform a query and generate a query report

1.	Select Query from the Analyze menu, displaying the Query dialog box.

2.	Select the Nets or TimeGroups radio button. Nets is the default.

All of the nets or time groups not disabled by other commands are listed in the Available Nets/TimeGroups list box.

3.	If Nets is selected, enter a value in the Delay Greater Than field, if desired.

You can only enter a value in the Delay Greater Than field if you selected Nets.

4.	Enter a filter in the other portion of Filter, to display a subset of the delay group, and click Apply.

5.	Select nets or timing groups that you want to query from the Available Nets/TimeGroups list box and move specific ones or all of them to the Selected Nets/TimeGroups list box. Use the >, >>, <, and << buttons. The buttons are enabled and disabled as you move items between the list boxes.

6.	Click OK.

The Timing Analyzer displays the Query Nets/TimeGroups Report in a pop-up window, which can be saved as a TWR report file. Nets/TimeGroups is Nets or TimeGroups; it corresponds with the selection you make in step 2.


Creating a Custom Analysis Report

The Custom Analysis report displays a detailed analysis of all specified paths. It contains the worst-case path delays for all paths that are not filtered out.

To create a Custom Analysis report

Select Custom from the Analyze menu, or click the Custom button on the toolbar.

When analysis is complete, a Custom Analysis report window appears with the results. The contents of the window can be saved as a TWR report file using the Save or Save As commands.

This command has an interrupt function when analyzing FPGA designs. When the Custom command is selected, a Timing Analysis in Progress dialog box with an Abort button appears. Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis. A report is not generated and data is not displayed.

You can use the following path filtering commands to modify the scope of this report.

•	Select Sources

•	Select Destinations

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing


Creating a Clocks Report

The Clocks command opens a window that lists the names of all clocks in the design. You can save the contents as a report file using the Save or Save As commands in the File menu.

To create a Clocks report

1.	Select Clocks from the View menu. A Clocks window appears, listing all of the clocks in the design. The contents of the window can be saved to a file.

2.	Select Save from the File menu. The Save As dialog box appears. Type a name in the File Name field (the default is Clocks). Add a .twr extension to the file name to list it as a Timing Analysis Report when using the Open command in the File menu.

3.	In the Save in list box, select the directory in which you want to save the information from the list box.

4.	Click OK.


Creating an Advanced Design Analysis Report

The Advanced Design Analysis report provides a set of summary statistics for the paths from the timing requirements specified for analysis. For FPGAs, this report displays the maximum clock frequencies for all clocks in the design and the worst-case timing for all clock paths. For CPLDs, this report displays all external pad-to-pad (tPD), clock-pad-to-output pad (tCO), setup-to-clock-at-the-pad (tSU), and internal clock-to-setup (tCYC) delays.

To create an Advanced Design Analysis report

Select Advanced Design from the Analyze menu, or click the Advanced Design button on the toolbar.

When analysis is complete, an Advanced Design Analysis report window appears with the results. The contents of the window can be saved as a TWR report file using the Save or Save As commands.

This command has an interrupt function when analyzing FPGA designs. When the Advanced Design command is selected, a Timing Analysis in Progress dialog box with an Abort button appears. Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis. A report is not generated and data is not displayed.

You can use the following path filtering commands to modify the scope of this report.

•	Disable Timing Constraints

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing


Creating a Settings Report

The Settings command opens a window that lists all option settings in the design. You can save the settings as a macro or report using the Save or Save As commands on the File menu.

To create a Settings report

1.	Select Settings from the View menu. A Settings window appears, listing all of the current settings. The contents of the window can be saved to a file.

2.	Select Save from the File menu. The Save As dialog box appears. Type a name in the File Name field (the default is Settings). Add an .xtm extension to save the file as a macro or a .twr extension to save the file as a report.

3.	In the Save in list box, select the directory in which you want to save the macro or report from the list box.

4.	Click OK.


creating Timing Analysis reports
Creating a Timing Constraints Analysis Report

The Timing Constraints Analysis report compares the design's performance to the timing constraints. The Timing Constraints submenu in the Analysis menu contains three commands for generating different types of Timing Constraints Analysis reports as described below.

In addition to using these three timing report commands, you can use the following path filter commands to specify the scope of the information reported in the Timing Constraints Analysis reports. These commands are located in the Timing Constraint Filters submenu of the Path Filters menu.

•	Disable Timing Constraints

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing

The number of paths reported is affected by the Limit Report To setting in the Report Options dialog box, which you access with the Report Options command.

To create a Timing Constraints Analysis report

Select one of the following commands in the Timing Constraints submenu in the Analyze menu:

•	Report Paths in Timing Constraints - Generates a Timing Constraints Analysis report for all paths covered by timing constraints.

•	Report Paths Failing Timing Constraints - Generates a Timing Constraints Analysis report for only the paths that do not meet the timing constraints.

•	Report Paths Not Covered by Timing Constraints - Generates a Timing Constraints Analysis report for paths covered by timing constraints and for paths not covered by timing constraints.

You may alternatively click one of the following three timing analysis buttons on the toolbar. These correspond in order from left to right to the three report commands listed above.

The three report timing constraints commands have an interrupt function when analyzing FPGA designs. When running these commands, a Timing Analysis in Progress dialog box with an Abort button appears. Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis and prevents a report from being generated or displayed.

When analysis is complete, a Timing Analysis report window appears with the results.The contents of the window can be saved as a TWR report file using the Save or Save As commands.


Changing Speed Grade

The speed grade is usually set during the design implementation process. Changing the speed grade helps you determine if you need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints.

Changing the speed grade may affect the worst case and range of values available in the Prorating Options dialog box.

Note:  Changing the speed grade with the Timing Analyzer only affects analysis; the speed grade in the design file is not changed.

To change the speed grade

1.	Select Speed Grade on the Options menu to open the Speed Grade dialog box.

2.	Select a speed grade from the list of available speed grades using one of the following methods.

•	Using the mouse, click on the down arrow and select a speed grade.

•	Using the keyboard, tab until the speed grade is highlighted, and press the up or down arrow keys until the appropriate speed grade appears.

For families that support minimum speed grades, a Min selection is available in the speed grade list.

3.	Click OK.


Customizing a Report

You can determine the appearance and the content of the reports that the Timing Analyzer generates.

To set report options

1.	Select Report Options from the Options menu to open the Report Options dialog box.

2.	After specifying all desired report options in the dialog box, click OK.

The Report Options dialog box closes. You can now select another filtering command or generate a Timing Constraints Analysis report by selecting one of the timing analysis commands in the Timing Constraints submenu in the Analyze menu.


Searching for Text in a Report or Macro

You can search for any text string in the active report or macro window, including normal grammatical symbols like hyphens or underscores. You cannot search for special characters like tabs or hard returns.

To search for a text string in a report

1.	Open or select the report or macro window in which you want to search.

2.	Select Find from the Edit menu to open the Find dialog box.

3.	Enter the text string that you want to search for in the Find What field.

4.	Click the Match Case box if you want the option of specifying case sensitivity.

Match Case finds only instances that have the same case as the text string. By default, case is ignored.

5.	Indicate the search direction.

•	Up searches backward from the present location of the cursor to the beginning of the report. Searching stops at the beginning of the report.

•	Down searches forward from the present location of the cursor to the end of the report. Searching stops at the end of the report. This direction is the default.

6.	Click Find Next, the F3 key, or select Find Next from the Edit menu to find the next instance of the text string.

7.	Click Help for help on the Find command.

8.	Click Cancel to close the Find dialog box.


Printing a Report

You can send a Timing Analyzer report to your default printer, or you can send it to a printer that you specify.

To print a report

1.	Select Print from the File menu, or click the Print button.

The Timing Analyzer displays the Print dialog box, which indicates the default printer.

Note:  PC and workstation Print dialog box options may vary.

2.	If you want to print more than one copy, enter the number of copies that you want to print in the Copies field.

3.	If you want to print a range of pages, enter "From" and "To" pages in the corresponding boxes.

4.	If you want to print to a file, select the Print to File box.

5.	Click OK.


Saving a Report

To save a report

1.	Make sure the report that you want to save is in the active window by clicking on it. The active window has a colored border.

2.	Click Save from the File menu, or click the Save button.

The Timing Analyzer displays the Save As dialog box.

3.	Under List Files of Type, click on the down arrow to display the pull-down list box of available file types. Highlight a format to select it. File names of that format appear in the list box below the File Name field.

4.	In the File Name field, type the name of the file in which to store the report. Add a .twr extension to the file name.

If this is the first time you are saving the file, the Timing Analyzer provides a default name corresponding with the type of information contained in the window, with a .twr extension.

If you want to overwrite an existing file with the new report, click on that file in the list box, so it appears in the File Name field.

You can also use word processor applications to open and edit the report file.

5.	In the Save in list box, select the directory in which you want to save the report.

6.	Click OK.


Closing a Report

You can close a report in three ways.

To close a report

Here is one method.

Select Close from the File menu.

If the report has been previously saved, the window closes. If it has not been saved, the Save As dialog box appears; see the Saving a Report section for the procedure to save a report.

Here is a second method.

1.	Make sure the report that you want to close is in the active window by clicking on it. The active window will have a colored border.

2.	Click the horizontal bar in the upper left-hand corner of the report window.

A pop-up menu appears.

3.	Select Close from the menu.

A dialog box appears and prompts you about saving changes to the file. The available choices are Yes, No, and Cancel buttons.

4.	If you click Yes, the Save As dialog box appears. If you click No, the dialog box and report window both close. If you click Cancel, the dialog box closes and the report window remains open.

Here is a third method.

1.	Make sure the report that you want to close is in the active window by clicking on it.

2.	Type Ctrl F4 from the keyboard.

A dialog box appears and prompts you about saving changes to the file. The available choices are Yes, No, and Cancel buttons.

3.	If you click Yes, the Save As dialog box appears. If you click No, the dialog box and report window both close. If you click Cancel, the dialog box closes and the report window remains open.


Opening a Saved Report or Macro

To open a previously saved report to view or print, or a macro to run

1.	Select Open from the File menu.

The Open dialog box appears.

2.	In the Look in list box, click on the directory containing the report or macro file to load.

3.	In the List Files of Type field, select Timing Analysis Reports (*.twr). The default is Timing Analysis Macros (*.xtm).

All the report or macro files are displayed in the list box. You can list and open any text file by selecting All Files (*.*).

4.	Select a report or macro file from the list box, or type the name in the field below File Name after backspacing over the asterisk. If you do not specify a file extension, the Timing Analyzer loads an XTM (macro) file by default.

5.	Click OK.


Disabling Timing Constraints

You can omit particular timing constraints from analysis.

To disable timing constraints in a report

1.	Select Disable Timing Constraints from the Timing Constraint Filters submenu in the Path Filters menu.

The Disable Timing Constraints dialog box appears. If an FPGA design is open, Include PCF Entered Constraints is selected by default. Click the Omit PCF Entered Constraints radio button if you want to include user constraints during analysis. User constraints are contained in the "USER" section of the PCF. These two buttons and their functions are only available for FPGAs.

2.	Enter a filter in the Filter for Enabled Timing Constraints field to display a subset of timing constraints, if desired, and click Apply.

3.	Select the timing constraints that you want to exclude from the Timing Analysis report by using the >, >>, <, and << buttons to move constraints from the Enabled Constraints list box to the Disabled Constraints list box.

The buttons are enabled and disabled as you move constraints between the list boxes by applicability.

4.	Click OK.

The Disable Timing Constraints dialog box closes. You can now select another command or generate a Timing Analysis report.


Using Custom Filters

You can select starting points, ending points, and specific path types using commands described in this section to modify the scope of path analysis information reported in the Custom Analysis report. These commands exist in the Custom Filters submenu of the Path Filters menu. By default, the Timing Analyzer selects all sources and all destinations for path analysis.

Selecting Sources

You can select the starting points for path analysis. By default, the Timing Analyzer analyzes all sources during path analysis. After you select sources to include, you can generate a Custom Analysis report.

To select specific sources for path analysis

1.	Choose Select Sources from the Custom Filters submenu in the Path Filters menu to open the Select Sources dialog box.

2.	Select the source type by clicking the down arrow of the Source Element Type pull-down list box to display the list of sources, then highlight it. The default is Flip-Flops.

FPGA source types can be flip-flops, RAMs, latches, pads, nets, pins, CLBs, clocks, or timegroups. CPLD destination types can be flip-flops, pads, nets, macrocells, or clocks.

Element in the Filter field and the Source Element list box changes to match the source type you select.

3.	If you select Clocks, indicate the source clock edge by clicking the down arrow and highlighting a selection in the Clock Edge field. Clock edges are only supported for FPGA designs.

4.	Enter some text in the Filter field to display a subset of the specified source type, if desired, and click Apply.

5.	Select the sources you want to include in Timing Analysis by using the >, >>, <, and << buttons to move elements from Source Element to Selected Sources.

The Select Sources dialog box utilizes a special way of representing nets in the Source Element and Selected Sources list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Source Flip-Flops list box and move it to the Selected Sources list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flop nets are selected. You get the same result if you individually move all the Flip-Flop nets from the Source Flip-Flops list box to the Selected Sources list box.

6.	Repeat steps 2 through 5 until you move all desired elements to Selected Sources.

7.	Click OK.

The Select Sources dialog box closes. You can now select another path filtering command or generate a timing report.

Selecting Destinations

You can select the ending points for path analysis. By default, the Timing Analyzer selects all destinations for path analysis.

After you select destinations to include, you can generate a Custom Analysis report.

To select specific destinations for path analysis

1.	Choose Select Destinations from the Custom Filters submenu in the Path Filters menu to open the Select Destinations dialog box.

2.	Select the ending point type by clicking the down arrow of the Destination Element Type pull-down list box to display the list of destinations, then highlight it. The default is Flip-Flops.

FPGA destination types can be flip-flops, RAMs, latches, pads, nets, pins, CLBs, clocks, or timegroups. CPLD destination types can be flip-flops, pads, nets, macrocells, or clocks.

Element in the Destination Element list box changes to match the destination type you select.

3.	If you select Clocks, specify the type of clock edge by clicking the down arrow and making a selection in the Clock Edge field.

4.	Enter some text in the Filter field to display a subset of the specified source type, if desired, and click Apply.

5.	Select the destinations you want to include in Timing Analysis by using the >, >>, <, and << buttons to move elements from Destination Element to Selected Destinations.

The Select Destinations dialog box utilizes a special way of representing nets in the Destination Element and Selected Destinations list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Destination Flip-Flops list box and move it to the Selected Destinations list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flop nets are selected. You get the same result if you individually move all the Flip-Flop nets from the Destination Flip-Flops list box to the Selected Destinations list box.

6.	Repeat steps 2 through 5 until you move all desired elements to Selected Destinations.

7.	Click OK.

The Select Destinations dialog box closes. You can now select another filtering command or generate a timing report.


using common filters commands
Using Common Filters

You can include or exclude paths with nets or control path tracing using commands described in this section to modify the scope of timing analysis. These commands exist in the Common Filters submenu of the Path Analysis menu.

After using these commands, you can generate a Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis report.

Including Paths with Nets

Use the Include Paths with Nets command to limit analysis to paths that contain specified nets. After selecting the paths with nets to include, you can generate Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis reports.

To select nets to be analyzed

1.	Select Include Paths with Nets from the Common Filters submenu of the Path Filters menu.

The Include Paths with Nets dialog box appears.

2.	Enter some text in the Filter field to display a subset in the Available Nets list box, if desired, and click Apply.

3.	Select the nets that you want to include in timing analysis by using the >, >>, <, and << buttons to move elements from the Available Nets list box and move specific ones or all of them to the Selected Nets list box.

4.	Click OK.

The Include Paths with Nets dialog box closes. You can now select another filtering command or generate a timing report.

Excluding Paths with Nets

Use the Exclude Paths with Nets command to exclude paths containing specific nets from analysis. Any paths that pass through the selected nets are not analyzed. After you select which nets to exclude, you can generate Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis reports.

To exclude specific nets from analysis

1.	Select Exclude Paths with Nets from the Common Filters submenu of the Path Filters menu.

The Exclude Paths with Nets dialog box appears.

2.	Enter some text in the Filter field to display a subset in the Available Nets list box, if desired, and click Apply.

3.	Select the nets that you want to exclude from timing analysis by using the >, >>, <, and << buttons to move elements from the Available Nets list box and move specific ones or all of them to the Selected Nets list box.

4.	Click OK.

The Exclude Paths with Nets dialog box closes. You can now select another filtering command or generate a timing report.

Controlling Path Tracing

Use the Control Path Tracing command to enable or disable path analysis through delay path types for specific components, such as latches, RAMs, tristate buffers, input and output pins, components, and Set/Reset logic. These paths may be irrelevant to your analysis.

Note:  This command applies only to FPGAs; it is disabled if a CPLD design (.vm6) is open. (CPLD path tracing analysis ignores paths through Set/Reset logic and breaks paths at bidirectional I/O pins.)

After you specify which path types to control through which components, you can generate a Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis report.

To control path tracing

1.	Select Control Path Tracing from the Common Filters submenu of the Path Filters menu.

The Control Path Tracing dialog box appears.

2.	Select the path type for which you want to control tracing in the Path Type field. Click on the down arrow and highlight one of the path types.

The components of that path type in the design appear in the Enabled Components or Disabled Components list box, depending on the default state of that path type.

3.	Enter some text in the Filter field to display a subset of components of the specified type, if desired, and click Apply.

4.	Select components that you want to enable or disable by moving them from Disabled Components to Enabled Components and vice versa using the >, >>, <, and << buttons.

5.	Click OK.

The Control Path Tracing dialog box closes. You can now select another filtering command or generate a timing report.


Resetting All Path Filters

You can reset all of the path filtering commands to the design defaults. To view the current settings, see Viewing Settings.

To reset the paths filters to the defaults

Select Reset All Path Filters from the Path Filters menu. To then view those default settings, select Settings from the View menu.


Using the Console Window

The Console window records all the commands that you use in a Timing Analyzer session. You can use these commands to form macros, as described in the Creating a Macro section. In addition, it provides an alternative to using some menu commands by allowing you to enter commands from the keyboard.

With all these methods, the Timing Analyzer starts the search from the bottom of the command list.

To execute a command from the Console window

1.	To open the Console window, select Console from the View menu.

The Console window appears.

Note:  You cannot delete text from within the Console window.

2.	You can add a command manually by typing it in the field at the bottom of the window below the Show Command Status box. The number of the next consecutive command is displayed to the left of the field.

Use the syntax given for the command in the Command Summary section. After you enter the command and press the Return key, the command is executed and reflected in the Console window.

To re-execute commands in the Console window

If you want to re-execute a command in the Console window, use one of the following methods in the field at the bottom of the window.

•	Type two exclamation points (!!) to re-execute the previous command.

•	Type an exclamation point (!) and the number of the command.

•	Type an exclamation point (!) and the first letter or first few letters of the command.

To display status messages in the Console window

Click on the Show Command Status box to display status messages. Deselect the box to hide status messages. By default, status messages are not displayed.


Suppressing Messages

When you run a macro, the commands in the macro file can generate informational, confirmational, and error messages. You can suppress the informational and confirmational messages by using this procedure. You cannot suppress these messages while executing menu commands. This command does not have an equivalent menu command.

To suppress informational or confirmational messages

1.	Select Console from the View menu.

2.	In the field at the bottom of the Console window, type this command:

SetForce on

3.	If you are creating a new macro, follow the procedure in the Creating a Macro section, adding the SetForce on command when you want to suppress messages, for example, after opening a design.

If you want to suppress the messages for an existing macro, open the macro and cut and paste the SetForce on command into the macro using the instructions in the Editing a Macro section.

4.	Run the macro with the Run Macro command from the File menu.

5.	To restore the informational and confirmational messages, type this command.

SetForce off


Creating a Macro

To create a macro

1.	Select Console from the View menu to open the Console window.

Alternatively, you can create or edit a macro manually or create one by entering keyboard commands in a text file.

2.	From the Timing Analyzer menus, select the commands that will constitute the macro or type console commands in the field at the bottom of the window.

The commands are recorded in the Console window numerically.

3.	Select New Macro from the File menu, or click the New Macro button, to open the New Macro window.

4.	In the Console window, hold down the left mouse button and highlight the sequence of commands that will constitute the macro.

5.	Click the Copy button.

6.	Position the cursor in the New Macro window and click the Paste button.

The lines from the Console window are pasted into the New Macro window.

You can also highlight, copy, and paste individual lines from the Console window to the New Macro window.

You can add text in the New Macro window by inserting the cursor and typing. Delete text by pressing the backspace key or by highlighting and pressing the Delete key.

7.	Save the new macro by following the instructions in the Saving a Macro section.


Saving a Macro

You can save a macro in a new file, the same file, or an existing file.

To save a new macro

1.	Select Save from the File menu, or click the Save button.

The Save As dialog box appears.

2.	In the Save in list box, select the directory in which you want to save the macro.

3.	In the List Files of Type field, make sure Timing Analysis Macros (*.XTM) is selected.

A default file name related to the command(s) in the new macro window with an .xtm extension appears in the File Name field.

4.	Type a name for your new macro in the File Name field.

You must save the macro in a file with an .xtm extension.

5.	Click OK.

To save an edited macro to the same file

If you want to save an edited macro in the same file, select Save from the File menu.

If you have already saved the macro once, the Save command saves the macro in the specified file without activating the Save As dialog box.

To save an edited macro to a different file

1.	Follow the procedure in the "To save a new macro" section up to step 4.

2.	Highlight the part of the file name that appears before .xtm. Type a different file name.

If you want to save the macro to the existing file, select the name of the existing file in the list box.

3.	Click OK.

If you are overwriting an existing file, a message box appears, asking if you want to overwrite the current macro. Click Yes.


Running a Macro

To run a macro

1.	Select the Run Macro command from the File menu to open the Run Macro dialog box.

2.	In the Look in list box, select the directory in which the macro file is located. All macro files with an XTM extension are listed in the list box.

3.	Click on the macro file in the list box that you want to run.

4.	Click Open.

To run a macro displayed in an editor window

1.	Click on the window to make it the active window.

2.	Click the Run Macro toolbar button.


Editing a Macro

To edit a macro

1.	Select Open from the File menu.

The Open dialog box appears.

2.	In the Look in list box, select the directory in which the macro file is located.

3.	In the List Files of Type field, select Timing Analysis Macros (*XTM).

4.	In the File Name field, type the name of the macro file that you want to open. Alternatively, click on the name of the XTM file in the list box.

5.	Click OK.

The Open dialog box closes, the macro window appears and remains highlighted.

6.	Edit the macro. See Creating a Macro to add, delete, copy, and paste commands in the macro window.

7.	If you want to save the edited macro in the same file, click Save from the File menu. The Save command saves the macro without activating the Save As dialog box.

If you want to save the edited macro to another file, see Saving a Macro.


New Macro command
New Macro (File Menu)

The New Macro command creates a new Timing Analyzer macro document window, in which you can perform text editing to create a macro. You can also copy commands from the Console window and paste them in a New Macro window. The macro is saved to an .xtm file, which is the only document type you create directly in Timing Analyzer. The equivalent keyboard shortcut for the New Macro command is Ctrl N. Selecting this command performs the same function as clicking the New Macro button.

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See also

Console

Creating a Macro

Saving a Macro

Using the Console Window


Open Design command
Open Design (File Menu)

The Open Design command loads a mapped NCD (FPGA) or a completely placed and routed VM6 (CPLD) design file. The mapped FPGA design can be partially or completely placed, routed, or both. For FPGAs, a physical constraints file (PCF) is also needed for timing analysis for specific constraints. By default, the Timing Analyzer opens the PCF file with the same name and in the same directory as the design file. You can analyze the same design with different PCF files. It displays the Open Design dialog box. Selecting this command performs the same function as clicking the Open Design button.


Open Design Dialog Box

Use this dialog box for the following.

Opening a Design

You open this dialog box with the Open Design command in the File menu.

File Name

Specifies the NCD (FPGA) or VM6 (CPLD) design file to load.

Look in/Directories

Lists the directories (for the specified drive on PCs) so you can select the directory that contains the design file that you want to load.

Files of Type/List Files of Type

Specifies whether the file to load is an NCD (FPGA) or a VM6 (CPLD) design file.The default is an NCD file.

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See also

OpenDesign

Toolbar


Open Physical Constraints command
Open Physical Constraints (File Menu)

The Open Physical Constraints command displays the Open Physical Constraints dialog box, which you use to load an existing physical constraints file (PCF) other than the default. The default PCF file has the same name and exists in the same directory as the NCD design file. The order of the constraints in the PCF file is reflected by the Timing Analyzer. This command only supports FPGAs; CPLD physical constraint information exists in the (VM6) design file itself.


Open Physical Constraints Dialog Box

Use this dialog box for the following.

Opening a Physical Constraints File

You open this dialog box with the Open Physical Constraints command in the File menu.

File Name

Specifies the PCF file to load.

Look in/Directories

Lists the directories (for the specified drive on PCs) so you can select the directory that contains the physical constraints file that you want to load.

Files of Type/List Files of Type

Lists physical constraints files.

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See also

OpenPCF


Open command
Open (File Menu)

The Open command opens existing timing analysis report (TWR), macro (XTM), or other text files. It displays the Open dialog box.


Open Dialog Box

Use this dialog box for the following.

Editing a Macro

Running a Macro

Opening a Saved Report or Macro

You open this dialog box with the Open command in the File menu.

File Name

Specifies the name of the macro, report, or other file to load. The default is a report (TWR) file.

Look in/Directories

Lists the directories (for the specified drive on PCs) so you can select the directory that contains the file that you want to load.

Files of Type/List Files of Type

Indicates the category of file to list. It can be an XTM, a TWR, or all files. TWR is the default.

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See also

Run Macro


Close command
Close (File Menu)

The Close command closes the active report, macro, or design file.

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See also

Save

Closing a Report

Saving a Report


Save command
Save (File Menu)

The Save command saves the report or text file in the active window to a specified file. It also saves macros created by the New Macro command. By default, the Timing Analyzer saves reports as TWR files and macros as XTM files. This command brings up the Save As dialog box, which you can use to save reports and macros as different files. If you saved the report or macro once, the Save command saves the document in the existing file without activating the Save As dialog box. Selecting this command performs the same function as clicking the Save button.

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See also

Close

Closing a Report

Saving a Report

Saving a Macro

Toolbar


Save As command
Save As (File Menu)

The Save As command saves the edited report or macro to another file. It displays the Save As dialog box, which is the same dialog box activated by the Save command.


Save As Dialog Box

Use this dialog box for the following.

Saving a Macro

Editing a Macro

Saving a Report

You open this dialog box with the Save As command in the File menu.

File Name

Specifies the name of the file in which to store the report or macro. If a macro window is active, the default file name is Timing.xtm and Timing Analysis Macros are listed in the List Files of Type field. If a report window is active, the default file name is Design.twr and Timing Analysis Reports are listed in the List Files of Type field. You can select an existing file from the list box to overwrite an existing file.

Save in

Lists the directories (for the specified drive on PCs) so you can select the directory in which to save the report or macro file.

Save as type

Allows you to select a category of file type to display in the File Name field and list box. You do not have to save the file as a TWR or an XTM file, but the Timing Analyzer saves reports as TWR and macros as XTM files by default. The Timing Analyzer only reads XTM files, that is, files with an .xtm extension.

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See also

Save


Run Macro command
Run Macro (File Menu)

The Run Macro command displays the Run Macro dialog box, which allows you to select a specific macro file to be executed. A macro is a script file that contains Timing Analyzer commands, filters, report options, or all three.

The Recent Macro MRU list in the File menu shows the four macros that have been most recently run or opened for editing.

The Run Macro toolbar button just runs the macro in the active window.


Run Macro Dialog Box

Use this dialog box for the following.

Running a Macro

You open this dialog box with the Run Macro command in the File menu.

Look in/Directories

Lists the directories (for the specified drive on PCs) so you can select the directory that contains the macro you want to run.

File Name

Specifies the name of the macro that you select in the list box.

Files of Type/List Files of Type

Indicates the category of file to list. The default is an XTM file.

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See also

RunMacro

Toolbar


Print command
Print (File Menu)

The Print command displays the Print dialog box, which sends the file displayed in the active window to the default printer and allows you to indicate how many copies to print, to send the file to a printer other than the default, or to change printer options. Selecting this command performs the same function as clicking the Print button.

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See also

Printing a Report

Toolbar


Recent Design command
Recent Design (File Menu)

The Recent Design command lists up to the last four design files (NCD for FPGA or VM6 for CPLD) that you opened. The design you select is automatically loaded as the current design. For FPGAs, its default physical constraints file is also loaded.

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See also

Open Design

OpenDesign

Opening a Design


Recent Physical Constraints command
Recent Physical Constraints (File Menu)

The Recent Physical Constraints command lists up to the last four physical constraints files that you opened. The physical constraints file you select is automatically opened.


Recent Macro command
Recent Macro (File Menu)

The Recent Macro command lists up to the last four macro files that you opened. The macro you select is automatically opened.


Recent Report command
Recent Report (File Menu)

The Recent Report command lists up to the last four reports that you opened. The report you select is automatically opened.


Recent File command
Recent File (File Menu)

The Recent File command lists up to the last four files that you opened. The file you select is automatically opened.


Exit command
Exit (File Menu)

The Exit command exits the Timing Analyzer. If you have any unsaved open reports or macros, the Timing Analyzer displays a prompt box so you can save them.

Prompt Box

Yes

Exits the prompt box and displays the Save As dialog box.

No

Exits the Timing Analyzer without saving the report.

Cancel

Cancels the exit operation.

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See also

Exit (Command Line)

Save

Saving a Report


Cut command
Cut (Edit Menu)

The Cut command functions like the standard Cut command. Selecting this command performs the same function as clicking the Cut button.

________

See also

Toolbar


Copy command
Copy (Edit Menu)

The Copy command functions like the standard Copy command. Selecting this command performs the same function as clicking the Copy button.

________

See also

Toolbar


Paste command
Paste (Edit Menu)

The Paste command functions like the standard Paste command. Selecting this command performs the same function as clicking the Paste button.

________

See also

Toolbar


Find command
Find (Edit Menu)

The Find command brings up the Find dialog box, which allows you to search for a text string within a Timing Analyzer report or macro. It is available for the Console and all report and macro windows.


Find Dialog Box

You open this dialog box with the Find command in the File menu.

Find What

Allows you to enter the text string to search for.

Match Case

Finds only instances that have the same case as the text string. By default, it ignores the case of the text.

Direction

Indicates the direction to search.

•	Up searches backward from the present location of the cursor to the beginning of the report. It stops at the beginning of the report.

•	Down searches forward from the present location of the cursor to the end of the report. It stops at the end of the report. Down is the default.

Find Next

Searches for the next occurrence of the specified text string.


Find Next command
Find Next (Edit Menu)

The Find Next command finds the next instance of the text string you are searching for with the same parameters as the previous search within Timing Analyzer reports or macros. It is available for the Console window.


Toolbar command
Toolbar (View Menu)

The Toolbar command controls whether or not the toolbar is displayed. It is displayed by default. The Timing Analyzer toolbar provides button access to frequently used commands in the pull-down menus. Textual labels for the buttons appear when you place the cursor over a button; this feature is called a tool tip. A longer description appears in the status bar. Every toolbar button has a tool tip. See the Toolbar section for a description of the buttons on the toolbar.


Status Bar command
Status Bar (View Menu)

The Status Bar command controls whether or not the status bar is displayed. It is displayed by default. The status bar displays a brief description of the current menu item under the cursor, which command is being executed, the open PCF file name, and Timing Analyzer messages.

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See also

Viewing Status


Console command
Console (View Menu)

The Console command displays the Console window, which records all the commands that you have used in a Timing Analyzer session.

You cannot delete text from the Console window.

You can add a command manually by typing it in the field at the bottom of the window below the Show Command Status box. Use the syntax for the command from the Command Summary section. After you enter the command and press the Return key, the command is executed and is reflected in the Console window after the previously executed commands.

If you want to re-execute a command shown in the Console window, you can use one of the following methods in the field at the bottom of the window.

•	Type an exclamation point (!) and the number of the command.

•	Type an exclamation point (!) and the first letter or first few letters of the command name.

•	Type two exclamation points (!!) to repeat the last command.

With all these methods, the Timing Analyzer starts the search from the bottom of the command list.

When you click on the Show Command Status box, the Timing Analyzer displays any responses to a command, such as errors and warning messages.

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See also

Run Macro

New Macro

Open

Save

Using the Console Window

Creating a Macro

Saving a Macro

Running a Macro

Editing a Macro


Clocks command
Clocks (View Menu)

The Clocks command creates the Clocks report, which lists the names of all clocks in the loaded design. The reported information can be saved to a file.

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See also

ShowClockNets

Save

Close

Print

Report Options

Creating a Clocks Report

Saving a Report

Closing a Report

Printing a Report

Searching for Text in a Report or Macro

Customizing a Report

Opening a Saved Report or Macro


Settings command
Settings (View Menu)

The Settings command lists the current settings of the Timing Analyzer options set with the commands in the Path Filters and Options menus in a pop-up window. You can save the settings as part of a macro to return the system to the same state as when the settings were saved or as a report. The settings apply to FPGAs and CPLDs unless specified. The default settings are as follows.

OpenPCF file_name

Displays the current physical constraints file (PCF).

Speed speed_grade

Sets the speed grade for analysis Corresponds with Speed Grade in the Options menu.

IncludeNets

If no arguments specified, includes all nets during analysis. Corresponds with Include Paths with Nets command.

ExcludeNets

If no arguments specified, includes all nets, and no nets are excluded during analysis. Corresponds with Exclude Paths with Nets command.

SelectFailingTimeConstraint True/False

If True, the Timing Analyzer reports only paths that do not meet timing constraints. The default is False. There is no direct equivalent menu command. The following menu commands are associated with SelectFailingTimeConstraint:

Report Paths in Timing Constraints

Report Paths Failing Timing Constraints

Report Paths Not Covered by Timing Constraints

IncludeNoTimingConstraint True/False

If True, the Timing Analyzer reports paths without timing constraints (in addition to paths with timing constraints). Default is False for FPGAs, True for CPLDs. There is no direct equivalent menu command. The following menu commands are associated with IncludeNoTimingConstraint:

Report Paths in Timing Constraints

Report Paths Failing Timing Constraints

Report Paths Not Covered by Timing Constraints

Report Normal|Wide

The default is Normal. A Normal report is 80 characters per line. A Wide report is 132 characters per line.

MaxPathsPerTimingConstraint number

Displays the maximum number of paths per timing constraint, which is set in the Report Options dialog box.

DelayLessThan delay_value

Optional and only supports analysis of CPLD designs. If not specified, there is "no upper limit." Change the delay_value in the Report Options dialog box.

DelayGreaterThan 0.000

Only supports analysis CPLD designs. Default is 0, which includes all paths. Change this number in the Report Options dialog box.

OnlyLongestPaths False

Only supports analysis of CPLD designs. If True, Timing Analyzer reports only the path with the longest delay, if there is more than one path between two end points. Change this setting in the Report Options dialog box.

SortOn Ascend

Only supports analysis of CPLD designs. Specifies how paths are sorted when reported. Corresponds with the Sort On pull-down list box in the Report Options dialog box.

DefineEndpoints ToAll

Corresponds with the Select Destinations command.

DefineEndpoints FromAll

Corresponds with the Select Sources command.

OmitUserConstraints False

Applies only to FPGAs. If set to True, disables timing constraints in "USER" section of PCF. If set to False, enables timing constraints in the "USER" section. Select this radio button in the Disable Timing Constraints dialog box.

DropTimingConstraint

Corresponds with the Disable Timing Constraints command.

SetForce Off

Corresponds with the SetForce command. When set to Off, informational, confirmational, and error messages are displayed in the Console window.

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See also

ShowSettings

Viewing Settings

Creating a Settings Report

Saving a Macro


Font command
Font (View Menu)

This command specifies the font type and font size for the text displayed in clocks, settings, and report windows. This command opens the font dialog box in which you can set these values.


Timing Constraints Submenu
Timing Constraints Submenu (Analyze Menu)

Timing Constraints is a submenu in the Analyze menu that contains the following commands. These commands allow you to specify how the Timing Analyzer generates the Timing Constraints Analysis (TWR) report:

•	Report Paths in Timing Constraints

•	Report Paths Failing Timing Constraints

•	Report Paths Not Covered by Timing Constraints

You can also access the functionality of these commands by clicking the corresponding Analyze Timing Constraints button in the Toolbar.

In addition to the above commands, you can use the following path filter commands to modify the scope of the Timing Constraints Analysis report.

•	Disable Timing Constraints

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing

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See also

AnalyzeTimingConstraints

Save

Close

Print

Report Options

Creating a Timing Constraints Analysis Report

Saving a Report

Closing a Report

Printing a Report

Searching for Text in a Report or Macro

Customizing a Report

Opening a Saved Report or Macro

Toolbar


Report Paths Failing Timing Constraints command
Report Paths in Timing Constraints (Analyze Menu)

This command is located in the Timing Constraints submenu in the Analyze menu. It generates a Timing Constraints Analysis report for all paths covered by timing constraints. However, the number of paths reported is affected by the Limit Report To setting in the Report Options dialog box. Selecting the Report Paths in Timing Constraints command performs the same function as clicking the Report Paths in Timing Constraints button in the Toolbar.

The Report Paths in Timing Constraints command has an interrupt function when analyzing FPGA designs. When this command is selected, a Timing Analysis in Progress box appears with an Abort button. Clicking this button or pressing Esc or the Enter/Return key aborts the analysis and data is not displayed.

When you invoke most Timing Analyzer menu commands, a corresponding macro command is issued and appears in the Console window. However, when you invoke the Report Paths in Timing Constraints command, the following macro commands are issued:

SelectFailingTimingConstraint False

IncludeNoTimingConstraint False

AnalyzeTimingConstraints

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See also

Report Paths Failing Timing Constraints

Report Paths Not Covered by Timing Constraints

Disable Timing Constraints


Report Paths Failing Timing Constraints command
Report Paths Failing Timing Constraints (Analyze Menu)

This command is located in the Timing Constraints submenu in the Analyze menu. It generates a Timing Constraints Analysis report for only the paths that do not meet the timing constraints. However, the number of paths reported is affected by the Limit Report To setting in the Report Options dialog box. Selecting the Report Paths Failing Timing Constraints command performs the same function as clicking the Report Paths Failing Timing Constraints button in the Toolbar.

The Report Paths Failing Timing Constraints command has an interrupt function when analyzing FPGA designs. When this command is selected, a Timing Analysis in Progress box appears with an Abort button. Clicking this button or pressing Esc or the Enter/Return key aborts the analysis and data is not displayed.

When you invoke most Timing Analyzer menu commands, a corresponding macro command is issued and appears in the Console window. However, when you invoke the Report Paths Failing Timing Constraints command, the following macro commands are issued:

SelectFailingTimingConstraint True

IncludeNoTimingConstraint False

AnalyzeTimingConstraints

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See also

Report Paths in Timing Constraints

Report Paths Not Covered by Timing Constraints

Disable Timing Constraints


Report Paths Not Covered by Timing Constraints command
Report Paths Not Covered by Timing Constraints (Analyze Menu)

This command is located in the Timing Constraints submenu in the Analyze menu. It generates a Timing Constraints Analysis report for paths covered by timing constraints and for paths not covered by timing constraints. However, the number of paths reported is affected by the Limit Report To setting in the Report Options dialog box. Selecting the Report Paths Not Covered by Timing Constraints command performs the same function as clicking the Report Paths Not Covered by Timing Constraints button in the Toolbar.

The Report Paths Not Covered by Timing Constraints command has an interrupt function when analyzing FPGA designs. When this command is selected, a Timing Analysis in Progress box appears with an Abort button. Clicking this button or pressing Esc or the Enter/Return key aborts the analysis and data is not displayed.

When you invoke most Timing Analyzer menu commands, a corresponding macro command is issued and appears in the Console window. However, when you invoke the Report Paths Not Covered by Timing Constraints command, the following macro commands are issued:

SelectFailingTimingConstraint False

IncludeNoTimingConstraint True

AnalyzeTimingConstraints

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See also

Report Paths in Timing Constraints

Report Paths Failing Timing Constraints

Disable Timing Constraints


Advanced Design command
Advanced Design (Analyze Menu)

The Advanced Design command generates the Advanced Design Analysis report, which provides a set of summary statistics for the paths from the timing requirements specified for analysis. This report is essentially an error report that displays a summary header for each constraint whether it passes or not and lists paths in error for constraints that are violated.

For FPGAs, this report displays the results of analyzing the constraints specified in the constraints file. If no constraints are specified, this report displays the maximum clock frequencies for all clocks in the design and the worst-case timing for all clock paths.

For CPLDs, this report displays all external pad-to-pad (tPD), clock-pad-to-output pad (tCO), setup-to-clock-at-the-pad (tSU), and internal clock-to-setup (tCYC) delays.

Filters from the Timing Constraints Filters and Common Filters submenus are applied during analysis. Selecting this command performs the same function as clicking the Advanced Design button.

This command has an interrupt function when analyzing FPGA designs. When the Advanced Design command is selected, a Timing Analysis in Progress box appears with an Abort button. Clicking this button or pressing Esc or the Enter/Return key aborts the analysis and data is not displayed.

You can use the following path filtering commands to modify the scope of this report.

•	Disable Timing Constraints

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing

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See also

AnalyzeAdvancedDesign

Report Options

Creating an Advanced Design Analysis Report

Searching for Text in a Report or Macro

Customizing a Report

Opening a Saved Report or Macro

Toolbar


Custom command
Custom (Analyze Menu)

The Custom command generates the Custom Analysis report, which contains a detailed analysis of all specified paths. Filters from the Custom Filters and Common Filters submenus are applied during analysis. Selecting this command performs the same function as clicking the Custom Analysis button.

This command has an interrupt function when analyzing FPGA designs. When the Custom command is selected, a Timing Analysis in Progress box appears with an Abort button. Clicking this button or pressing Esc or the Enter/Return key aborts the analysis and data is not displayed.

You can use the following path filtering commands to modify the scope of this report.

•	Select Sources

•	Select Destinations

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing

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See also

AnalyzeCustom

Save

Close

Print

Report Options

Creating a Custom Analysis Report

Saving a Report

Closing a Report

Printing a Report

Searching for Text in a Report or Macro

Customizing a Report

Opening a Saved Report or Macro

Toolbar


Query command
Query (Analyze Menu)

The Query command displays information about the timing of particular nets or members of a time group. It displays the Query dialog box.

Note:  This command does not support CPLD designs and is disabled if a CPLD design is open.


Query Dialog Box

Use this dialog box for the following.

Querying for Information

You open this dialog box with the Query command in the Analyze menu.

Nets/TimeGroups

Determines the information displayed, depending on which button is selected. Nets displays timing information of particular nets in the generated Query Nets Report. TimeGroups displays only timing information on members of a time group in the generated Query TimeGroups Report.

Filter

Consists of two parts, the Delay Greater Than field and a field in which to type in a filter. Both limit the elements displayed in the Available Nets/TimeGroups list box to those you specify. You can include a "?" or an "*" wildcard in the filter. The "?" represents a single character; the "*" represents zero or more characters. The filter display alternates between Nets and TimeGroups with the button you select.

Delay Greater Than

Enter a nanosecond value that corresponds with the minimum delay. This field is enabled only when Nets is selected.

Apply

Executes the filter that you have entered in the Filter box and displays the subset in the Available Nets/TimeGroups list box.

Reset

Deletes the filter and redisplays all the nets or time groups in the Available Nets/TimeGroups list box.

Available Nets/TimeGroups

Displays all the available net or timing group elements on which you can obtain information.

Selected Nets/TimeGroups

Displays the net or timing group elements that you selected.

Add (>)

Moves selected elements from the Available Nets/TimeGroups list box to the Selected Nets/TimeGroups list box.

Add All (>>)

Moves all the listed elements from the Available Nets/TimeGroups list box to the Selected Nets/TimeGroups list box.

Remove (<)

Moves selected elements from the Selected Nets/TimeGroups list box to the Available Nets/TimeGroups list box.

Remove All (<<)

Moves all listed elements from the Selected Nets/TimeGroups list box to the Available Nets/TimeGroups list box.

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See also

Query


Timing Constraint Filters submenu command
Timing Constraint Filters Submenu (Path Filters Menu)

This submenu contains the Disable Timing Constraints command, which allows you to specify paths to exclude from the Timing Constraints Analysis report.


Disable Timing Constraints command
Disable Timing Constraints (Path Filters Menu)

The Disable Timing Constraints command omits selected timing constraints from analysis. The full text of each timing constraint is displayed in the Disable Timing Constraints dialog box for FPGAs. The timing constraint name is displayed for CPLDs.

Use this path filtering command in conjunction with both the Timing Constraints Analysis report, which compares the implementation of the design to the constraints, and with the Advanced Design Analysis report, which provides a set of summary statistics for the paths from the timing requirements specified for analysis.


Diable Timing Constraints Dialog Box
Disable Timing Constraints Dialog Box

You open this dialog box with the Disable Timing Constraints command in the Path Filters menu.

Include PCF Entered Constraints

This radio button is automatically selected because the Timing Analyzer, by default, analyzes all constraints. This option enables all of the timing constraints from the "USER" section of the Physical Constraints File (PCF). The "USER" section of the PCF file consists of the constraints entered into the PCF file after the "SCHEMATIC END" statement. The order of the timing constraints in the PCF file is reflected by the Timing Analyzer. This button is only available for FPGAs. CPLD timing constraint information is contained in the design file (VM6) itself.

Omit PCF Entered Constraints

This radio button disables all of the timing constraints from the "USER" section of the Physical Constraints File (PCF). This button is only available for FPGAs.

Filter

Limits the constraints displayed in the Enabled Constraints list box to those you specify. You can include a "?" or an "*" wildcard in the component name for the filter to use in searches. The "?" represents a single character; the "*" represents zero or more characters.

Apply

Executes the filter indicated in the Filter for Enabled Timing Constraints field and displays the subset in the Enabled Constraints list box. More than one filter can be applied between Resets.

Reset

Deletes the filter and redisplays all the enabled timing constraints in the Enabled Constraints list box. Applies only to the Filter for Enabled Timing Constraints and filtered Enabled Constraints list box.

Enabled Constraints

Lists the timing constraints to be included in the timing analysis, except those specified in the Filter for Enabled Timing Constraints field. If you do not specify a filter, it lists all the timing constraints in the design.

Disabled Constraints

Lists all the timing constraints to be ignored in the current timing analysis.

Add (>)

Moves the selected timing constraint from the Enabled Constraints list box to the Disabled Constraints list box.

Add All (>>)

Moves all listed timing constraints from the Enabled Constraints list box to the Disabled Constraints list box.

Remove (<)

Moves the selected timing constraint in the Disabled Constraints list box to the Enabled Constraints list box.

Remove All (<<)

Moves all listed timing constraints in the Disabled Constraints list box to the Enabled Constraints list box.

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See also

DropTimingConstraint

OmitUserConstraints

Report Paths in Timing Constraints

Report Paths Failing Timing Constraints

Report Paths Not Covered by Timing Constraints


Custom Filters submenu
Custom Filters Submenu (Path Filters Menu)

By default the Timing Analyzer analyzes all paths during timing analysis. The Custom Filters submenu contains two commands that allow you to specify which paths are analyzed.

•	Select Sources

•	Select Destinations

These commands apply to the Custom command in the Analyze menu that produces the Custom Analysis report.


Select Sources command
Select Sources (Path Filters Menu)

The Select Sources command defines the starting points of the paths you want to analyze. It appears in the Custom Filters submenu. This command displays the Select Sources dialog box.

Use this path filtering command in conjunction with the Custom Analysis report, which contains detailed timing information for all paths in the design.


Select Sources Dialog Box

Use this dialog box for the following.

Selecting Sources

You open this dialog box with the Select Sources command in the Path Filters menu.

Source Element Type

FPGA source types: flip-flops, pads, nets, pins, CLBs, RAMs, latches, clocks, or timegroups. CPLD source types: flip-flops, pads, nets, macrocells, or clocks. The default is flip-flops.

If an element type is not used in the design, the type will not appear in the pull-down list.

Clock Edge

Determines whether the source is a clock's rising or falling edge, or either edge. This option is available only for FPGAs when you select Clocks in the Source Element Type field.

Filter

Limits the elements displayed in the Source Element list box to those you specify. The Element changes with the element you select in the Source Element Type. You can include a "?" or an "*" wildcard in the source name for the filter to use in searches. The "?" represents a single character; the "*" represents zero or more characters.

Apply

Executes the filter in the Filter field and displays the subset in the Source Element list box.

Reset

Deletes the filter and redisplays all the sources of the specified type in the Source Element list box.

Source Element

Lists all the individual sources that you specify in the Source Element Type field. You can display a subset by applying a filter in the Filter field.

The Select Sources dialog box utilizes a special way of representing nets in the Source Element and Selected Sources list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Source Flip-Flops list box and move it to the Selected Sources list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flop nets are selected. You get the same result if you individually move all the Flip-Flop nets from the Source Flip-Flops list box to the Selected Sources list box.

Selected Sources

Displays all the individual sources that you selected for the specified source type.

Add (>)

Moves the selected elements from the Source Element list box to the Selected Sources list box.

Add All (>>)

Moves all the listed elements from the Source Element list box to the Selected Sources list box.

Remove (<)

Moves the selected elements from the Selected Sources list box to the Source Element list box.

Remove All (<<)

Moves all listed elements from the Selected Sources list box to the Source Element list box.

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See also

DefineEndPoints

Select Destinations

Selecting Destinations


Select Destinations command
Select Destinations (Path Filters Menu)

The Select Destinations command defines the ending points of the paths you want to analyze. It appears in the Custom Filters submenu. This command displays the Select Destinations dialog box.

Use this path filtering command in conjunction with the following reports:

•	Advanced Design Analysis report, indicates overall design performance

•	Custom Analysis report, contains detailed timing information for all paths in the design


Select Destinations Dialog Box

Use this dialog box for the following.

Selecting Destinations

You open this dialog box with the Select Destinations command in the Path Filters menu.

Destination Element Type

FPGA destination types: flip-flops, pads, nets, pins, CLBs, RAMs, latches, clocks, or timegroups. CPLD destination types: flip-flops, pads, nets, macrocells, or clocks. The default is flip-flops.

If an element type is not used in the design, the type will not appear in the pull-down list.

Clock Edge

Determines whether the destination is a clock's rising or falling edge, or either edge. This option is available only for FPGAs when you select Clocks in the Destination Element Type field.

Filter

Limits the destination to a particular element or elements within the specified category and displays them in the Destination Element list box. The Element changes with the element you select in the Destination Element Type. You can include a "?" or an "*" wildcard in the element type for the filter to use in searches. The "?" represents a single character; the "*" represents zero or more characters.

Apply

Executes the filter in the Filter field and displays the subset in the Destination Element list box.

Reset

Deletes the filter and redisplays all the element destinations in the Destination Element list box.

Destination Element List Box

Lists all the individual destinations that you specify in the Destination Element Type field. You can display a subset by applying a filter in the Filter field.

The Select Destinations dialog box utilizes a special way of representing nets in the Destination Element and Selected Destinations list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Destination Flip-Flops list box and move it to the Selected Destinations list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flop nets are selected. You get the same result if you individually move all the Flip-Flop nets from the Destination Flip-Flops list box to the Selected Destinations list box.

Selected Destinations

Displays the individual destinations that you selected.

Add (>)

Moves selected elements from the Destination Element list box to the Selected Destinations list box.

Add All (>>)

Moves all the listed elements from the Destination Element list box to the Selected Destinations list box.

Remove (<)

Removes the selected elements from the Selected Destinations list box.

Remove All (<<)

Removes all listed elements from the Selected Destinations list box.

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See also

DefineEndPoints

Select Sources

Selecting Sources


Common Filters submenu
Common Filters Submenu (Path Filters Menu)

The following three commands in the Common Filters submenu use filters to specify the scope of analysis.

•	Include Paths with Nets

•	Exclude Paths with Nets

•	Control Path Tracing


Include Paths with Nets command
Include Paths with Nets (Path Filters Menu)

The Include Paths with Nets command limits analysis to paths that contain specified nets. If a net is not selected, paths through that net are not analyzed. However, if no nets are selected, which is the default, all nets, except those you exclude with other filters and commands, are analyzed. This command appears in the Path Filters Menu, Common Filters submenu and displays the Include Paths with Nets dialog box.

Use this path filtering command in conjunction with any of the following reports.

•	Timing Constraints Analysis, which compares the implementation of the design to the constraints

•	Advanced Design Analysis, which indicates overall design performance

•	Custom Analysis, which contains detailed timing information for all paths in the design


Include Paths with Nets Dialog Box

Use this dialog box for the following.

Including Paths with Nets

You open this dialog box with the Include Paths with Nets command in the Path Filters menu.

Filter

Limits the nets displayed in the Available Nets list box to those you specify. You can include a "?" or an "*" wildcard in the net name for the filter to use in searches. The "?" represents a single character; the "*" represents zero or more characters.

Apply

Executes the filter in the Filter field, which hides all nets in the Available Nets list box that do not match the filter.

Reset

Deletes the filter and displays all nets, except those that have been moved to the Selected Nets list box, in the Available Nets list box.

Available Nets

Lists the nets to be excluded from timing analysis, except those hidden by applying a filter in the Filter or those moved to the Selected Nets list box. If no nets are moved to the Selected Nets list box, which is the default, all nets except those you include with other filters or commands are analyzed.

Selected Nets

Lists the nets to be included in timing analysis.

Add (>)

Moves the selected nets from the Available Nets list box to the Selected Nets list box.

Add All (>>)

Moves all the listed nets from the Available Nets list box to the Selected Nets list box.

Remove (<)

Moves the selected nets from the Selected Nets list box to the Available Nets list box.

Remove All (<<)

Moves all listed nets from the Selected Nets list box to the Available Nets list box.

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See also

IncludeNets

Exclude Paths with Nets

Excluding Paths with Nets


Exclude Paths with Nets command
Exclude Paths with Nets (Path Filters Menu)

The Exclude Paths with Nets command excludes paths containing specified nets from timing analysis, regardless of which paths are specified in the Include Paths with Nets command or other filters. If a net is selected, paths through that net are not analyzed. The default does not exclude any nets from analysis. This command appears in the Path Filters Menu, Common Filters submenu and displays the Exclude Paths with Nets dialog box.

Use this path filtering command in conjunction with any of the following reports.

•	Timing Constraints Analysis, which compares the implementation of the design to the constraints

•	Advanced Design Analysis, which indicates overall design performance

•	Custom Analysis, which contains detailed timing information for all paths in the design


Exclude Paths with Nets Dialog Box

Use this dialog box for the following.

Excluding Paths with Nets

You open this dialog box with the Exclude Paths with Nets command in the Path Filters menu.

Filter

Limits the nets displayed in the Available Nets list box to those you specify. You can include a "?" or an "*" wildcard in the net name for the filter to use in searches. The "?" represents a single character; the "*" represents zero or more characters.

Apply

Executes the filter in the Filter field, which hides all nets in the Available Nets list box that do not match the filter.

Reset

Deletes the filter and displays all the nets in the Available Nets list box, except those that have been moved to the Selected Nets list box.

Available Nets

Lists the nets that are available to be excluded from timing analysis. These are all the nets in the design except those hidden by applying a filter in the Filter field or those moved to the Selected Nets list box.

Selected Nets

Lists the nets to be excluded from the timing analysis.

Add (>)

Moves the selected net from the Available Nets list box to the Selected Nets list box.

Add All (>>)

Moves all the listed nets from the Available Nets list box to the Selected Nets list box.

Remove (<)

Moves the selected net from the Selected Nets list box to the Available Nets list box.

Remove All (<<)

Moves all listed nets from the Selected Nets list box to the Available Nets list box.

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See also

ExcludeNets

Include Paths with Nets

Including Paths with Nets


Control Path Tracing command
Control Path Tracing (Path Filters Menu)

The Control Path Tracing command enables or disables path analysis through delay path types for specific components, such as latches, RAMs, tristate buffers, input and output pins, components, and Set/Reset logic. Some of these paths may be irrelevant to your analysis. This command appears in the Common Filters submenu.

Note:  This command applies only to FPGAs; it is disabled if a CPLD design (.vm6) is open. (CPLD timing analysis ignores paths through Set/Reset logic and breaks paths at bidirectional I/O pins.)

Use this path filtering command in conjunction with any of the following reports.

•	Timing Constraints Analysis, which compares the implementation of the design to the constraints

•	Advanced Design Analysis, which indicates overall design performance

•	Custom Analysis, which contains detailed timing information for all paths in the design

This command displays the Control Path Tracing dialog box.


Control Path Tracing Dialog Box

Use this dialog box for the following.

Controlling Path Tracing

You open this dialog box with the Control Path Tracing command in the Path Filters menu.

Path Type

Specifies Timing Analyzer path tracing. The paths can be the following.

•	Asynchronous Set/Reset to Output enables path tracing through CLB flip-flop asynchronous Set or Reset outputs. By default, the Timing Analyzer does not analyze these paths.

•	Data to Output for Transparent Latch enables path tracing from the latch D input to the Q output. By default, the Timing Analyzer does not analyze these paths.

•	RAM Data to Output enables path tracing through the data inputs of a CLB RAM. By default, the Timing Analyzer does not analyze these paths.

•	RAM WE (Write Enable) to Output disables path tracing through the write-enable input of a CLB RAM. By default, the Timing Analyzer analyzes these paths.

•	TBUF Tristate Control to Output disables path tracing of paths that pass through a T pin to the O pin. By default, the Timing Analyzer analyzes these paths.

•	TBUF Input to Output disables path tracing from the input pin to the output pin of a TBUF. By default, the Timing Analyzer analyzes these paths.

•	I/O Pad to Input disables path tracing from the pad pin to the input pin of an IOB. By default, the Timing Analyzer analyzes these paths.

•	I/O Output to Pad disables path tracing from the output pin of an IOB to the pad pin. By default, the Timing Analyzer analyzes these paths.

•	I/O Tristate Control to Pad disables path tracing from the tristate control pin of an IOB to the pad, or if the architecture supports it, the path through the data input to output of the tristate enable latch. By default, the Timing Analyzer analyzes these paths.

•	Bidirectional Tristate I/O Output to Input disables path tracing of paths that pass from the IOB O pin to the pad and back into the chip through the IOB I pin. By default, the Timing Analyzer analyzes these paths, but is disabled for tristate IOBs.

If you select a path type from the Path Type pull-down list box, the Timing Analyzer displays all components that use that path type in the Enabled Components or Disabled Components list box, corresponding with the path type default. The path type default is the state when you initially open a design or use the Reset All Path Filters command as shown in the "Control Path Tracing Path Types" table.

In the following table, the Abbreviation column lists path type abbreviations that appear in the Physical Constraints File (PCF) or are used in keyboard commands. The Path Type column describes the path type. The Default column shows the default state of the path type.

Control Path Tracing Path Types

Abbreviation	Path Type	Default
reg_sr_q	Asynchronous Set/Reset to output	Disabled
lat_d_q	Data to output for transparent latch	Disabled
ram_d_o	RAM data to output	Disabled
ram_we_o	RAM WE to output	Enabled
tbuf_t_o	TBUF tristate control to output	Enabled
tbuf_i_o	TBUF input to output	Enabled
io_pad_i	I/O pad to input	Enabled
io_t_pad	I/O tristate control to pad	Enabled
io_o_i	Bidirectional tristate I/O output to input	Enabled
io_o_pad	I/O output to pad	Enabled
Filter

A filter entered in this field applies to the list of components for the default state (enabled or disabled) of the selected path type. Applying a filter produces a "filtered" list. You can include a "?" or an "*" wildcard in the filter. The "?" represents a single character; the "*" represents zero or more characters.

If the default for the selected path type is enabled, the filter is located above the Enabled Components list box and the filter applies to that list box. If the default for the selected path type is disabled, the filter is located above the Disabled Components list box and the filter applies to that list box.

Apply

Removes all components that do not match the filter from the list box located below the filter.

Reset

Clears the filter and displays all components in the list box located below the filter except those in the other list box.

Enabled Components

If you have not applied a filter, it lists all the components for which tracing of the selected path type is enabled. If you applied a filter, this filtered list displays components that have path tracing enabled for the selected path type. However, some of the enabled components may have been hidden by applying a filter.

Disabled Components

If you have not applied a filter, it lists all the components for which tracing of the selected path type is disabled. If you have applied a filter, this filtered list displays components that have path tracing disabled for the selected path type. However, some of the disabled components may have been hidden by applying a filter.

Add (>)

Moves the selected component from the Enabled Components list box to the Disabled Components list box.

Add All (>>)

Moves all the listed components from the Enabled Components list box to the Disabled Components list box.

Remove (<)

Moves the selected component from the Disabled Components list box to the Enabled Components list box.

Remove All (<<)

Moves all listed components from the Disabled Components list box to the Enabled Components list box.

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See also

ControlPathTracing


Reset All Path Filters command
Reset All Path Filters (Path Filters Menu)

The Reset All Path Filters command resets path filtering commands to the default settings. To display the path filtering command settings, see the Settings command.

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See also

ResetAllPathFilters

Resetting All Path Filters


Speed Grade command
Speed Grade (Options Menu)

The Speed Grade command changes the device speed grade for analysis only. Changing the speed grade helps determine if you need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints.

The speed grade is set in the design file, NCD for FPGAs or VM6 for CPLDs. Using the Speed Grade command does not affect the speed grade set in the NCD or VM6 file.

Changing the speed grade may affect the worst case and range of values available in the Prorating Options dialog box

This command displays the Speed Grade dialog box.


Speed Grade Dialog Box

Use this dialog box for the following.

Viewing Timing Analyzer Settings

Changing Speed Grade

You open this dialog box with the Speed Grade command in the Options menu.

Speed Grade

Lists the available speed grades for the target device. For families that support minimum speed grades, a Min selection is available in the Speed Grade menu.

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See also

Speed

Settings


Prorating Options command
Prorating Options (Options Menu)

The Prorating Options command controls voltage and temperature prorating. The command is only enabled when temperature or voltage prorating data is available for the current device and speed grade.

This command displays the Prorating Options dialog box. The actual values for Worst Case and ranges are obtained from the speeds file at run time.


Prorating Options Dialog Box

You open this dialog box with the Prorating Options command in the Options menu.

Voltage

Choose between the Worst Case value or setting a range of values.

Temperature

Choose between the Worst Case value or setting a range of values. The temperature is given in degrees Celsius.

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See also

ProratingOptions


Report Options command
Report Options (Options Menu)

The Report Options command determines the appearance of a report and the information that it contains. It displays the Report Options dialog box.


Report Options Dialog Box

Use this dialog box for the following.

Customizing a Report

Viewing Timing Analyzer Settings

You open this dialog box with the Report Options command in the Options menu.

The Timing Analyzer has three appearance formats, summary, default, and wide. The default report displays a detailed list of path delays.

Summary Only

Generates a summary report containing only the path source and end point. This report lists one delay path per line and does not display cumulative delays through CLBs. Applies only to FPGAs.

No Limit

Generates a report containing an unlimited number of paths reported per timing constraint.

Limit Report To

Sets the limit for the number of paths reported per timing constraint. This option can be useful, because it limits the size of report files.

Wide Report

Creates a report formatted into 132 characters per line, which prevents long component and net names from being truncated. If not selected, a "normal" report (80 characters per line) is generated.

Note:  The next four options only support analysis of CPLD designs.

Report Delays Less Than

Report only those paths that have a delay less than or equal to the specified value. Not specifying a value is equivalent to "no limit" and the option is turned Off.

Report Delays Greater Than

Report only those paths that have a delay greater than or equal to the specified value. The default is 0, which reports all paths regardless of their delay.

Sort On

Specifies how paths are sorted when they are reported. Click on the down arrow and select one of the following options.

•	Ascending Delay lists paths in order from shortest to longest delays.

•	Descending Delay lists paths in order from longest to shortest delays.

•	Source Net sorts path delays by the source net name, which is useful when trying to determine the worst-case delay from a given component.

•	Destination Net sorts path delays by the destination net name, which can help determine the worst-case path to each component.

•	Source Clock Net sorts path delays by the clock name that sources the first element in a path, which separates delay information for two or more clock nets in a design.

•	Destination Clock Net sorts path delays by the clock name that sources the last element in a path.

Report Only Longest Paths Between Points

Report only the path with the longest delay if there is more than one path between two end points. By default, the Timing Analyzer reports all paths.

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See also

Report

MaxPathsPerTimingConstraint

DelayLessThan

DelayGreaterThan

OnlyLongestPaths

SortOn

Settings


Do Hold/Race Check command
Do Hold/Race Check (Options Menu)

The Do Hold/Race Check command is a check box (toggle) item in the Options menu. When enabled, it checks for race conditions and does a rigorous clock skew analysis on the design.

Note:  The command is only enabled for FPGA designs.

_______

See also

DoHoldRaceCheck


Cascade command
Cascade (Window Menu)

The Cascade command arranges the open windows diagonally down the screen so that they overlap one on top of another. After you execute the command, the active window is on top.

_______

See also

Tile


Tile command
Tile (Window Menu)

The Tile command arranges the open windows in rows across the Timing Analyzer screen. The windows are fitted into all available screen space without overlapping.

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See also

Cascade


Arrange Icons command
Arrange Icons (Window Menu)

This command arranges the icons in the Timing Analyzer main window in a row along the bottom of the window.


Recent Window command
Recent Window (Window Menu)

The Recent Window command lists the active windows, whether they are open or iconized. Select a window from the Recent Window list to expand it if it is iconized and bring it to the front view.


Help Topics command
Help Topics (Help Menu)

The Help Topics command lists the online help topics available for the Timing Analyzer. From the opening screen, you can jump to command information or step-by-step instructions for using the Timing Analyzer. Select Help Topics from the Help Menu whenever you want to return to the Help topic list.

Pressing the F1 key is the same as selecting the Help Topics command, if no dialog boxes are displayed.

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See also

Toolbar


Online Documentation command
Online Documentation (Help Menu)

Use this command to open the software manuals in the default Web browser.


About Timing Analyzer command
About Timing Analyzer (Help Menu)

The About Timing Analyzer command displays a pop-up window that includes the software version number, the Timing Analyzer specific graphic icon, and copyright. Selecting this command performs the same function as clicking the About button.


Toolbar

The toolbar provides convenient access to frequently used commands. Click once on a toolbar button to execute a command. The following section briefly describes each toolbar button and, where appropriate, provides a link to the corresponding menu command.

When you position the mouse pointer over a toolbar button, a short description, called a tool tip, appears next to the button. A longer description appears in the status bar at the bottom of the main window.

Toolbar Buttons

New Macro opens a new Timing Analyzer macro document window.

Open Design opens an existing design for timing analysis.

Save saves the active macro or report window to a specified file.

Run Macro runs an existing macro, which you open with the Open command on the File menu. It is enabled when a macro file is active.

Print displays the Print dialog box and sends the contents displayed in the active window to the default printer. You can print Timing Analyzer macros, reports, settings, clocks, and so forth.

Cut cuts the selected text from a macro window and moves the text to the clipboard. It is enabled when a window is open and text is selected. (The Console and report windows are read-only.)

Copy copies the selected text in a macro or report window to the clipboard, so that you can paste it into a macro window to form a new macro or edit an existing one. It is enabled when a macro or report window is active and text is selected.

Paste replaces the currently selected text in the macro window with the contents of the clipboard. If no text is selected, the contents of the clipboard are inserted at the cursor position in the macro window.

Report Paths in Timing Constraints generates a Timing Constraints Analysis report for all the paths covered by the timing constraints.

Report Paths Failing Timing Constraints generates the Timing Analysis report for only the paths that do not meet the timing constraints.

Report Paths Not Covered by Timing Constraints generates the Timing Analysis report for paths covered by timing constraints and for paths not covered by timing constraints.

Advanced Design generates the Advanced Design Analysis report, which indicates overall design performance.

Custom generates the Custom Analysis report, which contains worst-case path delays for all paths in the design.

About Timing Analyzer displays program and copyright information about the Timing Analyzer.

Help activates context-sensitive help. After clicking this button, select a menu item or toolbar button for which you want help.


Command Line Conventions

You can enter console commands in the command line of the Console window as an alternative to using menu commands. Console commands do not display the dialog boxes that menu commands invoke.

The following is a summary of the syntax used for the console commands.

•	When an option occurs without parentheses "()" next to the command name in the syntax, it is required. When it appears in square brackets "[ ]," it is optional.

•	When two or more options occur between braces "{ }," the options must be entered with the command. If the options are separated by a vertical bar "|," you must choose one of the possible parameters. If one term is divided into a subset of parameters that can be entered separately or together, each subparameter occurs between square brackets.


Command Summary

Enter any of the following commands from the Timing Analyzer Console window. These commands are not case sensitive.

AnalyzeAdvancedDesign	Generates report indicating overall design performance
AnalyzeCustom	Generates report containing worst-case path delays for paths in design, except those suppressed by filtering commands
AnalyzeTimingConstraints	Generates report indicating whether design meets timing constraints
ControlPathTracing	Controls path tracing through components
DefineEndPoints	Defines path starting and ending points
DelayGreaterThan	Only supports analysis of CPLD designs. Specifies minimum delay
DelayLessThan	Optional and only supports analysis of CPLD designs. Specifies maximum delay
DoHoldRaceCheck	Checks for race conditions and does a rigorous clock skew analysis on the design
DropTimingConstraint	Omits specified timing constraints from analysis
ExcludeNets	Prohibits analysis of specified nets
Exit	Exits the Timing Analyzer
IncludeNets	Limits analysis to paths containing specified nets
IncludeNoTimingConstraint	Forces reporting of paths with no timing constraints
MaxPathsPerTimingConstraint	Limits number of paths reported per timing constraint
OmitUserConstraints	Enables or disables user-specified constraints in the PCF file
OnlyLongestPaths	Only supports analysis of CPLD designs. Reports only path with longest delay for each constraint
OpenDesign	Loads a design for timing analysis
OpenPCF	Opens an existing physical constraints file
ProratingOptions	Controls voltage and temperature prorating
Query	Displays information about groups of elements
Report	Determines format of reports
ResetAllPathFilters	Causes path filtering commands to revert to defaults
RunMacro	Runs macro
SelectFailingTimingConstraint	Limits reporting to paths that do not meet timing constraints
SetForce	Suppresses messages when macro is run
ShowClockNets	Show or hide the window showing the clock nets
ShowSettings	Show or hide the window displaying the current settings of filters and command option settings
SortOn	Only supports analysis of CPLD designs. Defines order in which paths are reported
Speed	Selects speed grade for analysis


AnalyzeAdvancedDesign command
AnalyzeAdvancedDesign (Command Line)

The AnalyzeAdvancedDesign command generates an Advanced Design Analysis report. The report appears in a pop-up window.

For FPGAs, this report displays the results of analyzing the constraints specified in the constraints file. If no constraints are specified, this report displays the maximum clock frequencies for all clocks in the design and the worst-case timing for all clock paths. For CPLDs, this report lists all external Pad to Pad (tPD), Clock Pad to Output Pad (tCO), Setup to Clock at the Pad (tSU) and delays, and internal Clock to Setup (tCYC) delays.

This command is equivalent to the Advanced Design command on the Analyze menu.

Syntax	AnalyzeAdvancedDesign [save file_name.twr]
Options	Save indicates that you can optionally save the Advanced Design Analysis report in a file. File_name is the name of the file in which the Advanced Design Analysis report is saved. The .twr extension indicates the file is in report format.
Abbreviation	aad [s file_name.twr]
Example	To create an Advanced Design Analysis report and save it analyzeadvanceddesign save postdesign.twr
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See also

Command Summary

Using the Console Window


AnalyzeCustom command
AnalyzeCustom (Command Line)

The AnalyzeCustom command creates the Custom Analysis report, a long report that displays a detailed analysis of all specified paths. The report appears in a pop-up window.

This command is equivalent to the Custom command in the Analyze menu.

Syntax	AnalyzeCustom [save file_name.twr]
Options	Save indicates that you can optionally save the Custom Analysis report in a file. File_name is the name of the file in which the Custom Analysis report is saved. The .twr extension indicates the file is in report format.
Abbreviation	ac [s file_name.twr]
Example	To create a Custom Analysis report and save it analyzecustom save xredesign.twr
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See also

Command Summary

Using the Console Window


AnalyzeTimingConstraints command
AnalyzeTimingConstraints (Command Line)

The AnalyzeTimingConstraints command generates the Timing Analysis report, which compares design performance to the timing constraints. The report appears in a pop-up window.

There is no direct equivalent menu command for AnalyzeTimingConstraints. The following three menu commands are associated with AnalyzeTimingConstraints:

•	Report Paths in Timing Constraints

•	Report Paths Failing Timing Constraints

•	Report Paths Not Covered by Timing Constraints

Syntax	AnalyzeTimingConstraints [save file_name.twr]
Options	Save indicates that you can optionally save the Timing Analysis report in a file. File_name is the name of the file in which the Timing Analysis report is saved. The .twr extension indicates the file is in report format.
Abbreviation	atc [s file_name.twr]
Example	To create a Timing Analysis report and save it analyzetimingconstraints save mercury.twr
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Command Summary

Using the Console Window


ControlPathTracing command
ControlPathTracing (Command Line)

The ControlPathTracing command controls whether the Timing Analyzer traces paths through RAMs, tristate buffers, input and output pins, components, and Set/Reset logic.

This command corresponds to the Control Path Tracing command on the Common Filters submenu of the Path Filters menu.

Syntax	ControlPathTracing {Enable|Disable} {reg_sr_q|lat_d_q|ram_d_o|ram_we_o|tbuf_t_o| tbuf_i_o|io_pad_i|io_t_pad|io_o_i|io_o_pad} component_name component_name ...
Options	reg_sr_q enables path tracing through CLB flip-flop asynchronous Set or Reset outputs. By default, this path is disabled; the Timing Analyzer does not analyze these paths. lat_d_q enables path tracing from the latch D input to the Q output. By default, this path is disabled; the Timing Analyzer does not analyze these paths. ram_d_o enables path tracing through the data inputs of a CLB RAM. By default, this path is disabled; the Timing Analyzer does not analyze these paths. ram_we_o disables path tracing through the write-enable input of a CLB RAM. By default, this path is enabled; the Timing Analyzer analyzes these paths. tbuf_t_o disables path tracing of paths that pass through a T pin to the O pin. By default, this path is enabled; the Timing Analyzer analyzes these paths. tbuf_i_o disables path tracing from the input pin to the output pin of a TBUF. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths. io_pad_i disables path tracing from the pad pin to the input pin of an IOB. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths. io_t_pad disables path tracing from the tristate control pin of an IOB to the pad, or if the architecture supports it, the path through the data input to output of the tri-state enable latch. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths. io_o_i disables path tracing of paths from the IOB O pin to the I pin. By default, this path is enabled but is disabled for tristate IOBs; the Timing Analyzer analyzes these paths. io_o_pad disables path tracing from the output pin of an IOB to the pad pin. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths. Component_name is the name(s) of the CLBs, IOBs, or TBUFs that the path goes through.
Abbreviation	cpt {Enable|Disable} {reg_sr_q|lat_d_q|ram_d_o|ram_we_o|tbuf_t_o| tbuf_i_o|io_pad_i|io_t_pad|io_o_i|io_o_pad} component_name component_name ...
Example	To disable path tracing through the write-enable input of the CLB_R4C4 RAM  controlpathtracing ram_we_o CLB_R4C4
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See also

Command Summary

Using the Console Window


DefineEndPoints command
DefineEndPoints (Command Line)

The DefineEndPoints command selects the starting points and ending points of the paths that you want to analyze.

This command corresponds to the Select Sources and the Select Destinations commands on the Path Analysis Filters submenu of the Path Filters menu.

FPGA starting and ending points are: flip-flops, pads, nets, pins, CLBs, RAMs, latches, clocks, or timegroups. CPLD starting and ending points are: flip-flops, pads, nets, macrocells, or clocks.

In the DefineEndPoints command syntax, you can enter * for pad_name, CLB_name, net_name, pin_name, flip-flop_name, clock_name, macrocell_name, RAM_name, latch_name, or timegroup_name to specify all the elements of that type.

The defaults are FromAll and ToAll.

Syntax	DefineEndPoints {FromAll|ToAll} DefineEndPoints {FromPad|ToPad} pad_name DefineEndPoints {FromCLB|ToCLB} CLB_name DefineEndPoints {FromNet|ToNet} net_name DefineEndPoints {FromPin|ToPin} pin_name DefineEndPoints {FromFF|ToFF} flip-flop_name DefineEndPoints {FromEitherEdge|ToEitherEdge} clock_name DefineEndPoints {FromRising|ToRising} clock_name DefineEndPoints {FromMacrocell | ToMacrocell} macrocell_name DefineEndPoints {FromFalling|ToFalling} clock_name DefineEndPoints {FromRAM|ToRAM} RAM_name DefineEndPoints {FromLatch|ToLatch} latch_name DefineEndPoints {FromTimeGroups|ToTimeGroups} timegroup_name
Options	FromAll selects paths that begin at any path source. ToAll selects paths that end at any path source. FromPad selects pads as starting points for the path to be analyzed. ToPad selects pads as ending points for the path to be analyzed. FromCLB selects CLBs as starting points for the path to be analyzed. ToCLB selects CLBs as ending points for the path to be analyzed. FromNet selects nets as starting points for the path to be analyzed. ToNet selects nets as ending points for the path to be analyzed. FromPin selects pins as starting points for the path to be analyzed. ToPin selects the ending points for the path to be analyzed. FromFF selects flip-flops as starting points for the path to be analyzed. ToFF selects flip-flops as ending points for the path to be analyzed. FromEitherEdge selects either clock edge as starting points for the path to be analyzed. ToEitherEdge selects either clock edge as ending points for the path to be analyzed. FromRising selects rising clock edges as starting points for the path to be analyzed. ToRising selects rising clock edges as ending points for the path to be analyzed. FromMacrocell selects macrocells as starting points for the path to analyzed. ToMacrocell selects macrocells as ending points for the path to be analyzed. FromFalling selects falling clock edges as starting points for the path to be analyzed. ToFalling selects falling clock edges as ending points for the path to be analyzed. FromRAM selects RAMs as starting points for the path to be analyzed. ToRAM selects RAMs as ending points for the path to be analyzed. FromLatch selects latches as starting points for the path to be analyzed. ToLatch selects latches as ending points for the path to be analyzed.
	FromTimeGroups selects timegroups as starting points for the path to be analyzed. ToTimeGroups selects timegroups as ending points for the path to be analyzed. Pad_name is the name of the PAD that is the starting or ending point of the path to be analyzed. CLB_name is the name of the CLB that is the starting or ending point of the path to be analyzed. Net_name is the name of the net that is the starting or ending point of the path to be analyzed. Pin_name is the name of the pin that is the starting or ending point of the path to be analyzed. Flip-Flop_name is the name of the flip-flop that is the starting or ending point of the path to be analyzed. Clock_name is the name of the clock that is the starting or ending point of the path to be analyzed. Macrocell_name is the name of the macrocell that is the starting or ending point of the path to be analyzed. RAM_name is the name of the RAM that is the starting or ending point of the path to be analyzed. Latch_name is the name of the latch that is the starting or ending point of the path to be analyzed. Timegroup_name is the name of the timegroup that is the starting or ending point of the path to be analyzed.
Abbreviations	dep {fall|tall} source_name dep {fpad|tpad} pad_name dep {fclb|tclb} CLB_name dep {fnet|tnet} net_name dep {fpin|tpin} pin_name dep {fff|tff} flip-flop_name dep {fee|tee} clock_name dep {fris|tris} clock_name dep {fmc|tmc} macrocell_name dep {ffal|tfal} clock_name dep {fram|tram} RAM_name dep {fl|tl} latch_name dep {ftg|ttg} timegroup_name
Examples	To select specific flip-flops as starting points for the paths to be analyzed defineendpoints fromff CNT3Q0 CNT3Q1
	To select specific pads as ending points for the paths to be analyzed dep topad P80 P68
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Command Summary

Using the Console Window


DelayGreaterThan command
DelayGreaterThan (Command Line)

The DelayGreaterThan command only supports analysis of CPLD designs. It specifies a minimum delay in nanoseconds. The Timing Analyzer reports only those paths that have a delay greater than or equal to the specified value. The default delay_value is 0, which reports all paths regardless of their delay.

This command corresponds to the Report Delays Greater Than field in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	DelayGreaterThan delay_value
Options	Delay_value is the minimum delay in nanoseconds.
Abbreviation	dg delay_value
Example	To report only paths that have a delay of 30 or more nanoseconds delaygreaterthan 30
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Command Summary

Using the Console Window


DelayLessThan command
DelayLessThan (Command Line)

DelayLessThan is an optional command that only supports analysis of CPLD designs. It specifies a maximum delay in nanoseconds. The Timing Analyzer reports only those paths that have a delay less than or equal to the specified value. By default, the Timing Analyzer reports all paths regardless of their delay.

This command corresponds to the Report Delays Less Than option in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	DelayLessThan delay_value
Options	Delay_value is the maximum delay in nanoseconds. It is optional. If a value is not specified, the limit is turned Off.
Abbreviation	dl delay_value
Example	To report only paths that have a delay of 30 or fewer nanoseconds  delaylessthan 30
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Command Summary

Using the Console Window


DoHoldRaceCheck command
DoHoldRaceCheck (Command Line)

DoHoldRaceCheck checks for race conditions and does a rigorous clock skew analysis on the design.

This command is only enabled for FPGA designs.

Syntax	DoHoldRaceCheck {true|false}
Options	True enables race checking and full skew analysis. False disables race checking and full skew analysis.
Abbreviation	dhrc {t|f}
Example	To enable race checking and full skew analysis doholdracecheck true
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Command Summary

Using the Console Window


DropTimingConstraint command
DropTimingConstraint (Command Line)

The DropTimingConstraint command prevents the Timing Analyzer from analyzing the specified timing constraints.

This command corresponds to the Disable Timing Constraints command on the Timing Constraint Filters submenu of the Path Filters menu.

Syntax	DropTimingConstraint [time_constraint1 time_constraint2...]
Options	Time_constraint1, time_constraint2, and so forth are the timing constraints to be ignored. Each can be either the name or the full text of the timing constraint in single quotes.
Abbreviation	dtc [time_constraint1 time_constraint2...]
Example	To prevent the Timing Analyzer from analyzing specified timing constraints droptimingconstraint TS08 TS09 TS10
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Command Summary

Using the Console Window


ExcludeNets command
ExcludeNets (Command Line)

Use the ExcludeNets command to exclude paths that contain specified nets from analysis. If a net is selected, paths through that net are not analyzed. However, if no nets are selected, which is the default, all nets, except those you exclude with other filters and commands, are analyzed.

This command corresponds to the Exclude Paths with Nets command on the Common Filters submenu of the Path Filters menu.

Syntax	ExcludeNets [net_name1 net_name2...]
Options	Net_name1, net_name2, and so forth are the names of the nets to be excluded.
Abbreviation	exnet [net_name1 net_name2...]
Example	To exclude paths containing specific nets from analysis excludenets $1N95 CNT5 CNT6 CNT7 EXT_CLK1
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Command Summary

Using the Console Window


Exit (Command Line)

The Exit command exits the Timing Analyzer.

This command is equivalent to the Exit command on the File menu.

Syntax	exit
Options
Abbreviation	e
Example	To exit the Timing Analyzer exit
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Command Summary

Using the Console Window


IncludeNets command
IncludeNets (Command Line)

Use the IncludeNets command to limit analysis to paths that contain specified nets. If a net is not selected, paths through that net are not analyzed. However, if no nets are selected, which is the default, all nets, except those you exclude with other filters and commands, are analyzed.

This command corresponds to the Include Paths with Nets command on the Common Filters submenu of the Path Filters menu.

Syntax	IncludeNets [net_name1 net_name2...]
Options	Net_name1, net_name2, and so forth are the nets to be analyzed.
Abbreviation	incnet [net_name1 net_name2...]
Example	To include only paths containing specific nets in the analysis includenets in2_1 in2_2
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Command Summary

Using the Console Window


IncludeNoTimingConstraint command
IncludeNoTimingConstraint (Command Line)

The IncludeNoTimingConstraint command includes paths without timing constraints in analysis, in addition to paths with timing constraints.

There is no direct equivalent menu command for IncludeNoTimingConstraint. The following three menu commands are associated with IncludeNoTimingConstraint:

•	Report Paths in Timing Constraints

•	Report Paths Failing Timing Constraints

•	Report Paths Not Covered by Timing Constraints

Syntax	IncludeNoTimingConstraint {true|false}
Options	True reports paths with no timing constraints (in addition to paths with timing constraints). It is the default setting when opening a CPLD design. False does not report paths with no timing constraints. This argument is the default when opening an FPGA design.
Abbreviation	intc {t|f}
Example	To include paths with no timing constraints in a report includenotimingconstraint true
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Command Summary

Using the Console Window


MaxPathsPerTimingConstraint command
MaxPathsPerTimingConstraint (Command Line)

The MaxPathsPerTimingConstraint command sets the limit for the number of paths reported per timing constraint. This option can be useful, because it limits the size of report files. For FPGAs, the default is one path per timing constraint. For CPLDs, the default is unlimited.

This command corresponds to the Maximum Paths per Timing Constraint field in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	MaxPathsPerTimingConstraint number_of_paths
Options	Number_of_paths is the maximum number of paths per timing constraint that the Timing Analyzer reports. It is optional. Not specifying a number_of_paths value turns the limit Off.
Abbreviation	mpptc number
Example	To report a maximum of 20 paths per timing constraint maxpathspertimingconstraint 20
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Command Summary

Using the Console Window


OmitUserConstraints command
OmitUserConstraints

The OmitUserConstraints command enables or disables timing constraints in the "USER" section of the PCF. The USER section is delineated by SCHEMATIC START; and SCHEMATIC END;. The order of the timing constraints in the PCF file is reflected by the Timing Analyzer. This command only supports analysis of FPGA designs.

The UCF (User Constraints File) is the file in which you specify your timing constraints. The design and UCF constraints are read by the Xilinx software tools and mapped. During mapping the logical constraints are converted to physical constraints, producing the PCF file.

This command corresponds with the Include PCF Entered User Constraints and Omit PCF Entered Constraints radio buttons in the Disable Timing Constraints dialog box. This dialog box is activated by the Disable Timing Constraints command in the Path Filters menu, Timing Constraint Filters submenu.

Syntax	OmitUserConstraints {true|false}
Options	True disables the "USER" timing constraints. False enables the "USER" timing constraints.
Abbreviation	ouc {t|f}
Example	To enable timing constraints in the "USER" section of the physical constraints file omituserconstraints false
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Command Summary

Using the Console Window


OnlyLongestPaths command
OnlyLongestPaths (Command Line)

The OnlyLongestPaths command only supports analysis of CPLD designs. It restricts the Timing Analyzer to reporting only the path with the longest delay, if there is more than one path between two end points. By default, the Timing Analyzer reports all paths.

This command corresponds to the Report Only Longest Paths Between Points check box in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	OnlyLongestPaths {true|false}
Options	True includes only the longest paths; it is the default when you generate the Advanced Design Analysis report. False includes all paths; it is the default when you generate any report except the Advanced Design Analysis report.
Abbreviation	olp {t|f}
Example	To include all paths in the timing report onlylongestpaths false
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Command Summary

Using the Console Window


OpenDesign command
OpenDesign (Command Line)

The Open Design command opens a mapped NCD (FPGA) or a completely placed and routed VM6 (CPLD) design file for timing analysis. The mapped FPGA design can be partially or completely placed, routed, or both. This command does not open a report (TWR) file.

This command corresponds to the Open Design command on the File menu.

Syntax	OpenDesign {design_name.ncd|design_name.vm6}
Options	Design_name is the NCD or VM6 file name, including the path of the directory in which it is located.
Abbreviation	od design_name.ncd
Example	To open a file for design analysis opendesign shelby.ncd
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Command Summary

Using the Console Window


OpenPCF command
OpenPCF (Command Line)

The OpenPCF command opens an existing physical constraints file (PCF).

Loading a new physical constraints file causes the Prorating Options to be reset to the values specified in the last PCF file you loaded. If the PCF file does not contain Prorating Options preferences, the worst case values are used.

This command corresponds to the Open Physical Constraints command on the File menu.

Note:  This command only applies to FPGAs.

Syntax	OpenPCF file_name.pcf
Options	File_name is the name of the PCF file
Abbreviation	op file_name.pcf
Example	To open a physical constraints file openpcf checkers.pcf
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Command Summary

Using the Console Window


ProratingOptions command
ProratingOptions (Command Line)

ProratingOptions controls temperature and voltage prorating. The command is only enabled when temperature or voltage prorating data is available for the current device and speed grade.

If no value is specified for the temperature or voltage, the prorating is set to the Worst Case value.

Syntax	ProratingOptions [Temp [degrees_celsius]] [Volts [voltage]]
Options	degrees_celsius is the temperature prorating. voltage is the voltage prorating.
Abbreviation	po [T [degrees_celsius]] [V [voltage]]
Examples	To use the worst case values for both temperature and voltage prorating po
	To set the temperature prorating to the worst case value and leave the voltage prorating unchanged po t
	To set both the temperature and voltage prorating to specific values po t 80 v 5.2
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Command Summary

Using the Console Window


Query command
Query (Command Line)

The Query command reports information about particular nets or members of a time group. It is not supported for CPLD designs. See the Query command in the Menu Commands section for details about the information reported.

This command is the same as the Query command on the Options menu.

Note:  This command only applies to FPGAs.

Syntax	query {net|timegroup} element_name
Options	Net reports information about nets. Timegroup reports information about timing groups. Element_name can be either a net name or a timing group name, depending on whether you specify the net option or the timegroup option, respectively.
Abbreviation	qy {n|tg} element_name
Examples	To report information about a particular net query net ram_d_o
	To report information about a particular timing group query timegroup 05
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Command Summary

Using the Console Window


Report command
Report (Command Line)

The Report command determines the format of the report output.

This command corresponds to the Wide Report option in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	report {wide|normal}
Options	Wide sets a format of 132 characters per line, which prevents long component and net names from being truncated. Normal, the default, displays a detailed list of path delays. The width is 80 characters per line. Because normal is the default, it does not appear as an option for the Report Options menu command.
Abbreviation	r {w|n}
Example	To set the format of the report output to wide report wide
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Command Summary

Using the Console Window


ResetAllPathFilters command
ResetAllPathFilters (Command Line)

The ResetAllPathFilters command resets the path filtering commands to the system defaults. Refer to the Settings command for a listing of these defaults.

This command is equivalent to the Reset All Path Filters command on the Path Filters menu.

Syntax	ResetAllPathFilters
Options
Abbreviation	rapf
Example	To reset the path filtering commands to the system defaults resetallpathfilters
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Command Summary

Using the Console Window


RunMacro command
RunMacro (Command Line)

The RunMacro command runs an existing macro.

Syntax	RunMacro file_name.xtm
Options	File_name is the name of the macro file.
Abbreviation	runm file_name.xtm
Example	To run the deb.xtm macro runmacro deb.xtm
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Command Summary

Using the Console Window


SelectFailingTimingConstraint command
SelectFailingTimingConstraint (Command Line)

The SelectFailingTimingConstraint command reports only the paths that do not meet timing constraints.

There is no direct equivalent menu command for SelectFailingTimingConstraint. The following three menu commands are associated with SelectFailingTimingConstraint:

•	Report Paths in Timing Constraints

•	Report Paths Failing Timing Constraints

•	Report Paths Not Covered by Timing Constraints

Syntax	SelectFailingTimingConstraint {true|false}
Options	True reports only the paths that do not meet your timing constraints within the generated report. False includes all paths. This setting is the default.
Abbreviation	sftc {t|f}
Example	To report only the paths that do not meet your timing constraints selectfailingtimingconstraint true
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Command Summary

Using the Console Window


SetForce command
SetForce (Command Line)

When you run a macro, the commands in the macro file can generate informational, confirmational, and error messages. When the SetForce command is set to On, the Timing Analyzer suppresses the warning and confirmational messages in dialog boxes. Error messages continue to appear. Macros continue to run until an error is produced. SetForce Off restores the appearance of all three types of messages to the Console window. The default is On.

This command does not have an equivalent menu command.

Syntax	SetForce {on|off}
Options	On suppresses the informational and confirmational messages. Off restores the messages.
Abbreviation	sf {on|off}
Example	To suppress the informational and confirmational messages setforce on
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Command Summary

Using the Console Window


ShowClockNets command
ShowClockNets (Command Line)

The ShowClockNets command creates the Clocks report, which lists the names of all clocks in the design. The report appears in a pop-up window.

This command is the same as the Clocks command on the View menu.

Syntax	ShowClockNets [save file_name]
Options	Save indicates that you want to save the Clocks report in a file. File_name is the name of the saved file. You can add a .twr extension to the file_name to list it under Timing Analysis Reports (*.twr) under List Files of Type in File menu command dialog boxes.
Abbreviation	scn [s file_name]
Example	To create a Clocks report and save it showclocknets save nikkoclocks.twr
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Command Summary

Using the Console Window


ShowSettings command
ShowSettings (Command Line)

The ShowSettings command creates the Settings report, which lists the current settings for Timing Analyzer options. The report appears in a pop-up window.

This command performs the same function as the Settings command on the View menu.

Syntax	ShowSettings [save file_name]
Options	Save indicates that you can optionally save the Settings report in a file. File_name is the name of the saved file. You can add an .xtm extension to the file_name to save the settings as a macro to return the system to the same state as when the settings were saved. Or you can add a .twr extension to the file_name to save the settings as a report. TWR files are listed as Timing Analysis Reports (*.twr) under List Files of Type in File menu command dialog boxes.
Abbreviation	ss [s file_name]
Example	To create a Settings report and save it showsettings save shelby2.xtm
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See also

Command Summary

Using the Console Window


SortOn command
SortOn (Command Line)

The SortOn command only supports analysis of CPLD designs. It defines the order in which the paths are reported. The default is Descend.

This command is equivalent to the Sort On field in the Report Options dialog box, which is activated by the Report Options command on the Options menu.

Syntax	SortOn {Ascend|Descend|SourceNet|DestNet| SourceClkNet|DestClkNet}
Options	Ascend lists paths in order from shortest to longest delays. Descend, the default, lists paths in order from longest to shortest delays. SourceNet sorts path delays by the source net name, which is useful when trying to determine the worst-case delay of a given net. DestNet sorts path delays by the destination net name, which can help determine the worst-case path to each net. SourceClkNet sorts path delays by the clock name that sources the first element in a path, which separates delay information for two or more clock nets in a design. DestClkNet sorts path delays by the clock name that sources the last element in a path.
Abbreviation	sort {a|d|sn|dn|scn|dcn}
Example	To sort path delays in the report by the source net name sorton sourcenet
_______

See also

Command Summary

Using the Console Window


Speed command
Speed (Command Line)

The Speed command sets the speed grade for analysis. Changing the speed grade helps determine if you need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints.

The speed grade is set in the design file, NCD for FPGAs or VM6 for CPLDs. Using this command does not affect the speed grade set in the design file.

Changing the speed grade may affect the worst case and range of values available in the Prorating Options dialog box

This command is the same as the Speed Grade command on the Options menu.

Syntax	speed speed_grade
Options	Speed_grade can be any of the speed grades available for the architecture used. You can obtain this information from the Design Manager or the Timing Analyzer's graphical interface.
Abbreviation	sp speed_grade
Example	To set the speed grade to -3 speed -3
_______

See also

Command Summary

Using the Console Window


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Resource	Description/URL
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Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm


Glossary

BEL

CLB (configurable logic block)

clock input path

clock skew

clock-to-pad path

clock-to-setup path

component

console

critical path

destination

end point

fast function block (FFB)

filter

fitting

high-density function block (HDFB)

hold time

IOB (input/output block)

macro

main window

menu bar

net

offset

pad

pad-to-pad path

pad-to-setup path

path

period

pin

primitive

race check

schematic

SDF

setup time

slack

source

static timing analysis

status bar

time group

timing constraints

toolbar

TRACE

universal interconnect matrix (UIM)

verification

VHDL


BEL (definition)
BEL

A Basic ELement. Basic Elements are the building blocks that make up a CLB or IOB—function generators, flip-flops, carry logic, and RAMs.


CLB (definition)
CLB

The CLB, or Configurable Logic Block, constitutes the basic FPGA cell. The FPGA is an array of CLBs organized in columns and rows on the silicon die. CLBs are used to implement macros and other designed functions. They provide the physical support for an implemented and downloaded design. They have inputs on each side, and this versatility makes them flexible for the mapping and partitioning of logic.


clock input path (definition)
clock input path

A clock input path is a logic transition, which when applied to a clock pin on a synchronous element, captures data. It starts at either an input or an output of the chip, but can also start at other sequential elements. A clock input path propagates through any number of levels of combinatorial logic and ends at any clock pin on a flip-flip, latch enable, or synchronous RAM. These paths do not propagate through synchronous elements. The clock input path time is the maximum time required for the signal to arrive at the clock input of the synchronous element.


clock skew (definition)
clock skew

The difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop.


clock-to-pad path (definition)
clock-to-pad path

A path starting at the Q output of a flip-flop or latch and ending at an output of the chip. It includes the clock-to-Q delay of the flip-flop and the path delay from that flip-flop to the chip output. The clock-to-pad path time is the maximum time required for the data to leave the source flip-flop, travel through logic and routing, and arrive at the output.


clock-to-setup path (definition)
clock-to-setup path

A path starting at the Q output of a flip-flop or latch and ending at an input to another flip-flop, latch, or RAM, where that pin has a setup requirement before a clocking signal. It includes the clock-to-Q delay of the source flip-flop, the path delay from that flip-flop to the destination flip-flop, and the setup requirement of the destination flip-flop. The clock-to-setup path time is the maximum time required for the data to propagate through the source flip-flop, travel through the logic and routing, and arrive at the destination before the next clock edge occurs.


component (definition)
component

A logical configuration that will, at some point, go into a physical site. Examples of components are CLBs, IOBs, tristate buffers, pull-up resistors, and oscillators.


console log (definition)
console log

Record of the commands that you invoked during a session.


critical path (definition)
critical path

The path within a design that dictates the fastest time at which an entire design can run. This path runs from the source to a sink node such that if any activity on the path is delayed by an amount t, then the entire circuit function is delayed by time t.


destination (definition)
destination

A sink node or stopping point for a timing analysis path, the data input of a synchronous element or a pad.


end_points (definition)
end point

A node which acts as either the driver to begin a path or a load to end a path.


fast function block (definition)
fast function block (FFB)

A group of macrocells in a CPLD that can process very high-speed logic.


filter (definition)
filter

A set of limitations or options applied to the timing analysis to more specifically target important items of interest.


fitting (definition)
fitting

The process of putting logic from your design into physical macrocell locations in a CPLD. Routing is performed automatically, and because of the interconnect architecture, all designs are routable.


high-density function block (definition)
high-density function block (HDFB)

A group of macrocells in a CPLD that can efficiently perform complex logic such as arithmetic operations.


hold time (definition)
hold time

The time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


IOB (definition)
IOB (input/output block)

A collection or grouping of basic elements that implement the input and output functions of FPGA and CPLD devices.


macro (definition)
macro

A macro is an ASCII file containing a sequence of Timing Analyzer keyboard commands that are executed in script form.


main window (definition)
main window

The background against which windows are displayed.


menu bar (definition)
menu bar

The area located at the top of the main window that provides access to the menus.


net (definition)
net

A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.


offset (definition)
offset

Defines the timing relationship between an external clock and its associated data-in or data-out pin.


pad (definition)
pad

The physical bonding pad on an Integrated Circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an Integrated Circuit package.


pad-to-pad path (definition)
pad-to-pad path

A path starting at an input of the chip and ending at an output of the chip. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal.


pad-to-setup path (definition)
pad-to-setup path

A path starting at an input of the chip and ending at an input to a flip-flop, latch, or RAM—wherever there is a setup time against a control signal. The pad-to-setup path time is the maximum time required for the data to enter the chip, travel through logic and routing, and arrive at the input before the clock or control signal arrives.


path (definition)
path

An ordered set of elements identifying a logic flow pathway through a circuit. A path may consist of a single net or a grouping of related nets and components. There can be multiple paths (consisting of nets and components) between the two pins. When a component is selected as part of a path, both the input pin to the component and the output pin are included in the path. A path stops when it reaches the data input of a synchronous element (flip-flop) or pad. A path usually starts at the output of a synchronous element or pad.

Paths can be defined by using timing specifications (see the "Using Timing Constraints" chapter of the Development System Reference Guide).


period (definition)
period

The time specified for a clock signal to transition from a state back to the same state. Also, a requirement placed on the clock signal that the place and route software is expected to meet. The period of the clock is affected by the amount of time it takes the output of one sequential element to pass to the next sequential element in a path.


pin (definition)
pin

A symbol pin or package pin. A package pin is a physical connector on an Integrated Circuit package that carries signals into and out of an Integrated Circuit.

A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.


primitive (definition)
primitive

A logic element that directly corresponds, or maps, to a basic element.


race check (definition)
race check

An analysis that compares the time it takes for data to propagate from a source register to a destination register with the amount of skew on the clock lines driving each register. A race condition exists if the clock skew is greater than the propagation time plus the hold time.


schematic (definition)
schematic

A hierarchical diagram representing a design in terms of user and library components.


SDF (definition)
SDF

Standard Delay Format, which is an industry-standard file format for specifying timing information. It is often used for simulation.


sequential element (definition)
sequential element

A flip-flop, synchronous RAM, or Latch.


setup time (definition)
setup time

The time relative to a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


slack (definition)
slack

The difference between the constraint and the analyzed value, with negative slack indicating an error condition.


source (definition)
source

An output pin that drives a path. Sources are input pads and the outputs of synchronous elements.


static timing analysis (definition)
static timing analysis

A point-to-point delay analysis of a design network with respect to a given set of constraints. It does not include insertion of stimulus vectors.


status bar (definition)
status bar

An area located at the bottom of an application window that provides information about the commands that you are about to select or that are being processed.


time group (definition)
time group

A collection of design elements, including nets, BELs, components, and so forth that can be used to constrain many objects in the same way.


timing constraints (definition)
timing constraints

A series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay.


toolbar (definition)
toolbar

A group of buttons with graphic icons located under the menu bar in the application window that provide button access to frequently used commands in pull-down menus.


TRACE (definition)
TRACE

The Timing Reporter And Circuit Evaluator provides static timing analysis of a design based on input timing constraints. Its two major functions are timing verification and reporting.


universal interconnect matrix (definition)
universal interconnect matrix (UIM)

The routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing 100 percent routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.


verification (definition)
verification

In timing, the process of comparing the desired performance of a design using constraints against the expected performance, based on software models of the device speed and routing delays.


VHDL (definition)
VHDL

An acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High-Speed Integrated Circuits) or HDL, which can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level.