Copyright: HH Bridge(c) Bristol Technology Inc. 1993


Overview

LogiBLOX is a graphical interactive design tool that you can use to create high-level modules such as counters, shift registers, and multiplexers. LogiBLOX includes both a library of generic modules and a set of tools for customizing them.

Using the LogiBLOX graphical user interface (GUI), you can create and process high-level LogiBLOX modules that fit into your schematic-based design or HDL synthesis-based design.

The modules you create with LogiBLOX can be used in designs generated with schematic editors from Aldec, Viewlogic, Mentor Graphics, and Cadence, as well as third-party synthesis tools such as Synopsys FPGA Compiler, FPGA Express, and Exemplar Logic.


LogiBLOX Window

For information on using the LogiBLOX GUI, select one of the topics from the list below.

Note:  Menus, dialog boxes, and parts of the application window are documented as they appear on a Unix workstation. Differences between the PC and the workstation applications are documented if there is a difference in operation between the two platforms.

About the Module Selector Dialog Box

About the Setup Dialog Box

About the User Preferences Window

About the Modules

About the Files

About the GUI Messages Window


How to Use Help

This page is a quick reference guide to the LogiBLOX Help.

Help Topics Organization

Getting Started	An overview of LogiBLOX and instructions for using the interface
About the Modules	Descriptions of the LogiBLOX modules
Procedures	Step-by-step instructions for performing tasks
Help on Help	Instructions for using help and how to access it
Reference	Glossary, trademark, technical support, and additional resource information
Summary of Help Operations

To	Do this
Go to related topics	Click underlined words
Go to the Help Topics	Click Help Topics
Search in the Help	Click Index or Find, select a topic
Scroll in the Help window	Move the scroll bars with the mouse
Return to the previous topic	Click Back
Return to any previous topic	From the Options menu, select Display History Window and select a topic
Browse forward	Click Browse>>
Browse backward	Click <<Browse
Get detailed help on Help	On the workstation, select How to Use Help from the Help menu
Close the Help window	Select Exit from the Help File menu
Printing Help Topics	On the workstation, select How to Use Help from the Help menu, and select Configure a Printer from the How To list


Obtaining Help

You can obtain help on commands and procedures by clicking the Help button in the toolbar, clicking the Help button in dialog boxes, or pressing the F1 key. The Help button in the toolbar and in some menu command dialog boxes provides context-sensitive help.

Help Menu

The Help menu displays the following commands.

•	Help Topics lists the online help topics available. From the opening screen, you can jump to command information or step-by-step instructions. After you open help, you can click the Help Topics button (first button on the left) in the Help window whenever you want to return to the help topics list.

•	About Software displays a popup window that shows the version number of the software.

Toolbar

You can obtain context-sensitive help from the toolbar.

1.	Click the Help button.

The cursor changes to a question mark.

2.	Click once with the left mouse button on the menu item or toolbar button for which you want information.

Online help information about the selected command appears in a popup window.

Help Button in Dialog Boxes

Many of the dialog boxes have a Help button that you can click to obtain help on that dialog box. A window opens that displays information.

F1 Key

Pressing the F1 key when the cursor is placed on a dialog box displays help on that dialog box. The F1 key functions the same as selecting Help Topics from the Help menu, if no dialog boxes are displayed.


About the Module Selector Dialog Box

Use the Module Selector dialog box to create a new module, or modify an existing design module. Once the module is created or modified, it can be added to or updated in your design.

Adding a Module to Your Design

There are three sections in the LogiBLOX Module Selector dialog box.

•	Selection — choose the Module Name, Module Type, and Bus Width.

•	Details — represents a graphical model of the module and provides check boxes to select or deselect optional pins on the symbol.

•	Attribute Selection Boxes — enter or select attributes specific to your design.

Selection

The Selection section has three drop-down list-boxes for you to choose a Module Name, Module Type and Bus Width. Each Selection is explained below.

Module Name

Use the Module Name selection to identify the module you want to create, or click the drop-down list arrow to see the list of modules that have already been created for your project. LogiBLOX uses the name to create files in which it saves the different outputs it generates for the module. If you choose an existing module from the pull-down list and alter its characteristics, you must change the module name or you will overwrite the existing module. Overwriting an existing module implies that you want to update the selected module.

Note:  Do not give a LogiBLOX module the same name as an existing component in the Unified Libraries.

Module Type

Use the Module Type selection to identify the type of module you want to add to your design. Click the drop-down list arrow to see the list of module types that are available. Each module type displays a graphical representation of the module in the Details portion of the dialog box. If you have been previously working on a particular module type, that module will be displayed. If you are creating a new module, the Accumulator module type will be displayed by default. To see details on each of the available module types, see About the Modules.

Bus Width

Use the Bus Width selection to select the data bus width for the module. You can use one of the predefined settings (2, 4, 8, 16, or 32 bits), or type in a custom bus width in the text box. Generally, the minimum value allowed is 2 and the maximum is 64. Decimal is the only valid base. All LogiBLOX bus pins are big endian, that is, the bits in a bus of width N are numbered N-1 through 0.

Details

The Details section of the Module Selector dialog box shows a graphical representation of the current module configuration.

Use the check boxes to select or deselect optional pins on the symbol.

Attributes Section

The attributes section provides list-boxes of attributes that can be selected or fields in which values can be entered. The values you select or enter are used to customize your module design.

The attributes are described in detail in About the Modules.

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See also

 	User Preferences Window


About the Setup Dialog Box

Use the LogiBLOX Setup dialog box to define the settings for each new project. You can edit these settings by clicking on the Setup button from the Module Selector dialog box.

The Setup dialog box is displayed if the Module Selector does not find the initialization file, logiblox.ini, in the current directory. This is the case when you invoke LogiBLOX for the first time.

Using the Setup Dialog Box

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See Also

Vendor

Project Directory

Device Family

Options


Vendor

Use the Vendor panel to select the third-party vendor and associated bus notation.

Vendor Name

Select a vendor from the pull-down list box.

You must choose one of the following in order to return to the Module Selector.

•	Cadence

•	Foundation

•	Mentor

•	Synopsys

•	Viewlogic

•	Other

Bus Notation

Different vendors use different notations to reference a bus index. When you select one of the vendors in the Vendor Name list, LogiBLOX automatically assigns the default notation for that vendor.

If you select Other, then you must also select a bus notation from the following choices. You must choose one in order to return to the Module Selector.

•	B<I>

•	BI

•	B(I)

•	B[I]

B is the name of the bus. I is the index of the bus. For example, if the bus notation is B<I> and the bus name is Q_OUT[2:0], the expanded bus will be Q_OUT<2>, Q_OUT<1>, Q_OUT<0>.


Project Directory

Use the Project Directory choice on the Setup dialog box to choose the directory path to which the logiblox.ini configuration file and all output files will be stored. The Project Directory option may not be available if LogiBLOX is invoked from a third-party schematic editor such as Viewlogic. In that case, LogiBLOX determines where to store the output netlist.

You can select a project directory by either entering the directory name directly in the LogiBLOX Project Directory field or opening the Browse dialog box and choosing a directory from the list of available directories.

Note:  In Windows 95, if you start LogiBLOX by selecting 'Run' in the Start menu and entering 'lbgui' in the Run window, the default project directory may show as C:\WIN95\DeskTop. This will send all output generated by LogiBLOX to the desktop. You should change the project directory to some other location, such as C:\LOGIBLOX.


Browse Dialog Box

Use the Browse dialog box to see a graphical representation of the current directory structure. From the Browse dialog box you can select the directory in which you want LogiBLOX to put your output files.

To select a directory, perform the following steps.

1.	Click the directory name in which you want your module files to be placed. The directory you select is displayed in the Directory Name field.

Note: If you are using LogiBLOX on Windows NT or Windows 95, you must also select the drive.

2.	Click OK.

The Browse dialog box will close, and the directory you selected will display in the LogiBLOX Project Directory field.


Device Family

Use the Device Family choice on the Setup dialog box to select one of the supported Xilinx device families. The supported device families for LogiBLOX follow:

Spartan

SpartanXL

XC3000A

XC3000L

XC3100A

XC3100L

XC4000E

XC4000EX

XC4000L

XC4000XL

XC4000XLA

XC4000XV

XC5200

XC9500

XC9500XL

LogiBLOX checks whether the appropriate libraries are installed for each of these families. The families whose libraries are not installed will not appear in the list of choices in the pull-down list box.

This information is needed by the Design Rule Checker (DRC). It is also used for NGO file generation.


Options

Use the Options choice on the Setup dialog box to select the outputs you require for your design. Each of your selections (except the LogiBLOX DRC box) generates a file that is placed in the project directory or other appropriate directories depending on your third-party vendor schematic editor.

There are four selection groups in the Options dialog box.

•	Simulation Netlist

•	Component Declaration

•	Implementation Netlist

•	LogiBLOX DRC

Simulation Netlist

You can select one or more of the simulation outputs.

The choices are:

•	Behavioral VHDL netlist — generates a simulation netlist in behavioral VHDL. The output file has a .vhd extension.

•	Gate level EDIF netlist — generates a simulation netlist in EDIF format. The output file has an .edn extension.

•	Structural Verilog netlist — generates a simulation netlist in structural Verilog. The output file has a .v extension.

Component Declaration

The choices in this box create instantiation templates in different formats that can be copied into your design. You can select either, both, or neither of the selections in this group.

The choices are:

•	VHDL template — generates a LogiBLOX VHDL component declaration and instantiation template that can be copied into your VHDL design when a LogiBLOX module is to be instantiated. The output file has a .vhi extension.

•	Verilog template — generates a LogiBLOX Verilog module definition and instantiation template that can be copied into your Verilog design when a LogiBLOX module is to be instantiated. The output file has a .vei extension.

Implementation Netlist

Select NGC File to generate an implementation netlist in Xilinx NGD binary format. You must select this option whether instantiating LogiBLOX modules in a schematic or HDL design. The output file will have an .ngc extension. NGDBuild reads these files when processing the top level module.

LogiBLOX DRC

You can select Stop Process on Warning to halt module processing if the DRC (Design Rule Checker) issues any warning messages during the design entry process.


User Preferences Window

Use the User Preferences window to select the editor you want to use for editing memory files. The default editor on UNIX platforms is vi. The default editor on Windows 95 and Windows NT is Wordpad.

Click the User Prefs button in the Module Selector to bring up the User Preferences window.


About the Files

There are several types of files that are created by LogiBLOX. You can select which files you want LogiBLOX to create from the Options choice in the Setup dialog box. There are, however, three files that are used by LogiBLOX that are created automatically for you. These are the initialization file, the module definition file, and the log file.

Below are descriptions of the different LogiBLOX files.

LogiBLOX Initialization Files

•	LogiBLOX Initialization File (logiblox.ini) — contains the information you recorded on the initial setup dialog box. At start-up, LogiBLOX reads this initialization information and uses it to configure the Module Selector.

•	Module Definition File (.mod) — defines the functionalities of a LogiBLOX module, specifying module type, module name, device family, attributes, and pin connections.

•	LogiBLOX Log File (logiblox.log) — contains all the messages printed in the GUI Messages window.

Simulation Files

•	VHDL Simulation Netlist (.vhd) — is the simulation model for a LogiBLOX module in behavioral VHDL. Selecting the "Behavioral VHDL netlist" option in the LogiBLOX Setup dialog box enables the generation of a VHDL behavioral simulation model.

•	EDIF Simulation Netlist (.edn) — is the simulation model of a LogiBLOX module in EDIF format. Selecting the "Gate level EDIF netlist" option in the LogiBLOX Setup dialog box enables the generation of a gate-level EDIF simulation model.

•	Verilog Simulation Netlist (.v) — is the simulation model of a LogiBLOX module in structural Verilog. Selecting the "Structural Verilog netlist" in the LogiBLOX Setup dialog box enables the generation of a structural gate-level Verilog simulation model.

Netlist File

•	LogiBLOX Implementation Netlist (.ngc) — is the LogiBLOX module implementation netlist in Xilinx NGD binary format. This is an NGD format implementation netlist used in the LogiBLOX HDL instantiation flow. This LogiBLOX-specific NGD implementation netlist will be merged with your top-level design during the implementation process. Selecting the "NGC File" option in the LogiBLOX Setup dialog box enables the output of the .ngc netlist.

Component Declaration Files

•	VHDL Instantiation Template (.vhi) — is the LogiBLOX VHDL component declaration/instantiation template to be copied into the user's VHDL design when a LogiBLOX module is to be instantiated. Selecting the "VHDL template" option in the LogiBLOX Setup dialog box enables the generation of the LogiBLOX VHDL component declaration and instantiation template.

•	Verilog Instantiation Template (.vei) — is the LogiBLOX Verilog module definition/instantiation template to be copied into the user's Verilog design when a LogiBLOX module is to be instantiated. Selecting the "Verilog template" option in the LogiBLOX Setup dialog box enables the generation of the LogiBLOX Verilog module definition and instantiation template.


About the Modules

You can see details about the LogiBLOX modules by selecting one of the module names from the list below.

Accumulator Module

Adder/Subtracter Module

Clock Divider Module

Comparator Module

Constant Module

Counter Module

Data Register Module

Decoder Module

Input/Output Module

Memories Module

Multiplexer Module

Pad Module

Shift Register Module

Simple Gates Module

Tristate Buffer Module


About the Accumulator Module

The Accumulator module takes the data on its B input port and its Carry Input port and adds this data to, or subtracts it from, the current value stored in the accumulator register. It then loads the result back into the register, making it available at the Q_OUT port.

There are two types of accumulators: those that accumulate the value applied to the symbol's B input port and those that accumulate a constant value.

The Carry Output and the Overflow outputs are generated by the Adder/Subtracter to indicate the status of the present arithmetic operation. You can latch these outputs by specifying the appropriate attribute. You can also load separate predefined values synchronously or asynchronously into any or all of the module's registers.

Descriptions of the Input pins and fields are provided below.

Input Pins

•	Add/Sub — The input on this pin determines whether the module should add the value on the B input port to or subtract it from the value in the Accumulator register. If the input is High, the module performs an addition. If the input is Low, the module performs a subtraction.

Connections: This pin is available only if you set the Operation attribute to Add/Subtract. If you select either of the individual Add or Subtract operation modes, the Add/Sub input pin is removed from the module.

•	Carry Input — The Carry Input port, together with the data on the B input port, is added to or subtracted from the current accumulator register value.

Connections: Carry Input is optional. Its value depends on whether the Operation mode is Add or Subtract. If Carry Input is not specified, the default values are 0 for Add and 1 for Subtract.

•	B — The data on the B input port, along with the Carry Input port, is added to or subtracted from the current accumulator register value.

Connections: The B input is present if a Constant value is not specified. If you set the Constant Value attribute, you generate a schematic symbol with a Constant input instead of the B input.

•	Load — The Accumulator register is loaded directly with the value on the B input port on the next active Clock transition when the Asynchronous Control and the Synchronous Control pins are Low and Load is High.

Connections: Load is optional. If you do not specify this input, the accumulator always adds or subtracts; it never loads.

•	Clock Enable — If the Clock Enable input is High, either the data on the B input port, the output of the adder/subtracter, or the value assigned to the Synchronous Value attribute is loaded into the accumulator register on the next active Clock transition.

If the Clock Enable input is Low, the register contents are unaffected by the Clock and the register holds its current value. This input does not affect asynchronous load operations, which occur when the Asynchronous Control pin is asserted.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

•	Clock — If the Clock Enable input is High, the rising clock edge loads the selected data into the accumulator register. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: Clock is always specified.

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When input is High, it loads the value assigned to the Asynchronous Value attribute into the accumulator register independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the accumulator register's power-on value.

•	Sync. Control — Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the accumulator register on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, a default value of 0 is used and a warning is issued.

Note: The Asynchronous Control and Synchronous Control inputs can be used to control all registered elements — the Accumulator register, the Registered Carry Output register, and the Registered Overflow register. The Asynchronous Value and Synchronous Value attributes may contain data for all three registered elements. See the Attributes section.

Output Pins

•	Q_OUT — The Q_OUT pin always reflects the current contents of the Accumulator register.

Connections: Q_OUT is always specified.

•	Overflow, Reg'd Overflow — Overflow is the overflow output from the adder/subtracter. Registered Overflow is the overflow from the Accumulator register. The overflow output is High when the result of the operation exceeds the maximum allowed value of the adder/subtracter.

Connections: Overflow and Registered Overflow are optional. If you specify one, you cannot specify the other.

•	Carry Output, Reg'd Carry Output — Carry Output is the carry out from the most significant bit of the adder/subtracter. Registered Carry Output is the carry out from the most significant bit of the Accumulator register.

Connections: Carry Output and Registered Carry Output are optional. If you specify one, you cannot specify the other.

Attributes

•	C Value — Use the Constant Value attribute to replace the B input port with a constant. If you do not define this attribute, the B pin is present.

•	Operation — Use the Operation attribute to specify one of the three possible arithmetic operation modes: Add, Subtract, or Add/Subtract. If you select Add/Subtract, an Add/Sub pin is automatically added to the module.

•	Style — Style defines the implementation preference for the module, that is, optimize for area or speed.

Usage: For more information, see the "Implementation Styles" section of the "Understanding Attributes" chapter of the LogiBLOX Guide.

•	Encoding — Encoding defines the encoding scheme assumed in the generation of the overflow output logic. Valid values are Signed and Unsigned.

•	Async. Val — The value of the Asynchronous Value attribute defines the power-on contents of the register. It can also be used to specify the data values assigned to the three registered elements: the Accumulator register, the Registered Carry Out register, and the Registered Overflow register. On assertion of the Asynchronous Control pin, the data values for the specified pins are extracted from the value assigned to the Asynchronous Value attribute.

Usage: The Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero. See the "Synchronous and Asynchronous Control" section of the "Understanding Attributes" chapter of the LogiBLOX Guide for information on how to specify the values of the Registered Carry Out and Registered Overflow registers.

•	Sync. Val — The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin. It can also be used to specify the data values assigned to the three registered elements: the Accumulator register, the Registered Carry Out register, and the Registered Overflow register. On assertion of the Synchronous Control pin, the data values for the specified pins are extracted from the value assigned to the Synchronous Value attribute.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin. See the "Synchronous and Asynchronous Control" section of the "Understanding Attributes" chapter of the LogiBLOX Guide for information on how to specify the values of the Registered Carry Out and Registered Overflow registers.


About the Adder/Subtracter Module

The Adder/Subtracter module adds or subtracts two data inputs and a Carry input. You can use this module as an adder, as a subtracter, or both. The Adders/Subtracters module provides a Carry Output and an Overflow output to indicate the status of the current arithmetic operation.

There are two types of Adder/Subtracter modules: those that add or subtract the values applied through two bus-pins, and those that add a constant to or subtract a constant from a value applied to one bus-pin.

The Adder/Subtracter module permits the user to register any or all of its outputs.

Input Pins

•	A — The data on the A input port, along with the data on the Carry Input port, is added to or subtracted from the data on the B input port (A+B + C_IN or A - B - C_IN).

Connections: Pin A is required.

•	Add/Sub — The input on this pin determines whether the module should operate as an adder or as a subtracter. If the input is High, the module performs an addition. If the input is Low, the module performs a subtraction.

Connections: This pin is available only if you set the Operation attribute to Add/Subtract. If you select either of the individual Add or Subtract operation modes, the Add/Sub input pin is removed from the module.

•	Carry Input — The Carry Input port, together with the data on the B input port, is added to or subtracted from the value on port A (A + B + C_IN or A - B - C_IN).

Connections: Carry Input is optional. Its value depends on whether the Operation mode is Add or Subtract. If Carry Input is not specified, the default values are 0 for Add and 1 for Subtract.

•	B — The data on the B input port, along with the Carry Input port, is added to or subtracted from the data on the A input port (A + B + C_IN or A - B - C_IN).

Connections: The B input is present if a Constant value is not specified. If you set the Constant Value attribute, you generate a schematic symbol with a Constant input instead of the B input.

Additional Input Pins for Registered Modules

•	Load — When the Asynchronous Control and the Synchronous Control pins are Low and the Load input is High, the data on the B port is loaded directly into the register on the next active Clock transition.

Connections: Load is optional. If Load is High, the data on the B port is loaded directly into the register. If Load is Low, the output of Adder/Subtracter is registered instead.

•	Clock Enable — Whenever the Clock Enable input is High, the data on the B input port, the output of the adder/subtracter, or the value assigned to the Synchronous Value attribute is loaded into the register on the next active Clock transition.

If the Clock Enable input is Low, the register contents are unaffected by the Clock and the register holds its current value. This input does not affect an asynchronous load operation, which occurs when the Asynchronous Control pin is asserted.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

•	Clock — If the Clock Enable input is High, the rising clock edge loads the selected data into the Adder/Subtracter register. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock pin is always specified when any of the Adder/Subtracter modules outputs are registered.

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute into the Adder/Subtracter register independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the adder/subtracter register's power-on value.

•	Sync. Control — Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the Adder/Subtracter register on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, a default value of 0 is used and a warning is issued.

Note: Asserting either Asynchronous Control or Synchronous Control affects all registered elements — the Adder/Subtracter register and potentially the Carry Output and Overflow registers. The Asynchronous Value and Synchronous Value attributes may contain data for all three registered elements. See the Attributes section.

Output Pins

One or more of the following output pins must be specified:

•	Sum — Sum contains the result of the arithmetic operation performed on the Adder/Subtracter's inputs. The output is called Sum if the module is not registered. For a registered module, the output is Q_OUT.

Connections: The Sum bus is the output of the Adder/Subtracter and is required if no other output pin is specified.

•	Overflow — Overflow is the overflow output from the adder/subtracter. The overflow output is High when the result of the operation exceeds the maximum allowed value of the adder/subtracter.

Connections: Overflow is optional. Either the Overflow or the Registered Overflow output can be specified, but not both.

•	Carry Output — Carry Output is the carry out from the most significant bit of the adder/subtracter.

Connections: Carry Output is optional. Either the Carry Output or the Registered Carry Output can be specified, but not both.

Additional Output Pins for Registered Modules

•	Q_OUT — Q_OUT always reflects the current contents of the Adder/Subtracter register.

Connections: Q_OUT is always specified for registered modules.

•	Reg'd Overflow — Registered Overflow is the overflow from the Adder/Subtracter register. The overflow output is High when the result of the operation exceeds the maximum allowed value of the adder/subtracter.

Connections: Registered Overflow is optional. Either the Overflow or the Registered Overflow output can be specified, but not both.

•	Reg'd Carry Output — Registered Carry Output is the carry out from the most significant bit of the Adder/Subtracter register.

Connections: Registered Carry Output is optional. Either the Carry Output or the Registered Carry Output can be specified, but not both.

Attributes

•	C Value — Use the Constant Value attribute to replace the B input port with a constant value. If you do not define this attribute, the B pin is present.

•	Operation — Use the Operation attribute to specify one of the three possible arithmetic operation modes: Add, Subtract, or Add/Subtract. If you select Add/Subtract, an Add/Sub pin is automatically added to the module.

•	Style — Style defines the implementation preference for the module, that is, optimize for area or speed.

Usage: For more information, see the "Implementation Styles" section in the "Understanding Attributes" chapter of the LogiBLOX Guide.

•	Encoding — Encoding defines the encoding scheme used in the generation of the overflow output logic. Valid values are Signed and Unsigned.

Additional Attributes for Registered Modules

•	Async. Val — The value of the Asynchronous Value attribute defines the power-on contents of the register. It also determines the data values assigned to the three registered elements: the Adder/Subtracter register, the Registered Carry Out register, and the Registered Overflow register. On assertion of the Asynchronous Control pin, the data values for the specified pins are extracted from the value assigned to the Asynchronous Value attribute.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero. See the "Synchronous and Asynchronous Control" section of the "Understanding Attributes" chapter of the LogiBLOX Guide for information on how to specify the values of the Registered Carry Out and Registered Overflow registers.

•	Sync. Val — The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin. It also determines the data values assigned to the three registered elements: the Accumulator register, the Registered Carry Out register, and the Registered Overflow register. On assertion of the Synchronous Control pin, the data values for the specified pins are extracted from the value assigned to the Synchronous Value attribute.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin. The default value is zero. See the "Synchronous and Asynchronous Control" section of the "Understanding Attributes" chapter of the LogiBLOX Guide for information on how to specify the values of the Registered Carry Out and Registered Overflow registers.


About the Clock Divider Module

The Clock Divider module uses a Linear-Feedback-Shift-Register (LFSR) counter and decoder to generate an output pulse train that is a function of the clock input and the control attributes.

The Clock Output period is a multiple of the Clock period specified by the Clock Divisor attribute. Even multiples of the Clock period produce a 50 percent duty cycle on the Clock Output, while odd multiples produce a Low Output for one extra Clock period.

You can use the Output Duty Cycle attribute to control the duty cycle if you need values other than 50 percent.

The LogiBLOX Bus Width field is not applicable to this module and is therefore disabled.

Input Pins

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When this input is High, the Clock Divider's internal counter is reset to the value specified with the Asynchronous Count attribute.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the clock divider register's power-on value.

•	Sync. Control — Whenever the Synchronous Control and Clock Enable inputs are High, the Clock Divider's internal counter is reset to the value specified with the Synchronous Count attribute on the next active clock transition.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, the default value is the first value in the LFSR count sequence and a warning is issued.

•	Clock Enable — When the Clock Enable input is High, the Clock Divider's internal counter increments on the next active Clock transition. When the Clock Enable is Low, the Clock Divider is unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

•	Clock — If the Clock Enable input is High, the rising clock edge increments the Clock Divider's internal counter. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock pin is always specified.

Output Pins

•	Clock Out — The Clock Output port produces a pulse train whose period is a multiple of the period of the Clock input. The Clock Output has a 50 percent duty cycle except when the Clock Divisor attribute is assigned an odd number, in which case the Clock Output is Low for one extra Clock period. Alternatively, the duty cycle can be controlled with the Output Duty Cycle attribute.

Connections: The Clock Output pin is always specified.

Attributes

•	Clock Divisor — The Clock Divisor attribute specifies the number of input Clock cycles for each Output Clock Cycle. This value must be a positive integer.

Usage: Clock Divisor can be set to a value of 2 or higher. A value must be specified for this parameter.

•	Output Duty Cycle — The Output Duty Cycle attribute defines the High time of the output clock wave form in terms of multiples of the input clock period. This value is an integer that is less than the Clock Divisor value. If Output Duty Cycle is not specified, a value of one-half the Clock Divisor value is used. If Clock Divisor is odd and Output Duty Cycle is not specified, the duty cycle is less than 50 percent because the output is High for only (n-1)/2 input clock periods.

Usage: Output Duty Cycle can be set to 1 or higher but must be less than the value assigned to the Clock Divisor attribute.

•	Async. Count — The value of the Asynchronous Count attribute defines the power-on contents of the register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Count specifies the point in the Clock Divider's count sequence to which the internal LFSR counter returns on assertion of Asynchronous Control. For example, Asynchronous Count=0 causes the LFSR counter to return to the first count in its sequence.

•	Sync. Count — The Synchronous Count attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Count is available only if you specify the Synchronous Control pin. The Synchronous Count attribute specifies the point in the Clock Divider's count sequence to which the internal LFSR counter returns on assertion of Synchronous Control. For example, Synchronous Count=0 causes the LFSR counter to return to the first count in its sequence.


About the Comparator Module

The Comparator module compares the magnitude of two values, their equality, or both their magnitude and equality. There are two types of comparators: those that compare the values applied to the symbol's two bus-pins and those that compare a constant against the value applied to the A bus-pin.

Input Pins

•	A — The data on the A input port is compared to the data on the B input port.

Connections: A is a required input.

•	B — The data on the B input port is compared to the data on the A input port.

Connections: The B input is present if a Constant value is not specified. If you set the Constant Value attribute, you generate a schematic symbol with a Constant input instead of the B input bus.

Output Pins

At least one of the following outputs must be specified:

•	A = B — This output is an active High output when the data on the A input port equals the data on the B input port.

•	A <> B — This output is an active High output when the data on the A input port does not equal the data on the B input port.

•	A < B — This output is an active High output when the value on the A input port is less than the value on the B input port.

•	A > B — This output is an active High output when the value on the A input port is greater than the value on the B input port.

•	A <= B — This output is an active High output when the value on the A input port is less than or equal to the value on the B input port.

•	A >= B — This output is an active High output when the value on the A input port is greater than or equal to the value on the B input port.

Attributes

•	C Value — Use the Constant Value attribute to replace the B input port with a constant. If you do not define this attribute, the B pin is present.

•	Style — Style defines the implementation preference for the module, that is, optimized for area or speed.

Usage: Setting Style to Edge Decode or Wired AND causes all of the outputs to disappear except A = B and A <> B. For more information, see the "Implementation Styles" section in the "Understanding Attributes" chapter of the LogiBLOX Guide.

•	Encoding — Encoding defines the encoding scheme used to represent the data type of the module. Valid values are Signed and Unsigned.


About the Constant Module

The Constant module is used to force a constant value onto a bus. The Constant value is assigned to the module by means of a LogiBLOX attribute and can only be changed during the LogiBLOX module generation process.

Output Pins

C — The C output port contains the constant value specified by the user.

Connections: The C output pin is always present.

Attributes

C Value — Use the Constant Value attribute to define the data value that is forced onto a bus.

Usage: Edit the Constant Value attribute field to assign a value to the constant. For more information on how to specify the data values, see the "Data Values" section in the "Understanding Attributes" chapter, in the LogiBLOX Guide.


About the Counter Module

The Counter module generates a sequence of count values determined by the selected encoding and the status of the control inputs. The Counter module can be an up counter, down counter, or up/down counter with a predefined asynchronous or synchronous pre-load, and a dynamic synchronous parallel load.

LogiBLOX counter modules can be loaded with a value applied to a bus-pin or with a pre-defined constant.

Input Pins

•	D_IN — The Parallel Data from the D_IN input port is loaded into the counter during a Parallel Load operation on an active Clock transition.

Connections: The D_IN port is optional. When it is specified, the Load pin is also specified. If the module uses the LFSR Encoding, the maximum bus width for this module is 31, otherwise, the maximum bus width is 64.

•	Load — When the Parallel Load input is High, the data on the D_IN input port is loaded into the counter on the next active Clock transition. When the Load input is Low, the counter responds to the Up/Down control input. In order for a Load operation to take place, Asynchronous Control and Synchronous Control must both be Low and the Clock Enable must be High.

Connections: The Load input is automatically specified when the D_IN port is specified.

•	Up/Down — The Up/Down control input controls the direction of the count on the next active Clock transition. When Up/Down is High, the counter value is increased by one; when Up/Down is Low, the counter value is decreased by one.

Connections: The Up/Down input pin is present only if the Up/Down Operation mode has been selected. Because the LFSR counter does not support down-counting, it must always use the Up Operation type.

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute (or Asynchronous Count for an LFSR counter) into the counter independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value or Asynchronous Count attribute. By default, the attribute is assigned a value of zero if it is not specified. The Asynchronous Value and Asynchronous Control attributes may also be specified to define the accumulator register's power-on value.

•	Sync. Control — Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute (or Synchronous Count for an LFSR counter) is loaded into the counter on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin, you must assign a value to the Synchronous Value attribute (or Synchronous Count for an LFSR counter).

•	Clock Enable — When the Clock Enable input is High, the enabled load and count actions take place on the next active Clock transition. When Clock Enable is Low, the counter contents are unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

•	Clock — If the Clock Enable input is High, the rising clock edge either loads the selected data into the counter or increments or decrements the counter. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock input pin is always specified.

Output Pins

At least one of the output pins, Q_OUT or Terminal Count, must be specified.

•	Q_OUT — The Counter Output pin (Q_OUT) contains the current value of the counter.

•	Terminal Count — The Terminal Count output pin goes High for one clock cycle every Count Limit cycles. Count Limit is either specified by the user or, if not specified by the user, is the maximum value of the counter. The maximum value of Count Limit is listed in the "Counter — Encodings" table in the "Counter" section of the LogiBLOX Guide.

For an Up Counter, the Terminal Count is High during the cycle in which the counter reaches its maximum sequence value.

For a Down Counter, the Terminal Count is High during the cycle in which the counter reaches its minimum sequence value, typically zero.

For example, for a 4-bit binary Up Counter with no Count Limit attribute specified, the Terminal Count is High when the counter reaches its maximum value of 1111.

Attributes

•	Operation — Use the Operation attribute to specify one of the three possible types of counters: Up, Down, or Up/Down. If you select Up/Down, an Up/Down pin is automatically added to the module.

Note:  When the Encoding attribute is set to LFSR, the only value allowed for Operation is Up.

•	Style — Style defines the implementation style (area or speed preference).

Usage: Maximum Speed is the default implementation style and is the only valid style for all counters other than Binary counters. When the Encoding attribute is set to Binary, Style can be set to any of the available values. For more information, see the "Implementation Styles" section in the "Understanding Attributes" chapter of the LogiBLOX Guide.

•	Encoding — You can use this parameter to define the encoding of the Q_OUT port. When Encoding is set to LFSR, the only value allowed for Operation is Up, Style must be set to Maximum Speed, and the Asynchronous Count and Synchronous Count attributes are enabled instead of Asynchronous Value and Synchronous Value.

The encoding selections and corresponding maximum counts follow:

Binary — Binary Counter ((2 to the power of n)-1)

Johnson — Johnson Counter (2n)

LSFR — Linear Feedback Shift Register ((2 to the power of n)-1)

One-Hot — Generates a ONE_HOT sequence. (n)

Usage: Encoding defines the count sequence of the counter.

•	Count Limit— The Count Limit value defines the number of cycles before the counter resets to its initial value, after which the count sequence restarts. Thus, Terminal Count will be High for one cycle every Count Limit cycles. You should specify Count Limit only if the length of the count sequence is different than the MAX Count Limit associated with the counter's encoding.

The following values are valid for the Count Limit field.

Binary: The Count Limit attribute values are any number between 2 and (2 to the power of n)-1 inclusive.

Johnson: The only allowed Count Limit attribute values are 2n or 2n-1.

LFSR: The Count Limit attribute can be any number between 2 and (2 to the power of n)-1 inclusive.

One-Hot: The Count Limit attribute may not be set.

When Count Limit is used with a Binary counter, the following applies. If counting down, the counter counts down to 0 and on the next cycle, Q_OUT goes to Count Limit. If counting up, the counter counts up to Count Limit and on the next cycle, Q_OUT goes to 0.

The behavior of a counter loaded with a value outside the range of the Count Limit (with D_IN, Sync_Val, or Async_Val) is undefined. However, Binary and Johnson counters are guaranteed to return to legal count sequences after as many as 2 to the power of n (Binary) or 2n (Johnson) clock pulses.

•	Async. Val — The value of the Asynchronous Value attribute defines the power-on contents of the counter. It also defines the value to which the counter returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, its default value depends on the kind of counter you specify with the Encoding attribute. For Binary and Johnson counters, the default value is zero. For One-Hot counters the default value is 1. If the Encoding attribute is set to LFSR, you cannot assign a value to the Asynchronous Value attribute.

•	Sync. Val — The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin. Note that when the Encoding attribute is set to LFSR, you cannot assign a value to Synchronous Value.

•	Async. Count — The Asynchronous Count attribute specifies the counter's reset state on assertion of the Asynchronous Control pin. The number specified for this attribute represents the number of transitions from the counter's initial default state. For example, if Asynchronous Count is set to 5, then the value in the counter after its first five transitions is the value assigned to the counter whenever the Asynchronous Control pin is asserted.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero. Use Asynchronous Count instead of Asynchronous Value when the Encoding attribute is set to LFSR.

•	Sync. Count — The Synchronous Count attribute specifies the counter's reset state on assertion of the Synchronous Control pin. The number specified for this attribute represents the number of transitions from the counter's initial default state. For example, if Synchronous Count is set to 5, then the value in the counter after its first five transitions is the value assigned to the counter whenever the Synchronous Control pin is asserted.

Usage: Synchronous Count is available only if you specify the Synchronous Control pin. Use Synchronous Count instead of Synchronous Value when the Encoding attribute is set to LFSR.


About the Data Register Module

The Data Register module is used to capture the data applied to its D_IN port on active Clock transitions. The contents of the data register are always present on the Q_OUT port. The module is synthesized as an array of flip-flops that can be loaded with predefined asynchronous and synchronous data.

Input Pins

•	D_IN — The data applied to the D_IN input port is loaded into the register when the Clock Enable is High and an active Clock transition occurs on the Clock pin.

Connections: The D_IN port is always specified.

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute into the data register independently of the Clock and Clock Enable.

Connections: Asynchronous Control is optional. If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the accumulator register's power-on value.

•	Sync. Control — Synchronous Control is optional. Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the data register on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin, you must assign a value to the Synchronous Value attribute.

•	Clock Enable — When the Clock Enable input is High, the D_IN input data or the value assigned to the Synchronous Value attribute is loaded into the register on the next active Clock transition. When the Clock Enable is Low, the register contents are unaffected by the Clock. This input does not affect asynchronous load operations, which occur when the Asynchronous Control pin is asserted.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled. When the Style attribute is set to Latches, this input becomes a Gate Enable.

•	Clock — If the Clock Enable input is High, the rising clock edge loads the selected data into the register. You can implement an active falling (negative) clock edge by connecting an inverter to the Clock input.

Connections: The Clock pin is always specified. When the Style attribute is set to Latches, this input becomes a Gate.

Output Pins

•	Q_OUT — Q_OUT always reflects the Data Register's contents.

Connections: Q_OUT is always specified.

Attributes

•	Style — Style defines whether the module is implemented as an array of Latches or D-Type flip-flops.

Usage: Set this attribute to D-Type or Latches. The value D-Type is valid for all architectures. The value Latches is only valid for the XC4000EX and XC5200 device families.

•	Async. Val — The value of the Asynchronous Value attribute defines the power-on contents of the register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero.

•	Sync. Val — The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin.

•	Use RPMs— Use RPMs attribute determines whether the data flip-flops in the register maintain a constant relative location to each other. This attribute applies to the XC4000 and XC5200 device families only.

This attribute is not supported if Style is set to Latches.

Usage: Use RPMs can be set to True or False. The default is False.


About the Decoder Module

The Decoder module converts unsigned binary data on the Select port to a 1-of-n one-hot output on the D_OUT port. The width (precision) of the Select and D_OUT ports is determined by the Bus Width attribute.

Input Pins

•	Select — The data on the Select pin is converted to a one-hot value on the D_OUT port.

Connections: The Select pin is always specified. Specify its bus width by selecting the appropriate width from the Bus Width pull-down list box. The valid range of values for the bus width is 2 through 8.

•	Enable — When the Enable Input is High, the selected Output is High. When the Enable Input is Low, the Decoder is disabled and all bits of the Output are Low. If the Enable Input is not specified, the Decoder is always enabled.

Connections: The Enable input is optional.

Output Pins

•	D_OUT — When enabled, one of the lines of the D_OUT port will be High (one-hot encoding). The width of the D_OUT pin is 2 to the power of n, where n is the width of the Select pin.

Connections: The D_OUT pin is always specified.

Attributes

•	Style — The Style attribute is only enabled for the XC5200 device family. You can select Cascade, Maximum Speed, or Normal Gates. For more information, see the "Implementation Styles" section in the "Understanding Attributes" chapter of the LogiBLOX Guide.

For other device families, Style is always set to Normal Gates.


About the Input/Output Module

Input/Output modules represent the physical pins on a device that are actually used in a design. Pad modules are connected to the I/O modules to simulate input/output wires.

There are three types of I/O modules. These modules represent all the possible logic combinations that can fit into the Input/Output blocks (IOBs).

Input Modules

Input modules are device-input modules that connect a Pad to an internal pin signal or bus.

Output Modules

Output modules are device-output modules that connect an internal pin signal or bus to a Pad.

Bidirectional Modules

Bidirectional modules combine the function of an Input module with that of an Output module.

I/O modules can be registered or buffered. Buffered I/O modules simply output whatever appears on the input port. Registered I/O modules are used to store the I/O values and are implemented as IOB registers.

Input Pins

This section describes the input pins of the Input and Output modules. The input pins of the bidirectional module are just combinations of the same input pins for the Input and Output modules.

Input Module

•	P — The input of the Input module

Connections: This input is always specified. For bidirectional modules, P is both the input and output of the I/O module. Connect a Pad module to the P pin to simulate a wire.

Registered Input Module

If you select an input operation that includes a register, the following inputs are also available.

•	Input Clock — The Clock input loads the selected data into the register on the rising (positive) edge. You can implement an active falling (negative) edge by connecting an inverter to the Clock input.

Connections: The Input Clock pin is always specified on registered modules. If the Clock Enable input is specified and Low, the Clock is temporarily disabled and the register contents remain unchanged.

•	Input Clock Enable — When it is specified and Low, the Input Clock Enable input temporarily disables the clock, causing the register to hold its previous value. When the Input Clock Enable input is High, the input data is loaded into the register on the next active Clock transition.

Connections: The Input Clock Enable pin is optional. If this input is not specified, the Clock is always enabled.

Output Module

•	O — The O pin is the input to the Output module.

Connections: The O pin is always connected.

Registered Output Module

If you select an output operation that includes a register or tristate, the following pins are available.

•	Output Enable — The Output Enable input appears on a buffered tristate Output module. For all devices except the XC9500 and XC9500XL families, when Output Enable is High, the signal on the P pin is tristated. When Output Enable is Low, the signal is enabled. For the XC9500 device family, the signal on the P pin is tristated when Output Enable is Low and enabled when Output Enable is High. For the XC9500XL family, the value of the OE Phase attribute determines the behavior of the signal on the P pin when Output Enable is High or Low.

Connections: The Output Enable pin is always specified on a tristate Output module.

Note: In the Unified Libraries this pin is labeled T (for Tristate) rather than OE on the output buffers. Also, the bubble is not present, indicating that the signal is active when T is High.

•	Output Clock — The Clock pin, when enabled, loads the selected data into the register on the rising edge. You can use an active falling edge by connecting an inverter to the Clock input.

Connections: The Output Clock pin is always specified on a registered Output module.

•	Output Clock Enable — When the Clock Enable pin is High, the input data is loaded into the register on the next active Clock transition. When the Clock Enable is Low, the register contents are unaffected by the active Clock transition (hold).

Connections: The Clock Enable pin is optional. If this pin is not specified, the Clock is always enabled.

Output Pins

This section describes the output pins of the Input and Output modules. The output pins of the bidirectional module are just combinations of the same output pins for the Input and Output modules.

Input Module

•	I — The I pin is the output of the buffered Input module.

Connections: The I pin is always connected.

Registered Input Module

•	IQ — On a registered module, the I pin is replaced by the IQ pin.

On a registered buffer Input module, the output of the register is the IQ pin and the buffer output is the I pin.

Connections: The IQ pin is always specified in a registered Input module.

Output Module

•	P — The P pin represents the output of the Output module and connects to a signal outside the chip.

Connections: This pin is always specified. You must connect a Pad symbol to the P pin of an Output module.

Attributes

•	IO Type — The IO Type attribute specifies the type of I/O function: input, output, or bidirectional.

Usage: For each mode you select, the Input/Output module graphic is adjusted appropriately. For more information, see the appropriate pin descriptions section.

•	Input Operation — The Input Operation attribute specifies the operation mode of the Input module.

Usage: Valid values include Buffer Only, Register Only, Latch Only, Buffer and Register, and Buffer and Latch.

If you select an input option with a register, the Input Clock pin is automatically added. The Input Clock Enable pin is optional.

If you select an input option with a latch, the Input Gate pin is automatically added. The Input Gate Enable pin is optional.

•	Output Operation — The Output Operation attribute specifies the operation mode of the Output module.

Usage: Valid values include Buffer Only, Register Only, Tristate, and Register with Tristate.

If you select an output option with a register, the Output Clock pin is automatically added. The Output Clock Enable pin is optional.

If you select an output option with a tristate, the Output Enable pin is automatically added.

•	Async. Val — The Asynchronous Value attribute controls the power-on state of the registers.

Usage: This attribute applies to the registered I/O modules only. For dual-register modules, you can specify the asynchronous value for either or both registers by using any of the following formats:

IN:15

OUT:31

OUT:31.IN:15

where OUT is the Output register and IN is the Input register.

•	OE Phase — This attribute determines whether the signal on the P pin in a tristate Output module is tristated when the Output Enable is High or Low.

Usage: This attribute can only be set by the user for the XC9500XL device family. The attribute is set to Active High for the XC9500 family and to Active Low for all other families.


About the Memories Module

The Memories module allows the user to create ROM, RAM, Synchronous RAM, and Dual Port RAM modules. These modules store information in the form of words in a tabular fashion. Use these modules for the following purposes.

•	Store information from a user-edited memory file (.mem file) and access that information as needed (ROM)

•	Store dynamic information into memory and then read that information from memory (RAM)

ROM — Read-Only Memory Modules

The Read-Only Memory (ROM) module is a memory for storing information from a user-edited memory file (.mem file). The word storage capacity of the ROM is called the depth. The depth must be a multiple of 16, ranging from 16 to 256 words.

The size of the data stored within the ROM ranges from 1 through 64 bits. The largest word stored in the ROM should be within the boundaries set by the bus width of the Data Out pin, DO.

To read a word from the ROM, specify a binary number on the Address bus that matches the location of the desired word. The data is immediately output at the Data Out pin. Only addressable locations that are within the valid depth will be synthesized.

Input Pins

•	A — A binary value on the Address port selects a word by pointing to the ROM location in which that word is stored. The Data Output port displays the selected word.

Connections: The Address input is always specified.

Output Pins

•	DO — The Data Output port reflects the word currently addressed in the ROM.

Connections: The Data Output pin is always specified.

Attributes

•	Memory Depth — The Depth attribute defines the number of locations that can be addressed in the ROM module or the number of words that can be stored in the ROM. The depth must be a multiple of 16 and range from 16 to 256 words.

•	Mem File — The Memory File attribute references the name of a memory definition file that defines the initial contents of the ROM. The name of the memory definition file must have a .mem file extension. The extension can be omitted from the Memory File attribute. If the memory definition file exists, it will be read; otherwise, you can generate a memory definition template file from LogiBLOX by specifying a name for the file and clicking Edit. The template file created by LogiBLOX does not contain correct data and must be edited before you can use it.

Usage: The Memory File attribute must be specified for ROM modules.

•	Multiplexer Style — The Multiplexer Style attribute determines the way multiplexers are built in memory modules. These multiplexers use address lines as select lines and choose among the outputs of the memory distributed in the CLBs. The Wired AND style uses Tristate buffers and long lines. The Normal Gates style uses CLB logic functions to implement the multiplexers.

Usage: Choose between the Maximum Speed, Normal Gates, and Wired AND values. If Memory Depth is set less than 64, the Maximum Speed value defaults to Normal Gates. If Memory Depth is set to 64 or more, Maximum Speed defaults to Wired AND.

•	Use RPMs — The Use RPMs attribute determines whether the function generators that comprise the ROM maintain a constant relative location to each other. Preserving the relative location helps ensure that the performance of the ROM is maintained regardless of where it is placed within the FPGA. This attribute applies to the XC4000 and XC5200 device families only.

Usage: Use RPMs can be set to True or False. The default is False.

•	Trim — Empty data columns are preserved by the software unless the Trim attribute is set to TRUE. If the software trims empty ROM primitives, it may yield a smaller design. The trade-off of having a smaller design is that you may not modify the contents of the ROM without rerouting the design. The default value is FALSE.

RAM — Random-Access Memory Modules

Random-Access Memory modules are used to store dynamic data. There are three different types of RAM modules: level-sensitive Asynchronous RAMs, Synchronous RAMs, and Dual Port RAMs.

RAM modules are not supported for the XC3000, XC5200, and XC9500 device families.

There are two ways of using RAM modules. One way consists of storing data dynamically by addressing locations from the Address bus pin and writing binary data furnished by the Data Input port into these locations. The other way consists of initializing the RAM module's contents at power-up by specifying the Mem File attribute. You can access the latter information the same way as you would in a ROM module. Furthermore, you can overwrite the information by writing new data in the RAM locations.

Storing Data Dynamically

To store a new word into the RAM and read it out on the output port, the address of the location to be written is placed on the address bus pin (A), the data to be written is placed on the data bus pin (DI), and Write Enable is driven from low to high.

For Asynchronous RAM modules, when Write Enable goes High, the data on the Data Input port is immediately stored into the currently addressed location and read out at the Data Out port. For Synchronous RAM and Dual Port RAM modules, the Write Enable Clock must also go High. Once a word is stored in the RAM, you can re-access it from the Address pin independently of the Write Enable signal.

If Write Enable stays Low while a value appears at the Data In port, this data is ignored. Only values that occur on a rising Write Enable pulse can be written. The data on the Address bus and on the Data Input port cannot change for the duration of the Write Enable pulse.

Initializing RAM Contents

In XC4000 devices, the contents of the RAM module are undefined at power-up. In XC4000E and XC4000EX devices, the power-on state of the RAM can be controlled by using a Memory Definition File (.mem file).

You can use the RAM module like a ROM to store a memory definition file that fits the depth of the module. The depth of the module refers to the word storage capacity of the RAM. The depth must be a multiple of 16, ranging from 16 to 256 words.

The width of the words contained in the memory definition file must also be within the width of the RAM module. The width of the RAM module ranges from 1 through 64 bits. The width of the module is set by the bus width of the Data Out pin.

You may overwrite the RAM locations using the Data Input pin to feed new data into the locations addressed by the Address bus.

Level-Sensitive Asynchronous RAM Modules (RAM)

Each time the Write Enable pin goes High, the data on the Data Input is stored into the addressed RAM location for as long as Write Enable is active High. In addition, to prevent new data from overwriting the current location, there is a time frame during which the data on the Address and the Data In pins cannot change: when the Write Enable pin is Low before going High and triggering a write operation, and when the Write Enable goes Low again immediately after going High. These states are referred to as the Setup and Hold times respectively. The setup and hold time constraints on the Address and Data Input pins with respect to the Write Enable pulse cause the Level-Sensitive RAM module to have lower bandwidth than the synchronous RAM modules.

Synchronous RAM Modules (SYNC_RAM)

This module is identical to the Level-Sensitive RAM except that writes to the RAM are synchronized to the Write Enable Clock. When the Write Enable input is high and the Write Enable Clock goes from low to high, the data on the Data Input pin is written to the location specified by the Address input pin. The data on the Data Input pin appears on the Data Output pin after it is written to the RAM. New data appearing in the Data Input pin must wait for the next high on the Write Enable pin and a low to high transition on the Write Enable Clock before it is written.

This module is faster than a Level-Sensitive RAM due to the synchronous nature of the write, which allows pipelining of data on the Data Input pin.

Dual Port RAM Modules (DP_RAM)

The Dual Port RAM module includes two independent pairs of Address and Data Output pins that share access to the same region of memory, allowing simultaneous read and write access to it. Writes are synchronized by the Write Enable Clock input.

Input Pins

All input pins of the respective RAM modules are always specified.

•	DI —The Data Input port determines the contents that will be stored into the RAM as well as the data that appears at the Data Output port when the Write Enable input goes High. Only the data currently at the Data Input port is read when Write Enable goes High.

Connections: The Data Input port is always specified.

•	WR_EN — For Asynchronous RAM modules, when the Write Enable input is High, the data on the Data Input port is written into the currently selected address location. When Write Enable is Low, no new data can be written into the RAM. For Sync_RAM and DP_RAM modules, a High on this input must be accompanied by a rising edge of the Write Enable Clock input to store the data into the memory location.

Connections: Write Enable is always specified.

•	WR_CLK — When the Write Enable Clock input goes High, the data on the Data Input port is stored into the currently addressed location and immediately read out at the Data Output port.

Connections: This input is available and required for the SYNC_RAM and DP_RAM modules only. For a valid write operation, the Write Enable input must first go High before this input goes High.

•	A — This input bus addresses a location in the RAM. Its purpose is twofold: 1) it selects the location whose contents are to appear on the Data Output port, or 2) it selects the location where new data is written whenever the Write Enable input goes High (for the level-sensitive RAM) or when the Write Enable Clock goes high while the Write Enable input is High (for SYNC_RAM and DP_RAM). The width of the Address port is always log base 2 (Depth).

Connections: The Address input is always specified.

•	DPRA — The Dual Port Read Address port is used for the secondary address line in a dual port RAM. Data residing at the address specified by the DPRA port appears at the Dual Port Output (DPO).

Connections: The Dual Port Read Address input is available for Dual Port RAM modules only. It is always specified.

Output Pins

•	DO — The Data Output port displays the contents of the location being accessed. The width of the Data Output port is set by the Bus Width attribute.

Connections: The Data Output pin is always specified. On DP_RAM modules this output port is called Single Port Output.

•	SPO — The Single Port Output is used to output the data that occurs on the Data Input pin whenever the Write Clock Enable is High.

Connections: This output is only used by DP_RAM modules. It is always specified.

•	DPO — The Dual Port Output is used to output the data that resides at the address specified by the Dual Port Read Address (DPRA) input of the DP_RAM module. The value of DPO can change independently of the Write Enable Clock going High.

Connections: This output is used only by DP_RAM modules. It is always specified.

Attributes

•	Memory Depth — The Depth attribute defines the number of words that can be stored in the RAM module. The depth must be a multiple of 16 and range from 16 to 256 words. The default value is 16. The width of the address port is always log base 2 (Depth).

•	Mem File — The Memory File attribute references the name of a memory definition file that defines the initial contents of the RAM. The name of the memory definition file must have a .mem file extension. You can omit the extension whenyou specify the Memory File attribute. If the memory definition file exists, it will be read; otherwise, you can generate a memory definition template file from LogiBLOX by specifying a name for the file and clicking Edit. The template file created by LogiBLOX does not contain valid data and you must edit it before you can use it.

Usage: The Memory File attribute is optional for RAM modules.

•	Multiplexer Style — The Multiplexer Style attribute determines the way multiplexers are built in memory modules. These multiplexers use address lines as select lines and choose among the outputs of the memory distributed in the CLBs. The Wired AND style uses Tristate buffers and long lines. The Normal Gates style uses CLB logic functions to implement the multiplexers.

Usage: Choose between the Maximum Speed, Normal Gates, and Wired AND values. If Memory Depth is set to less than 64, the Maximum Speed value defaults to Normal Gates. If Memory Depth is set to 64 or more, Maximum Speed defaults to Wired AND.

•	Use RPMs — The Use RPMs attribute determines whether the function generators that make up the RAM maintain a constant relative location to each other.

Usage: You can set Use RPMs to True or False. The default is False.

Memory Definition File Syntax

A memory definition file, or MEMFILE, consists of two parts — the Header, which describes characteristics of the ROM or RAM module, and the Data portion, which defines the contents of the memory module. The beginning of the Data portion of the file is delimited by the DATA keyword. The memory definition file is not case-sensitive.

Memory Definition File Header

The Header defines characteristics of the memory module, such as its size and radix. Each of the following keywords must exist on a single line in the MEMFILE. Continuation characters are not allowed in the Header.

Depth (optional) The Depth attribute defines the depth, in words, of the module. Specify the Depth in decimal notation, unless a radix definition precedes it. The value you specify must match the value of the Memory Depth attribute.

depth memory_depth

Width (optional) The Width definition sets the width of the memory, which is the number of bits in each word. The width must be a positive, non-zero, integer. Specify the Width in decimal, unless a radix definition precedes it. The value you specify must match the value of the Bus Width attribute.

width memory_width

Default The Default definition sets the value of all memory locations that are not specified in the MEMFILE Data section. If you do not specify a default value, all unspecified locations are set to zero. The default definition uses the current radix, which is 10, unless a radix definition precedes it.

Radix This keyword defines the radix (or base) of the numbers following each radix definition in the MEMFILE. Multiple radix definitions can appear in the header and affect all non-radixed numbers up to and including the next Radix definition. A radix definition affects the MEMFILE Header section and the MEMFILE Data section.

The default radix for the MEMFILE Header section is 10. The default radix for the MEMFILE Data section is 16.

radix integer

Comments Comments must be preceded by a semicolon. You can start your comment anywhere on the line. A semicolon at the end of the line generates a blank comment because it does not affect the next line of text.

; commentstring

Example The following example illustrates the syntactical concepts defined above:

; The default radix is 10
Default 10; Defines the default ROM contents = 10 base 10=10
Radix 16; Re-defines default radix = 16 base 10=16
Depth 10; Defines the depth = 10 base 16=16
Radix 10; Re-defines the default radix = 10 base 16=16
Width 12; Defines the width = 12 base 16=18

Memory Definition File Data Section

The data values you specify in the MEMFILE Data Section define the contents of the memory. Specify data values sequentially, beginning with the lowest address in the memory, as defined. You can specify the address of a data value. The default radix of the data values is 16. If more than one radix definition is given in the MEMFILE Header Section, then the last such definition is the radix used in the Data Section.

data data values

You can separate data values by commas, white space, or both.

Addressing An address is specified as follows.

address:

For example, the following definition defines a 16-word memory with the contents 6, 4, 5, 5, 2, 7, 5, 3, 5, 5, 5, 5, 5, 5, 5, 5, starting at address 0. Note that the contents of locations 2, 3, 6, and 8 through 15 are defined by the default definition. Two starting addresses, 4 and 7, are given.

depth 16
default 5
data 6,4,
4: 2, 7,
7: 3

ASCII Data You can specify ASCII data values by enclosing a string of characters in double quotes. You can include a double quote in a string by prefacing the character with a backslash (\). A MEMFILE may contain both ASCII strings and numeric values. Each ASCII character gets assigned to one address location.

For instance, the following defines the contents of 16 memory locations. Two ASCII BEL characters (7) are defined here — one before the "R" and one after the two "l" characters.

data 7, "Ring the bell", 7, 0.

Differences Between the LogiBLOX Memfile and the Memgen/XBLOX Memfile

LogiBLOX imposes some restrictions on memfiles that were previously supported by Memgen or X-BLOX 5.2.1:

•	The LogiBLOX memfile does not allow a PART declaration.

•	The radix of the data section is set by the RADIX command in the data section and cannot be changed. The radix cannot be overridden by using notation such as 2#1101#.

•	The characters `#' and `_' are not allowed in the memfile.

•	The depth value must be a multiple of 16. The valid range is 16 to 256 words.


About the Multiplexer Module

Select the type of multiplexer you want: Type 1 or Type 2. Type 1 includes one input bus and one select line. Type 2 includes at least two input buses and one select line.

Type 1 (One input bus)

The Type 1 Multiplexer module routes one bit of an n-bit Input to the Output under the control of the Select input port, where the value of n is determined by the width of the input port. The Select input encoding can be binary or one-hot.

Type 2 (Two to eight input buses)

The Type 2 Multiplexer module routes one of two or more Input Buses to the Output Bus under the control of the Select input port. The Select input encoding can be binary or one-hot.

Input Pins

•	M — M is the Multiplexer input bus data port of the Type 1 Multiplexer. The width of this bus is specified via the Bus Width attribute.

Connections: The Multiplexer input is always specified on Type 1 Multiplexers.

•	MA through MH — MA, MB, ..., MH are the input bus data ports of the Type 2 Multiplexer. For a 3-input bus module with binary encoded Select, MA is selected when the Select input evaluates to zero, MB is selected when the Select input evaluates to 1, and MC is selected when the Select input evaluates to 2. If the value of the Select input is 3, the Multiplexer outputs are all High.

Connections: The MA and MB inputs are always connected on Type 2 Multiplexers. The other inputs are dependent on the value of the INPUT_BUSES attribute. For example, if INPUT_BUSES=4, then MA, MB, MC, and MD would be the input buses shown. The input and output buses must have the same width. The maximum bus width is 64.

•	S — The Select input port chooses which input bus line is directed to the Multiplexer output line. Depending on the encoding scheme, the Select input can address more lines than are available on the input bus.

Connections: The Select input is required. The Select input port is from 1 to 64 bits wide on a Type 1 Multiplexer. On a Type 2 Multiplexer, the Select input port is from 1 to 8 bits wide, depending on the Select encoding method.

Output Pins

•	O — The Multiplexer output line (for a Type 1 multiplexer) or Bus port (for a Type 2 multiplexer) reflects the selected input bus port data. If the selected input port is unavailable (out-of-range), the Multiplexer outputs are High.

•	Connections: The output pin must be connected.

Attributes

•	Operation — The Operation attribute specifies the type of multiplexer module you want: single-bus input or multiple-bus input.

Usage: Valid values are Type 1 (single-bus input) and Type 2 (multiple-bus input).

•	Style — Style defines the implementation style (area or speed preference).

Usage: For more information, see the "Implementation Styles" section in the   "Understanding Attributes" section of the LogiBLOX Guide.

•	Input Buses — Use the Input Buses attribute to specify the number of input buses for Type 2 multiplexers. The number of buses can be any number in the range from 2 to 8.

Usage: This attribute only applies to Type 2 modules.

•	Encoding — Use the Encoding attribute to specify the encoding scheme used to represent the Select bus.

Usage: Valid values are Binary and One Hot.


About the Pad Module

Connect a Pad module to an Input/Output module to simulate the connection to the pin pad.

Attributes

•	Operation — This attribute selects the type of I/O module to which you will connect the Pad module. Valid values are Input, Output, and Bidirectional.

•	Pull-up/down Resistors — This attribute is used to tie all the pads of a symbol to pull-up or pull-down resistors. If no external signal is driving an input pad or tristate output pad, and it is not pulled up/down, it will float. You can use a value of Pull Up to drive a value that tends to 1 or a value of Pull Down to drive a value that tends to 0.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is optional and applies only to Input or tristatable Output modules. By default, no resistor is specified.

See the XC4000E and XC4000EX sections in The Programmable Logic Data Book for timing details.

•	Delay — By default, a delay, representing the internal IOB delay block, is used. The delay block ensures that the data path from Pad to register, also known as the setup time, is always longer than the external clock delay.

Using the IOB delay block prevents external data from overwriting the data currently at the Data Input port of the register before that data has been clocked into the register. Delaying the source data makes it unnecessary to specify a hold time to slow down the external data.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is only valid for modules that include an input register. The default is to use a Delay block. Select from the following values.

•	(none): This is the default. Uses a Delay block to slow down the time it takes for the signal to go from the device pin (Pad pin) to the register data input pin.

•	Medium Delay: This is only applicable to XC4000EX devices. It is a partial delay block within the IOB. Refer to the The Programmable Logic Data Book for more details.

•	No Delay: Bypass the Delay block. If you get rid of the Delay block, ensure that the external hold time is adequate. Refer to The Programmable Logic Data Book for more information.

•	Slew Rate — The slew rate of each output buffer is, by default, reduced in order to minimize power bus transients when switching non-critical signals. This reduces ground bounce when all outputs are being transitioned at the same time. See The Programmable Logic Data Book for more details.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is only valid for modules that include an output register. Set the Slew Rate to Fast to ensure that the fastest rate available is used for the slew rate of a critical output. The default value is Slow.

•	Pad Loc — The Pad Loc attribute specifies the pin location for an I/O pad.

Unlike other LogiBLOX attributes, the LogiBLOX Pad Loc setting can be overridden by location attributes specified on the LogiBLOX symbol in the schematic.

Usage: To assign a location to a specific bit, precede the location with a bit identifier. You can assign multiple bits by using a period as a separator. For example, with a bus width of 8 bits, you could have the following assignment:

PAD_LOC=0:P44.2:P45.7:P46

This specification assigns bit 0 to pad 44, bit 2 to pad 45, and bit 7 to pad 46.

Note: Commas will not work as separators between bit assignments.


About the Shift Register Module

The Shift Register module is multi-functional, with predefined asynchronous or synchronous pre-load, and dynamic synchronous parallel load.

The Shift Register can be synthesized in any one of the following configurations. For examples, refer to the figures at the end of the "SHIFT REGISTER" section in the LogiBLOX Guide.

•	Serial-in/serial-out shift register (FIFO or LIFO)

•	Serial-in/parallel-out shift register

•	Parallel-in/parallel-out shift register

•	Parallel-in/serial-out shift register

You can also select the shift style of the register. The shift styles include the following:

•	Logical — Data is shifted either left or right. For a left shift, the value specified by LS_IN is shifted into the LSB position. For a right shift, the value specified by MS_IN is shifted into the MSB position.

•	Circular — Data is shifted in a circular pattern. For a left shift, the MSB is shifted into the LSB position. For a right shift, the LSB is shifted into the MSB position.

•	Arithmetic — Data is shifted left to effectively multiply it by 2 or shifted right to effectively divide it by 2. For a left shift, a value of 0 is stuffed into the LSB. For a right shift, the Sign bit is extended if the data is signed. If the data is unsigned, a value of 0 is stuffed into the MSB.

Input Pins

•	D_IN — The Parallel Data from the Data Input port is loaded into the register during a Parallel Load operation on an active Clock transition.

Connections: The Data Input port is optional. When it is specified, the Load pin is also specified.

•	Load — When the Parallel Load input is High, the data on the Data Input port is loaded into the Shift register on the next active Clock transition. When the Load input is Low, the counter responds to the Right/Left control input.

Connections: The Load input is automatically specified when the Data Input port is specified.

•	MSB Serial Input and LSB Serial Input — The MSB Serial Input port is only valid for a Logical style Shift Register when the shift direction is to the right. It allows you to specify a value to be stuffed into the MSB when a right shift has taken place. If you do not specify a value, a value of 0 is used.

The LSB Serial Input port is only valid for an Arithmetic or Logical style Shift Register when the shift direction is to the left. It allows you to specify a value to be stuffed into the LSB when a left shift has taken place. If you do not specify a value, a value of 0 is used.

Connections: The MSB Serial Input and LSB Serial Input ports are optional.

•	Right/Left — The Right/Left Shift control input, when High, enables the left-to-right shifting of data (from MSB to LSB); when Low, it enables the right-to-left shifting of data (from LSB to MSB). Inverting this input reverses the active High/Low definition, but does not change the MSB/LSB definitions or the shift direction.

Connections: The Right/Left pin is automatically specified when the Operation attribute is set to Right/Left.

•	Async. Control — The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute into the shift register independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if you do not specify a value. You can also specify the Asynchronous Value attribute to define the accumulator register's power-on value.

•	Sync. Control — Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the shift register on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, a default value of 0 is used and a warning is issued.

•	Clock Enable — When the Clock Enable input is High, the enabled load and shift actions take place on the next active Clock transition. When Clock Enable is Low, the register contents are unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

•	Clock — If the Clock Enable input is High, the rising clock edge either loads the selected data into the register or performs a shift on the rising (positive) edge. You can use the falling (negative) clock edge by connecting an inverter to the Clock input.

Connections: The Clock input pin is always specified.

Output Pins

At least one of the output pins must be specified.

•	Q_OUT — The Parallel Data output port contains the current value of the register.

Connections: If you do not specify this signal, at least one of the MSB Output or LSB Output pins must be specified.

•	MSB Output — The MSB serial-data (left-shift) output port is used for shifting or for parallel-to-serial data conversions. MS_OUT is equal to the MSB of the shift register.

Connections: This pin is optional.

•	LSB Output — The LSB serial-data (right-shift) output port is used for shifting or parallel-to-serial data conversions. LS_OUT is equal to the LSB of the shift register.

Connections: This pin is optional.

Attributes

•	Operation — Use the Operation attribute to specify one of the three possible types of shift registers: Right, Left, or Right/Left. If you select Right/Left, a Right/Left pin is automatically added to the module.

•	Shift Type — The shift type defines the operation mode of the module. Valid values are Arithmetic, Circular, and Logical.

•	Encoding — You can use this parameter to define the encoding scheme of the data type of the Shift register. Valid values are Signed and Unsigned.

•	Async. Val — The value of the Asynchronous Value attribute defines the power-on contents of the shift register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero.

•	Sync. Val — The Synchronous Value attribute defines the value to which the shift register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin.


About the Simple Gates Module

This section describes the generic bused gate functions of LogiBLOX. Bused gate functions are defined as generalizations of the common logic primitives: AND, INVERT, NAND, NOR, OR, XNOR, and XOR. Except for the INVERT function, each of these can be implemented in three different ways, depending on the number and type of inputs.

The following functions are described for the AND gate, but the same bus expansion criteria apply to the other functions.

You can use the inversions of these logic functions by connecting an INVERT module to the outputs. You can also invert individual inputs (active Low) by using the Inversion Mask attribute associated with each module or specify which individual inputs will be active High with the Decode Mask attribute.

Attributes

•	Logic Type — To select the type of logic, click the radio button located under the type of logic you want. The following descriptions use the AND module for an example, but the logic applies to all of the Simple Gate modules except the INVERT module.

•	Type 1 (One input bus): The Type 1 AND module logically ANDs the individual signals of an input bus of width (n) to produce a single output signal, where (n) varies from 2-64 bits.

•	Type 2 (One input net and one input bus): The Type 2 AND module logically ANDs the individual signals of an input bus of width (n) with a single input to produce an output bus of width (n), where (n) varies from 2-64 bits.

•	Type 3 (2-8 input buses): The Type 3 AND module logically ANDs (m) input buses of width (n), where (m) varies from 2-8 buses and (n) varies from 2-64 bits. The output is a single bus of width (n).

Usage: This attribute does not apply to the INVERT module.

•	Gate Type — Use this attribute to select the type of gate: AND, INVERT, NAND, NOR, OR, XNOR, or XOR.

•	Input Buses — Specifies the number of Input buses (m) of the module.

Usage: This attribute applies to Type 3 modules only. Its value must be in the range 2-8.

•	Style — Style defines the implementation style (area or speed preference).

Usage: This attribute does not apply to the INVERT module. For more information, see the "Implementation Styles" section in the "Understanding Attributes" chapter of the LogiBLOX Guide.

•	Inversion Mask — A High level on this attribute inverts the input of the gate. For more information, see the "Inverting and Decoding Masks for Gated Modules" section of the "Understanding Attributes" chapter in the LogiBLOX Guide.

Usage: This attribute does not apply to Type 3 modules.

•	Decode Mask — A Low level on this attribute inverts the input value. See the "Inverting and Decoding Masks for Gated Modules" section of the "Understanding Attributes" chapter in the LogiBLOX Guide for more information.

Usage: This attribute does not apply to Type 3 modules.


About the Tristate Buffer Module

The Tristate Buffer module synthesizes internal non-inverting tristate buffers.

Tristate buffers are not supported for the XC9500XL family.

Inputs

•	I — The Input data port has the same width as the Output port.

Connections: The Input pin is always specified.

•	Output Enable — For all device families except the XC9500, when the Output Enable input is Low, the Input data passes to the Output. When the Output Enable is High, the Output is in high-impedance.

For the XC9500, this is reversed. When the Output Enable input is High, the Input data passes to the Output. When the Output Enable is Low, the Output is in high-impedance.

This reversal of functionality is indicated by the OE Phase attribute, which is automatically set to Active High for the XC9500 and to Active Low for all other device families.

Connections: The Output Enable pin is always specified.

Note: In the Unified Libraries this pin is labeled T (for Tristate) rather than OE. Also, the bubble is present when OE Phase is Active Low and is absent otherwise.

Outputs

•	O — The Output port reflects the state of the Input port when the Output Enable is Low. When the Output Enable is High, the Output is in high-impedance. Although Tristate Buffer output ports can be tied together, only one port at a time can be active.

Connections: The Output pin is always specified.

Attributes

•	Pull-up Resistors — You can use this attribute to add pull-up resistors to Tristate Buffer outputs that are connected to on-chip buses.

This attribute is not supported for the XC5200 and XC9500 families.

Connections: This is an optional parameter for this module. Use this attribute to specify the number of pull-ups: Single or Double. If this attribute is not specified, no pull-up is added. The double pull-up resistor draws more power than a single resistor but supports faster transition times. See The Programmable Logic Data Book for timing details.

•	OE Phase — This attribute determines whether the Input data passes to the Output port when the Output Enable is High or Low.

Usage: This attribute is set to Active High for the XC9500 family and to Active Low for all other families by default.


About the GUI Messages Window

When you start the LogiBLOX GUI, the LogiBLOX GUI Messages log window is displayed. The log window is a secondary window with scroll bars. LogiBLOX places any output messages generated by the Design Rule Checker, symbol generator, and netlist generator in this window.

Each time you complete a module and click OK, the Module Selector calls the Design Rule Checker (DRC). If the DRC reports no errors, LogiBLOX generates the required output. If the DRC finds errors, LogiBLOX displays the errors in the Messages log window. The module is not generated.

If the DRC finds only warning messages, LogiBLOX displays the warnings in the Messages log window. You can choose to ignore the warnings and generate the symbols by doing the following:

1.	Click Setup on the Module Selector window.

2.	Click Options from the Setup window.

3.	Turn off the "Stop Process on Warning" option.


Adding a Module to Your Design

You can add a LogiBLOX module to your schematic-based or synthesis-based (HDL) design.

LogiBLOX is integrated within the following third-party schematic tools.

Aldec

Viewlogic

Mentor Graphics

Cadence

LogiBLOX is available for the following design environments.

Synopsys FPGA Compiler

FPGA Express

Exemplar Logic

Synplicity (Synplify)

To Add a LogiBLOX Module to Your Schematic Design

1.	To create a new LogiBLOX module, select the "LogiBLOX" choice from the appropriate Add pull-down menu in your design tool to launch the LogiBLOX Module Selector.

2.	Customize and instantiate the required module on the schematic.

3.	To add an existing module, select the "Component" choice from the appropriate Add pull-down menu in your design tool.

A list of available LogiBLOX modules will be displayed when the current working directory is selected from the library list.

4.	Select and instantiate the required module on the schematic.

To Add a LogiBLOX Module to Your Synthesis Design

1.	Select a base module from the LogiBLOX Module Selector dialog box, Module Type list box. The module displays in the Details window.

2.	Modify the module to your specifications, and click OK.

3.	Cut and paste the module instantiation into the HDL file.

Considerations

Each third-party schematic design tool may have different menu names and selections for the steps above. The steps outlined are a guide and may vary in each design tool.


Copying Symbols and Modules

You can copy LogiBLOX symbols and modules from one design to another. If you copy a module within your schematic or add repeated instances to your schematic, the original module and all of its copies share the same .mod file and simulation model. Subsequent modifications to any one of these modules change all copies of that module.

Copying Modules from Another Design

If you copy a module from another design, such as an entire hierarchical module, you must invoke the LogiBLOX program and dismiss it to regenerate the module and create the simulation model for that module. Alternatively, if your design includes several copied modules, you can copy the raw HDL files into the new project directory and reanalyze them in the new environment.


Creating a Module for Schematic Designs

You can create a LogiBLOX module for your schematic-based design environment using your CAE design entry product.

LogiBLOX is integrated into the following third-party schematic tools:

Aldec

Viewlogic

Mentor Graphics

Cadence

To Create a LogiBLOX Module for Your Design

1.	Select the appropriate add or create menu choice in your design tool that launches LogiBLOX. The LogiBLOX Module Selector dialog box displays.

If LogiBLOX does not find a logiblox.ini file in the current directory, the Setup dialog box displays so you can set the project directory, device family, and outputs for LogiBLOX.

2.	Select the LogiBLOX module you want to create from the Module Type drop-down list box. A graphical representation of the module displays in the Details window.

3.	Select (or Deselect) the pins you require for your design.

4.	Enter values in the fields provided, or select attributes from the drop-down list boxes.

5.	Click OK.

Considerations

•	When LogiBLOX completes without errors, the following occurs:

A symbol definition file is generated (.mod) that describes the schematic symbol to be created for the module.

The third-party symbol generator utility is launched to create the LogiBLOX schematic symbol.

The appropriate simulation model is created.

•	From your design entry tool you can place the new LogiBLOX module in your schematic design. See Adding a Module to Your Design for details.


Creating a Module for Synthesis Designs

You can create an instance of a LogiBLOX module in your HDL synthesis-based design environment. In the synthesis-based design environment, LogiBLOX can be used as a stand-alone design product. Also, LogiBLOX is integrated into many third-party synthesis design entry tools and is automatically utilized by synthesis compilers.

LogiBLOX is available for the following design environments:

Synopsys FPGA Compiler

FPGA Express

Exemplar Logic

Synplicity

To Create (Instantiate) a LogiBLOX Module for a Synthesis (HDL) Design

1.	Start LogiBLOX on your PC by double-clicking the LogiBLOX icon or by executing the program from the command line on your workstation. The Module Selector dialog box displays.

If LogiBLOX does not find a logiblox.ini file in the current directory, the Setup dialog box displays so you can set the project directory, device family, and outputs for LogiBLOX. See Using the Setup Dialog Box for more information.

2.	Select the type of module you want to create from the Module Type drop-down list box. A graphical representation of the module displays in the Details window.

3.	Select (or Deselect) the pins you require for your design.

4.	Enter values in the fields provided, or select attributes from the drop-down list boxes.

5.	Click OK.

Considerations

When you have completed the operation, the LogiBLOX program creates a template file containing a VHDL or Verilog component instantiation, an implementation netlist (.ngc) file. The template file contains two pieces of information: pin names and comments detailing the module attributes. The component matches the pin-out of the specified HDL module. The VHDL or Verilog component instantiation can then be cut and pasted into your HDL source.


Using the Setup Dialog Box

You can use the Setup dialog box to choose a third-party vendor, define the project directory for a new module design, select the device family, and choose the type of output you desire for your design.

1.	Select the Vendor tab to choose a third-party vendor and associated bus notation. For most vendors, LogiBLOX automatically assigns a default notation for that vendor.

2.	Select the Project Directory tab and enter the name of a directory in the LogiBLOX Project Directory field where you want the logiblox.ini and all output files to be put.

Select the Browse button if you want to see the Browse Directories dialog box. The Browse Directories dialog box lists your directories in a graphical representation of your directory structure. You can choose a directory from the Browse Directories dialog box.

3.	Select the Device Family tab to define the device family library you want to use during the design of your module.

If you have already set the device family in your third-party design tool, this option is not available.

4.	Select the Options tab to select the types of output files you would like LogiBLOX to generate for you.

5.	Click OK to return to the LogiBLOX Module Selector dialog box.

The settings you choose can be edited during module design by selecting the Setup button on the LogiBLOX Module Selector dialog box.

_______

See Also

Vendor

Project Directory

Device Family

Options


Using the Module Selector Dialog Box

You can use the LogiBLOX Module Selector dialog box to create or modify modules.

To Create a New Module

1.	Select the type of module you want to create from the Module Type drop-down list box. The module you select will graphically display in the Details section of the dialog box.

2.	Type a name in the Module Name field if you want a name other than the name that appears in the field.

3.	Select the bus width from the Bus Width drop-down list box or type in a bus width value in the Bus Width attribute box.

4.	Select (or Deselect) pins from the diagram

5.	Select values from the attribute drop-down list boxes, or type values in the fields.

6.	Click OK.

To Modify an Existing Module

1.	Select the module name from the Module Name drop-down list box. The module you select displays in the Details window.

2.	The type of module is determined by the module name you select. If you want to change the module type, select one from the Module Type drop-down list box.

3.	Select the bus width from the Bus Width drop-down list box, or type in a bus width value in the Bus Width attribute box.

4.	Select (or Deselect) pins from the diagram

5.	Select values from the attribute drop-down list boxes, or type values in the fields.

6.	Click OK.

A dialog window will display asking you if you want to overwrite the existing module. If you do, select Yes. If you don't, select No, and rename the module by typing in a new name in the Module Name field.


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Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
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Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm


Glossary list
Glossary

Accumulator Module

Adder/Subtracter Module

Architecture

Attribute

Browse Dialog Box

Bus Notation

Clock Divider Module

Comparator Module

Component

Constant Module

Counter Module

Data Register Module

Decoder Module

Design Rule Checker (DRC)

Device Family

FPGA

Input/Output Module

Logiblox.ini File

Memories Module

Module Definition File

Module Selector Dialog Box

Multiplexer Module

NCD File

NGC File

Pad Module

Project Directory

Shift Register Module

Simple Gates Module

Speed

Tristate Buffer Module


Accumulator Module definition
Accumulator Module

The Accumulator module takes the data on its B input port and its Carry Input port and adds this data to, or subtracts it from, the current value stored in the accumulator register. It then loads the result back into the accumulator register, making it available at the Q_OUT port.


Adder/Subtracter Module definition
Adder/Subtracter Module

The Adder/Subtracter module adds or subtracts two data inputs and a Carry input. The module provides a Carry Output and an Overflow output to indicate the status of the current arithmetic operation.


Architecture definition
Architecture

Architecture is the common logic structure of a family of programmable integrated circuits. Examples of Xilinx architectures are the XC4000EX, XC5200, and XC9500 devices. A complete Xilinx part number includes architecture (for example, XC4000EX), device (for example, XC4028EX), package (for example, pg299), and speed (for example, -3).


Attribute definition
Attribute

Attributes are used to customize LogiBLOX modules. You can view and change the values of the attributes assigned to a module when you open the module in the Module Selector. When you save a module, the current values of the module's attributes are saved in the module definition file.


Browse Dialog Box definition
Browse Dialog Box

The Browse dialog box lets you select a desired directory from a graphical representation of the current directory structure.


Bus Notation definition
Bus Notation

Different vendors of third-party software use different notations to reference a bus index. LogiBLOX automatically assigns the default notation for the vendors listed in the Vendor panel of the Setup window.


Clock Divider Module definition
Clock Divider Module

The Clock Divider module uses a Linear-Feedback-Shift-Register (LFSR) counter and decoder to generate an output pulse train that is a function of the clock input and the control attributes.


Comparator Module definition
Comparator Module

The Comparator module compares the magnitude and equality of two values.


Component definition
Component

A component is an instantiation or symbol reference from a library of logic elements that can be placed on a schematic.


Constant Module definition
Constant Module

The Constant module forces a constant value onto a bus. The value can only be changed at design time.


Counter Module definition
Counter Module

The Counter module generates a sequence of count values determined by the selected encoding and the status of the control inputs.


Data Register Module definition
Data Register Module

The Data Register module stores the data applied to its D_IN port on active Clock transitions.


Decoder Module definition
Decoder Module

The Decoder module converts unsigned binary data on the Select port to a 1-of-n output on the D_OUT port.


Design Rule Checker definition
Design Rule Checker (DRC)

Physical DRC is a series of tests to discover physical errors and some logic errors in your design.


Device Family definition
Device Family

A device family is a group of devices that are architecturally related. For example, the XC4000E device family contains the XC4003E, XC4005E, and XC4028E devices. A complete Xilinx part number includes architecture (for example, XC4000EX), device (for example, XC4028EX), package (for example, pg299), and speed (for example, -3).


FPGA definition
FPGA

An FPGA (Field Programmable Gate Array) is a class of integrated circuits pioneered by Xilinx that can be programmed using the Xilinx development system software. The FPGA is programmable after it has been manufactured and delivered to the end user.


Input/Output Module definition
Input/Output Module

Input/Output modules represent the physical pins on a device that are actually used in a design. There are three types of I/O modules: input modules, output modules, and bi-directional modules.


Logiblox.ini File definition
Logiblox.ini File

The logiblox.ini file contains the information recorded on the initial setup dialog box. At start-up, LogiBLOX reads this initialization information and uses it to configure the Module Selector.


Memories Module definition
Memories Module

The Memories module is used to create ROM, RAM, Synchronous RAM, and Dual Port RAM modules. These modules store information in the form of words in a tabular fashion.


Module Definition File definition
Module Definition File

A module definition file defines the functionalities of a particular LogiBLOX module. It specifies the module type, module name, device family, attributes, and pin connections. The file has a .mod extension.


Module Selector Dialog Box definition
Module Selector Dialog Box

The Module Selector dialog box is used to create a new LogiBLOX module, or to modify an existing design module.


Multiplexer Module definition
Multiplexer Module

The Multiplexer module selects one input from two or more inputs and routes it to the output port.


NCD File definition
NCD File

An NCD file is the output design file from the MAP and PAR programs and represents the physical design.


NGC File definition
NGC File

An NGC file is the implementation netlist generated by LogiBLOX for the LogiBLOX module.


Pad Module definition
Pad Module

The Pad module can be connected to an Input/Output module to simulate the connection to the pin pad.


Project Directory definition
Project Directory

The Project Directory panel on the Setup dialog box allows you to choose the directory path to which the logiblox.ini configuration file and all output files will be stored.


Register Module definition
Shift Register Module

The Shift Register module shifts data to the right or left. The module can be set up as a logical, circular, or arithmetic shift register. The input and output data can be either serial or parallel.


Simple Gates Module definition
Simple Gates Module

The Simple Gates module implements the common logic primitives AND, INVERT, NAND, NOR, OR, XNOR, and XOR.


Speed definition
Speed

Speed is a function of net types, CLB density, switching matrices, and architecture. A complete Xilinx part number includes architecture (for example, XC4000Ex), device (for example, XC4028EX), package (for example, pg299), and speed (for example, -3).


Tristate Buffer Module definition
Tristate Buffer Module

The Tristate Buffer module synthesizes internal non-inverting tristate buffers.