Copyright: HH Bridge(c) Bristol Technology Inc. 1993


Overview

The Flow Engine is the portion of the Xilinx Development System that allows you to implement your design. The Flow Engine first translates the design file into the Xilinx internal database format (NGD). It then implements your design, which includes mapping, placing and routing for Field Programmable Gate Arrays (FPGAs) and fitting for Complex Programmable Logic Devices (CPLDs). Finally, it generates bitstream data. The Flow Engine allows you to easily process your design, control the implementation of your design, and guide your implementation revisions.


Design Implementation

The Flow Engine allows you to control the implementation of your design in different ways. For example, if you are new to Xilinx software or want to quickly check your design, you can run the Flow Engine automatically from the Alliance Series Design Manger or Foundation Series Project Manager. However, if you are an experienced user, you can open the Flow Engine and use the Flow menu or run control buttons to execute steps separately. When you use the Flow Engine in this way, it is called the interactive Flow Engine. You can also fine tune your design by modifying your implementation, simulation, and configuration options. You can access these options through the Options command.

If you use the interactive Flow Engine, you can control how far to process your design by using the Stop After command from the Setup menu. In the Stop After dialog box, select a step as your target break point. For example if you want to map, place, and route your design, but not create a timing simulation file or device programming file, select Stop After Place&Route. A stop sign indicates where the process flow will stop.

Following are the steps run by the Flow Engine.

Note:  See the Development System Reference Guide for information on some of the programs the Flow Engine runs to accomplish these steps.

Translate

During this step, the Flow Engine merges all of the input netlists. Using the Options command, you can set implementation options in the Translate tab to control processes that occur during this step. The Flow Engine accomplishes this step by running NGDBuild.

Map (FPGA)

During this step, the Flow Engine maps a logical design to a Xilinx FPGA. The input is an NGD file, which contains a logical description of the design and macro library (NMC) files. The Flow Engine first performs a logical Design Rule Check (DRC) on the design in the NGD file. It then maps the logic to the components in the target Xilinx FPGA. The output design is an Native Circuit Description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. You can control aspects of the Map step by setting implementation options using the Options command. The Flow Engine accomplishes the Map step by running the MAP program.

Place&Route (FPGA)

During this step, the Flow Engine takes the NCD file produced during Map and places and routes the design to produce a routed NCD file. The output NCD file can also act as a guide file if you place and route the design again. You can control aspects of the Place and Route step by setting implementation options using the Options command. To accomplish this step, the Flow Engine runs the PAR program.

Fit (CPLD)

During Fit, the Flow Engine launches the CPLD Fitter to minimize and collapse the combinational logic of your design so that it requires the least number of macrocell and product term resources. It also partitions and maps your design to fit within the architecture of the CPLD. You can control aspects of this step by setting implementation options using the Options command.

Timing (Sim)

The Flow Engine runs this step to produce timing simulation data. The data that is produced depends on the simulation options you set using the Options command. To accomplish this step, the Flow Engine runs NGDAnno and one of the following tools.

•	NGD2EDIF

•	NGD2VER

•	NGD2VHDL

Configure (FPGAs)

After the design has been completely routed, the Flow Engine configures the device so that it can execute the desired function. Using a fully routed NCD file as input, it produces a configuration bitstream, a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells, or it can be used to create a PROM file. You can control aspects of this step by setting configuration options using the Options command. The Flow Engine accomplishes this step by running BitGen.

Bitstream (CPLDs)

During this step, the Flow Engine produces a JED programming file. The JTAG Programmer uses this file to configure CPLD devices. You can control aspects of this step by setting implementation options using the Options command.

Note:  For more information on setting implementation, simulation, and configuration options, see Specifying Implementation Flow Options.


Smart Flow Engine

When the Flow Engine is first invoked, it automatically looks for changes made to certain files. If the Flow Engine detects changes, it restarts the flow for the implementation revision as follows. This feature is called the Smart Flow Engine.

•	If a previously set target break point has already been reached at the time you launch the Flow Engine, the Smart Flow Engine removes the break point and implements the next process in the flow.

•	If any of the following changes are made, the Smart Flow Engine determines which process to rerun.

•	Changes to implementation flow options from the Options dialog box

•	Changes to design, constraints, guide, or output files

The following table shows which flow process will be rerun if you make changes to a particular file.

	File Changed	Process Rerun
	design_name.ucf	Translate
	design_name.ngd, design_name.mfp	Map
	map.ncd, guide.ncd	Place&Route
	design_name.ncd	Timing (Sim) (FPGA)
	design_name.ncd	Configure (FPGA)
	design_name.ngd, design_name.gyd	Fit (CPLD)
	design_name.vm6	Timing (CPLD)
	design_name.vm6	Bitstream (CPLD)
Note:  The Flow Engine checks for changes related to successfully completed processes. If a process did not complete successfully, the Flow Engine does not look for changes related to this process but automatically restarts the flow at this process or, if appropriate, at a previous process. If the Flow Engine is already open and you want to check for changes, use the Update Flow command from the Setup menu.


Flow Engine Window

The main window is the background against which all other windows are displayed. This window consists of the following parts.

Note:  Menus, dialog boxes, and parts of the application window are documented as they appear on a UNIX workstation. Differences between the PC and workstation applications are documented if there is a difference in operation between the two platforms.

Title Bar

This area displays the program name followed by the name of the currently loaded design.

Menu Bar

This area contains the menus that control the operation of the Flow Engine.

Toolbar

This area contains toolbar buttons that provide access to frequently used commands.

Processing Target

Select the desired run target by using the Stop After command from the Setup menu. Select a processing target such as Map or Place&Route. After you select a target, a stop sign appears after the corresponding process indicator icon to show where processing will stop. For more information, see Setting a Run Target.

Process Indicators

These icons how you which Flow Engine step is currently processing. A stop sign indicates the flow will stop at that point in the flow. The arrows between each step turn black after the previous step is completed.

The process indicator icons differ depending on the target device family. This is determined when you open a new project. For an FPGA, the icons are Translate, Map, Place&Route, Timing (Sim), and Configure. For a CPLD, the icons are Translate, Fit, Timing (Sim), and Bitstream.

Progress Bar

Below each process indicator, a progress bar shows the status of each processing step, whether Running, Completed, Aborted, or Failed.

Message Log Window

This area displays output from underlying programs that the Flow Engine is running.

Run Control Buttons

The run control buttons control the processing steps.

Status bar

The status bar displays the name of the target part, user constraints file, and user specified guide file currently being used by the Flow Engine.


Using Dialog Boxes

Many menu commands display dialog boxes in which you can enter information and set options.

Common Fields

The fields shown in the following table are common to most dialog boxes.

Dialog Box Field	Function
OK	Closes the dialog box and implements the intended action according to the settings in the dialog box
Cancel	Closes the dialog box without effecting any action
Help	Displays information on that particular dialog box


How to Use Help

This page is a quick reference guide to the Flow Engine Help.

Help Topics Organization

Getting Started	An overview of the Flow Engine and instructions for using the interface
Procedures	Step-by-step instructions for performing tasks
Commands	Descriptions of commands available from menus and buttons
Help on Help	Instructions for using help and how to access it
Reference	Glossary, trademark, technical support, and additional resource information
Summary of Help Operations

To	Do this
Go to related topics	Click underlined words
Go to the Help Topics	Click Help Topics
Search in the Help	Click Index or Find, select a topic
Scroll in the Help window	Move the scroll bars with the mouse
Return to the previous topic	Click Back
Return to any previous topic	From the Options menu, select Display History Window and select a topic
Browse forward	Click Browse>>
Browse backward	Click <<Browse
Get detailed help on Help	On workstation, select How to Use Help from the Help menu
Close the Help window	Select Exit from the Help File menu
Printing Help Topics	On the workstation, select How to Use Help from the Help menu, and select Configure a Printer from the How To list


Obtaining Help

You can obtain help on commands and procedures by clicking the Help button in the toolbar, clicking the Help button in dialog boxes, or pressing the F1 key. The Help button in the toolbar and in some menu command dialog boxes provides context-sensitive help.

Help Menu

The Help menu displays the following commands.

•	Help Topics lists the online help topics available. From the opening screen, you can jump to command information or step-by-step instructions. After you open help, you can click the Help Topics button (first button on the left) in the Help window whenever you want to return to the help topics list.

•	Online Documentation provides access to the Xilinx Software Manuals Online.

•	About Flow Engine displays a popup window that shows the version number of the software.

Toolbar

You can obtain context-sensitive help from the toolbar.

1.	Click the Help button.

The cursor changes to a question mark.

2.	Click once with the left mouse button on the menu item or toolbar button for which you want information.

Online help information about the selected command appears in a popup window.

Help Button in Dialog Boxes

Many of the dialog boxes have a Help button that you can click to obtain help on that dialog box. A window opens that displays information.

F1 Key

Pressing the F1 key when the cursor is placed on a dialog box displays help on that dialog box. The F1 key functions the same as selecting Help Topics from the Help menu, if no dialog boxes are displayed.


Specifying Implementation Flow Options

You can specify options that control how the Flow Engine implements a design, configures a device, creates netlist files, and generates reports, timing data, and configuration data. The available options depend on the target device family.

You can specify these options by choosing settings within the Options dialog box. You can set implementation, simulation, and configuration options. The implementation options control how the software translates, maps, places, routes, and optimizes an FPGA design and how it translates and fits a CPLD design. The simulation options control the creation of netlists in terms of Xilinx primitives, allowing you to perform simulation and back-annotation. The configuration options define the initial configuration parameters, the startup sequence, and readback capabilities.

Changes you make in the Options dialog box are applied to the implementation revision that was selected when you invoked the dialog box. The Flow Engine picks up changes after the currently running process is finished if a flow is running, or when you implement your design if no flow is running.

To specify implementation flow options

1.	To open the Options dialog box, select Options from the Setup menu or click the Set Options toolbar button.

2.	If you are targeting an FPGA, do the following in the Options dialog box.

a.	Select a Place & Route Effort Level setting. A setting closer to High Effort provides better place and route results at the expense of longer run times.

b.	To modify the default implementation options, click the Edit Options button to the right of the Implementation field. These options affect the Translate, Map, and Place&Route steps in the implementation flow.

c.	To create timing simulation data, select one of the simulators in the drop-down list box next to the Simulation field. If you want to edit the default option settings, click the Edit Options button to the right of the Simulation field. Select OFF if you do not want to generate simulation data.

Note:  The Edit Options button is disabled if you set Simulation to OFF.

d.	To modify the default configuration options, click the Edit Options button to the right of the Configuration field. These options affect the Configure step in the implementation flow for FPGAs. Select OFF if you do not want to generate configuration data.

Note:  The Edit Options button is disabled if you set Configuration to OFF.

e.	Click OK.

3.	If you are targeting a CPLD, do the following in the Options dialog box.

a.	In the Implementation Options field, select Area, Balanced, or Speed for the CPLD Optimization Style, or select User Defined and choose a set of default options you can edit from the drop-down list.

b.	To edit your User Defined options, click the Edit Options button. These options affect the Translate, Fit, and Bitstream steps in the implementation flow.

c.	To create timing simulation data, select one of the simulators in the drop-down list box next to the Simulation field. If you want to edit the default option settings, click the Edit Options button to the right of the Simulation field. Select OFF if you do not want to generate simulation data.

Note:  The Edit Options button is disabled if you set Simulation to OFF.

d.	Click OK.

4.	Click OK to maintain your settings and exit the Options dialog box.


Implementing a Design

If you want to control the implementation processes, you can implement your design in separate steps from the Flow Engine. Implementing your design from the Flow Engine allows you to control aspects of the flow such as updating the implementation status, enabling flashing icons, and setting run targets. You can implement your design with default implementation flow options set, or you can set your own values.

To implement a design in separate steps

1.	If you want to set implementation flow options, follow the procedure in Specifying Implementation Flow Options.

2.	If you want to set a run target, enable flashing icons, or update the implementation status or flow, use the procedures in the following sections.

Setting the State of the Flow

Enabling Flashing Icons

Setting a Run Target

Updating the Flow

3.	Do one of the following.

•	In the Flow Engine window, select Run from the Flow menu to run through the entire implementation process.

•	Select Step from the Flow menu to single step through the implementation process.

Note:  If you stop processing while the Flow Engine is running the Place&Route step, the Flow Engine asks whether you want to save the data that has processed to this point or exit immediately without saving the data.


Viewing Reports

The Flow Engine generates various reports which you can view in the Report Browser.

To view reports

1.	Select Report Browser from the Utilities menu or click the Browse Reports toolbar button.

The Report Browser window opens and displays reports for the active implementation revision.

2.	In the Report Browser window, double-click the report icon for the report you want to view.

Note:  The icons change appearance to indicate whether or not you have read a report. A yellow mark in the upper left corner of the report icon indicates that the report has been generated but not read. A report icon without this mark indicates that the report has been generated and read.


Producing Timing Reports

You can generate timing reports after you implement your design using the Produce Timing Reports command. You can use this command if Map for FPGAs or Fit for CPLDs has completed successfully. The timing report created is based on the state of your design when you run the command.

Note:  If you select the appropriate options in the Timing Reports tab of the Implementation Options dialog box before you implement your design, the software automatically generates timing reports with the Map and Place&Route steps. See Specifying Implementation Flow Options for more information on making settings in the Implementation Options dialog box.

To produce timing reports

1.	Select Produce Timing Reports from the Utilities menu.

2.	In the Produce Timing Report dialog box, select a timing report format.

The timing report is created and placed in the Report Browser.

_______

See also

Viewing Reports


Producing Timing Simulation Data

The Flow Engine can produce timing simulation data for use in a third party simulation tool. This data is produced for the selected implementation revision.

To produce timing simulation data

1.	To open the Options dialog box, select Options from the Setup menu or click the Set Options toolbar button.

2.	Select one of the simulators in the drop-down list box next to the Simulation field.

3.	To edit the default option settings, click the Edit Options button to the right of the Simulation field.

Note:  If you set Simulation to OFF, no timing simulation data is created and the Edit Options button is disabled.

4.	Make settings in the Simulation Options dialog box and click OK.

5.	Click OK.

When you implement the design, the Flow Engine produces timing simulation data files. Each time the data is produced, it is automatically exported to your design directory. You can now use these files to simulate the design with a supported third party simulation tool.


Setting the State of the Flow

Use the Advanced command in the Setup menu to set the state of the implementation flow.

Note:  This setting is not used in normal Flow Engine use. It is used if some processing on the design was performed outside of the Flow Engine framework, such as in the FPGA Editor. It can also be used if you ran the Flow Engine Step Back button by mistake and want to reset the implementation state to its original state.

To set the state of the flow

1.	Select Advanced from the Setup menu.

2.	Select a state from the Implementation State list box to update the Flow Engine as to which implementation state was last completed.

3.	Click OK.

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See also

Implementing a Design


Enabling Flashing Icons

Use the Advanced command in the Setup menu to enable flashing icons that indicate a process step is being processed. A trade-off of this feature is that flashing icons slow down the implementation process.

To enable flashing icons

1.	Select Advanced from the Setup menu.

2.	Select Use Flashing to Indicate Heartbeat.

3.	Click OK.

_______

See also

Implementing a Design


Setting a Run Target

The Flow Engine flow includes several process steps. You can specify that the flow stop at a certain point with the Stop After command. When specified, the Flow Engine does not process beyond that point. You do not need to set a run target for typical Flow Engine use. By default, the Flow Engine processes all the steps.

To set a run target

1.	Select Stop After from the Setup menu or click the Set Target toolbar button.

2.	Select the desired run target from the Stop After dialog box.

3.	Click OK.

The Flow Engine stops processing after the specified point. The red stop sign visually indicates the run target.

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See also

Implementing a Design


Updating the Flow

When the Flow Engine is first invoked, it automatically looks for changes made to certain files. If changes are detected, the Flow Engine resets the flow for the implementation revision. If the Flow Engine is already open and you want to check for changes, use the Update Flow command from the Setup menu.

To update the flow

1.	Select Update Flow from the Setup menu.

The Flow Engine resets the flow if certain file changes are detected.

2.	Do one of the following.

•	In the Flow Engine window, select Run from the Flow menu to run through the entire implementation process.

•	Select Step from the Flow menu to single step through the implementation process.

_______

See also

Implementing a Design


Implementation, Simulation, and Configuration Options Dialog Boxes

The options in the Implementation, Simulation, and Configuration Options dialog boxes vary depending on the device family. Click the following links for more information.

•	For information on the settings in the Implementation Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

XC9500

•	For information on the settings in the Simulation Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

XC9500

•	For information on the settings in the Configuration Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200


Placing and Routing Non-Timing Driven Designs

When targeting the Virtex and Spartan2 device families on designs that are run without timing constraints, you may notice lower design performance results from the Place and Route process. To get a more realistic estimate of how your design will perform without timing constraints applied, do the following.

To place and route non-timing driven designs

1.	Set your run target to Place&Route.

2.	Select Run from the Flow menu.

3.	After the Flow Engine has finished routing your design, select FPGA Re-entrant Route from the Setup menu.

4.	In the FPGA Re-entrant Route dialog box, specify the number of Cleanup Passes to run.

5.	Click OK.

6.	Select Step Back from the Flow menu.

7.	Select Run from the Flow menu.

8.	Check the P&R Report and Post Layout Timing Report in the Report Browser for improved performance results.


Running Re-Entrant Routing on FPGAs

Use re-entrant routing to further route an already routed design. The design maintains its current routing and additional routing is added.

You can reroute connections by running cost-based cleanup, delay-based cleanup, and additional re-entrant route passes. Cleanup passes attempt to minimize the delays on all nets and decrease the number of routing resources used. Cost-based cleanup routing is faster while delay-based cleanup is more intensive.

Re-entrant routing offers the following advantages.

•	Cleanup passes significantly reduce delays, especially on non-timing driven runs.

•	For timing-driven runs, cleanup passes can improve timing on elements not covered by timing constraints.

•	For designs which do not meet timing goals by a narrow margin, delay-based cleanup passes can reorganize routing so that additional re-entrant route passes enable the design to meet timing goals.

Note:  The FPGA Re-entrant Route command is supported for the FPGA device families only.

To run re-entrant routing

1.	Select FPGA Re-entrant Route from the Setup menu.

2.	In the FPGA Re-entrant Route dialog box, select Allow Re-entrant Routing to route the previously routed design again.

3.	Select a number between 1 and 5 for the Run _ Cost-Based Cleanup Passes field.

These cleanup passes reroute nets if the new routing uses less costly resources than the original configuration. Cost is based on pre-determined cost tables. Cost-based cleanup usually has a faster runtime than the delay-based cleanup, but does not reduce delays as significantly.

Note:  If you run both cost-based and delay-based cleanup passes, the cost-based passes run first.

4.	Select a number between 1 and 5 for the Run _ Delay-Based Cleanup Passes field.

These cleanup passes reroute nets if new routing will minimize the delay for a given connection. Delay-based cleanup usually produces faster in-circuit performance.

5.	Select a number between 1 to 2000 for the Run _ Re-entrant Route Passes field to run additional re-entrant routing passes.

These passes are either timing driven or non-timing driven depending on whether you specified timing constraints.

6.	Select Use Timespecs During Re-entrant Route if you want to reroute the design within the specified timing constraints in your design file.

7.	Click OK.


Abort (Flow Menu)

Warning:  The Abort command is an immediate abort. When you select Abort, all data produced by the currently running process is lost.

Use this command to terminate the current Flow Engine execution. If you use this command while the Place&Route step is processing, the Abort dialog box appears.

Note:  To set a run target, use the Stop After command.


Abort Dialog Box

Ignore interrupt and continue processing

Select this option to close the dialog box and continue implementing your design.

Exit program normally at next checkpoint

Select this option to close the dialog box and continue processing until the next stopping point in the Place&Route step. If you select this option, the Flow Engine saves the best results to this point.

Exit program immediately

Select this option to close the dialog box and immediately abort the Place&Route process.


About Flow Engine (Help Menu)

Use this command to display program information, including the software version and serial number, and the copyright notice. A dialog box displays this information.


Advanced (Setup Menu)

Use this command to open the Advanced dialog box. Set the options in this dialog box to set the implementation state and enable flashing icons.

_______

See also

Setting the State of the Flow

Enabling Flashing Icons


Advanced Dialog Box

Use this dialog box for the following.

Setting the State of the Flow

Enabling Flashing Icons

Implementation State

Use this option to update the Flow Engine to which implementation state was last completed. Most users will not need to modify this setting.

In normal Flow Engine use, do not use this setting to change the implementation state. This setting is typically used if some processing on the design was performed outside of the Flow Engine. For example, if the design was routed using the FPGA Editor, the Implementation State should be set to Routed to inform the Flow Engine that this implementation state is complete. In addition, this setting is useful for restoring an implementation state when you have stepped forward or back too far.

Use Flashing to Indicate Heartbeat

Use this option to enable flashing process icons to indicate processing activity in the Flow Engine. This option is useful for providing feedback that the Flow Engine is running. Enabling this option may slow down the implementation process.This option is off by default.

_______

See also

Advanced (Setup Menu)


Close (Flow Menu)

Use this command to close the Flow Engine window. Use this command when you are finished implementing the design or no longer need the Flow Engine.


Command History (Utilities Menu)

Use this command to open the Command History utility and display the commands and options that have already been run in the flow for the current implementation revision. This command is useful for reviewing the commands and options that were used while executing the flow.


Command History Utility

Mode

Process

This mode displays high level flow information about previously executed commands, such as optimize, map, place, and route.

Command Line

This mode displays the executed operating system commands and command line options.

Show Date and Time

This mode displays the date and time that the commands were run on the selected implementation revision.

Close

Click Close to exit the utility.

_______

See also

Command History (Utilities Menu)


Command Preview (Utilities Menu)

Use this command to open the Command Preview utility and display the commands and options that remain to be run in the flow for the current implementation revision. This command is useful for determining which commands will be executed in the flow and whether the correct options have been set.


Command Preview Utility
Command Preview Utility Options

Mode

Process

This mode displays high level flow information about the commands, such as optimize, map, place, and route, that will be executed.

Command Line

This mode displays more detailed information about the commands and command options that will be executed.

Update View

This option updates the command preview information to reflect any changes made in Flow Engine option settings since opening the Command Preview window.

Close

Click Close to exit the utility.

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See also

Command Preview (Utilities Menu)


Font (View Menu)

Use this command to specify the font type and font size for the text displayed in the Flow Engine message log window. This command opens a standard font dialog box in which you can make these settings.


FPGA Re-Entrant Route (Setup Menu)

Use this command to reroute a previously routed design. This command opens the FPGA Re-entrant Route dialog box which allows you to set up the conditions for your re-entrant routing. You can set the number of re-entrant routing and cleanup passes and set whether to use timing constraints for the re-entrant route process.

Note:  This command is supported for the FPGA device families only.

_______

See also

Running Re-Entrant Routing on FPGAs


FPGA Re-Entrant Route Dialog Box

Use this dialog box for the following.

Running Re-Entrant Routing on FPGAs

Placing and Routing Non-Timing Driven Designs

Allow Re-entrant Routing

Use this option to further route an already routed design. The router reroutes some connections to improve the timing score or to finish routing unrouted nets. This option is useful if you want to manually route a portion of the design and then automatically route the design or if you want to run additional delay reduction passes.

Re-entrant Route Options

You can set the number of re-entrant routing and cleanup passes. If you run both cost-based and delay-based cleanup passes, the cost-based passes will run before the delay-based passes. Running more than two cleanup passes rarely provides improved results. You can also specify whether you want to use timing constraints during the re-entrant routing process.

Run _ Cost-Based Cleanup Passes

Cost-based cleanup makes rerouting decisions by assigning weighted values to the factors affecting delay times between sources and nets. Set the number of cost-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 1.

Run _ Delay-Based Cleanup Passes

Delay-based cleanup makes rerouting decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Run _ Re-entrant Route Passes

Re-entrant routing runs additional timing driven or non-timing driven routing passes, depending on whether you specified timing constraints. Placement and routing from previous place and route runs are preserved. Set the number of re-entrant route passes you want to run by choosing a number from 1 to 2000. The default is Auto.

Use Timespecs During Re-entrant Route

The Flow Engine uses timing constraints in the design file to route the design within the specified constraints. By default, this option is on.

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See also

FPGA Re-entrant Route (Setup Menu)


Help Topics (Help Menu)

Use this command to display the opening screen of the Help. From the opening screen you can jump to step-by-step instructions and to various types of reference information.

After you open help, you can click the Help Topics button in the Help window whenever you want to return to the opening screen of Help.

_______

See also

How to Use Help


Online Documentation (Help Menu)

Use this command to open the software manuals in the default Web browser.


Options (Setup Menu)

Use this command to open the Options dialog box. This dialog box allows you to set options used in the implementation flow. Changes made in this dialog box apply to the selected implementation revision.

Note:  If you open the Options dialog box from the Flow Engine while a step is running, the changes are picked up when the step is done. Subsequent steps are run with the changes you made.

_______

See also

Specifying Implementation Flow Options

Producing Timing Simulation Data


Options Dialog Box

The Options dialog box allows you to set implementation and simulation options for FPGAs and CPLDs and configuration options for FPGAs. The dialog box differs for FPGAs and CPLDs. Click one of the following links for more information.

Options Dialog Box (FPGA)

Options Dialog Box (CPLD)


Options Dialog Box (FPGA)

Use this dialog box for the following.

Specifying Implementation Flow Options

Producing Timing Simulation Data

Place & Route Effort Level

Use this option to specify the algorithms that the placer and router use to place and route a design. Use the Place & Route Effort Level slider bar to select an effort level setting. A setting closer to High Effort provides better place and route results at the expense of longer run times.

Program Options

Implementation

Select a set of implementation options to use from the Implementation drop-down list. Implementation options control how the software translates, maps, places, routes, and optimizes a design. These options affect the Translate, Map, and Place&Route steps in the implementation flow. A set of default implementation options and any option templates you created appear when you click this drop-down list.

Click the Edit Options button to the right of the Implementation drop-down list to open the Implementation Options dialog box. The options in this box depend on the target device family. For information on the implementation options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

Simulation

Select one of the simulators or a template you created from the drop-down list box to produce timing simulation data. This data is produced after the design is placed and routed. If you do not want to produce timing simulation data, select OFF.

Click the Edit Options button to the right of the Simulation drop-down list to open the Simulation Options dialog box. Simulation options control the creation of netlists in terms of the Xilinx primitive set, which allow you to simulate and back-annotate your design. In back-annotation, physical design data is distributed back to the logic design to perform back-end simulation. You can perform front and back-end simulation on both pre- and post-routed designs. For information on the simulation options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

Configuration

Select a set of configuration options to use in this implementation from the Configuration drop-down list. Configuration options control the configuration parameters of a device, the startup sequence, and readback capabilities. These options affect the Configure step in the implementation flow. A set of default configuration options and any option templates you created appear when you click on this drop-down list. Selecting a set of options produces configuration data after design implementation. The configuration data is used to program a device. Select OFF if you do not want to produce configuration data.

Click the Edit Options button to the right of the Configuration drop-down list to open the Configuration Options dialog box. The options in this dialog box depend on the target device family. For information on the configuration options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

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See also

Options (Setup Menu)


Options Dialog Box (CPLD)

Use this dialog box for the following.

Specifying Implementation Flow Options

Producing Timing Simulation Data

Implementation Options

Select a CPLD Optimization Style, whether optimized for area, a balance of both area and speed, or speed. Implementation options control how the software translates and fits a design. These options affect the Translate, Fit, and Bitstream steps in the implementation flow.

If you want to use your own options, click User Defined as your CPLD Optimization Style and select the default set of options or an option template you created from the drop-down list box. If you want to edit these user defined options, click the Edit Options button to the right of the drop-down list to open the Implementation Options dialog box. See XC9500 Implementation Options Dialog Box for more information.

Simulation Options

Select one of the simulators or a template you created in the drop-down list box to produce timing simulation data. This data is produced after the design is fitted. If you do not want to produce timing simulation data, select OFF.

Click the Edit Options button to the right of the Simulation drop-down list to open the Simulation Options dialog box. Simulation options control the creation of netlists in terms of the Xilinx primitive set, which allow you to simulate and back-annotate your design. In back-annotation, physical design data is distributed back to the logic design to perform back-end simulation. You can perform front and back-end simulation on both pre- and post-fitted designs. See XC9500 Simulation Options Dialog Box for more information.

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See also

Options (Setup Menu)


Produce Timing Report (Utilities Menu)

Use this command to generate timing reports. You can use this command if at least Map (for FPGAs) or Fit (for CPLDs) has completed successfully. The type, title, and file name of the report depend on the state of your design when you run this command. You cannot change the file name of the report. The following table shows the report that is generated given a particular state. The timing reports are placed in the Report Browser when complete.

State	File Name	Title
Mapped (FPGA)	map_number.twr	Logic Level Timing Report #number
Routed (FPGA)	design_name_number.twr	Post Layout Timing Report #number
Fitted (CPLD)	design_name_number.twr	Post Fitting Timing Report #number
Timed	design_name_number.twr	Post Layout Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD)
Implemented	design_name_number.twr	Post Bitgen Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD)
 This command opens the Produce Timing Report dialog box in which you can set the report format.

Note:  If you step back over a state that was necessary to generate a report, the report associated with that state is removed from the Report Browser. To restore the state and the associated reports, use the Step command from the Flow menu in the Flow Engine.

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See also

Producing Timing Reports


Produce Timing Report Dialog Box

This command opens one of the following dialog boxes, depending on whether you are targeting an FPGA or CPLD. Use this dialog box to set the report format.

Produce Timing Report Dialog Box (FPGA)

Produce Timing Report Dialog Box (CPLD)


Produce Timing Report Dialog Box (FPGA)

Use this dialog box for the following.

Producing Timing Reports

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist. The default setting is 3.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSETs for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option. This is the default format.

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See also

Produce Timing Report (Utilities Menu)


Produce Timing Report Dialog Box (CPLD)

Use this dialog box for the following.

Producing Timing Reports

Summary

Select Summary to generate a report that contains summary information and design statistics.

Detailed

Select Detailed to generate a report that lists delay information for all nets and paths.

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See also

Produce Timing Report (Utilities Menu)


Project Notes (Utilities Menu)

Use this command to open a standard text editor window in which to make notes for the current project.


Report Browser (Utilities Menu)

Use this command to view reports. This command opens the Report Browser utility. This utility contains icons that represent the reports generated by the Flow Engine.

The icons change appearance to indicate whether or not you have read a report. A yellow mark in the upper left corner of the report icon indicates that the report has been generated but not read. A report icon without this mark indicates that the report has been generated and read. To read a report, double-click the report icon.

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See also

Viewing Reports


Run (Flow Menu)

Use this command to start the Flow Engine. The Flow Engine processes until it completes the target process or reaches the end of the flow.

You can set a target with the Stop After command from the Setup menu. To step the Flow Engine through a single operation, use the Step command from the Flow menu.

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See also

Implementing a Design


Status Bar (View Menu)

Use this command to show or hide the status bar.


Step (Flow Menu)

Use this command to run the next operation in the processing flow. This command allows you to single-step through the implementation process.

To run the Flow Engine through the complete process or until it completes a target process, use the Run command or the Run button at the bottom of the Flow Engine window.

Note:  You can use the Implementation State option in the Advanced dialog box to restore an implementation state when you have stepped forward too far.

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See also

Implementing a Design


Step Back (Flow Menu)

Use this command to go back one step in the processing flow. You can use this command to backup and then rerun a step using different options. The data is not deleted until you overwrite it by rerunning the step.

Note:  You can use the Implementation State option in the Advanced dialog box to restore an implementation state when you have stepped back too far.


Stop After (Setup Menu)

Use this command to specify a break point where the Flow Engine will stop processing. Choose a process from the Stop After dialog box. For instance, if you want to map, place, and route your design but not create a timing simulation file or device programming file, select Stop After Place&Route.


Stop After Dialog Box

Use this dialog box for the following.

Setting a Run Target

Stop After

Select a target break point from the list box. When working with an FPGA design the available targets are Translate, Map, Place&Route, Timing (Sim), and Configure. When working with a CPLD design the available targets are Translate, Fit, Timing (Sim), and Bitstream. The selected target appears in the Stop After field.

Note:  To abort a currently running process, use the Abort command.

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See also

Stop After (Setup Menu)


Toolbar (View Menu)

Use this command to show or hide the toolbar.


Update Flow (Setup Menu)

Use this command to determine whether a change has been made that would cause a successfully run step to be rerun. If the Flow Engine determines that a process needs to be rerun, it presents a confirmation dialog box. Click Yes and the flow is reset to run the appropriate step next.

Note:  The Flow Engine will not automatically begin processing the appropriate step, you must select Run or Step from the Flow menu to begin the implementation process.

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See also

Smart Flow Engine

Updating the Flow


Toolbar

The toolbar provides convenient access to frequently used commands. Click once on a toolbar button to execute a command. The following section briefly describes each toolbar button and, where appropriate, provides a link to the corresponding menu command.

When you position the mouse pointer over a toolbar button, a short description, called a tool tip, appears next to the button. A longer description appears in the status bar at the bottom of the main window.

Flow Engine Toolbar Buttons

Set Options opens the Options dialog box in which you can specify implementation options.

 Browse Reports opens the Report Browser for viewing reports.

 	Command History opens a command history utility for viewing the history of commands that have been run for the current implementation revision.

Preview Commands opens a utility to preview the commands that will be run on the current implementation revision.

Set Target opens the Stop After dialog box from which you specify a processing break point.

 	Help activates context-sensitive help. After clicking this button, select a menu item or toolbar button for which you want help.


Run Control

The Flow Engine contains run control buttons that provide convenient access to the Flow menu commands. Click once on a run control button to execute a command. The following section briefly describes each run control button and, where appropriate, provides a link to the corresponding menu command.

If you position the mouse pointer over a run control button, a short description, called a tool tip, appears next to the button.

Flow Engine Run Control Buttons

Run starts running through the implementation process steps.

Step runs the next process step in the flow, then stops.

Step Back goes back one process step in the flow.

Abort terminates the current process.


Shortcuts

The right mouse button provides quick access to frequently used commands.

Flow Engine Popup Menus

The following popup menu commands are active in the Flow Engine message log window. To access a command, press the right mouse button while positioned in the message log window and choose the command from the popup menu. There are no equivalent menu commands for these commands.

Copy

Copy selected text to the clipboard.

Find

Search for a text string.


Spartan Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online Help.


Spartan Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Spartan Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing minimum signal combining requirements. The default is Fit Device.

Note:  Although the CLB Packing Strategy option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Use Generic Clock Buffers (BUFGs) in Place of BUFGPs and BUFGSs

Select this option to replace primary and secondary clock buffers with generic clock buffers before mapping occurs. This option is useful when working with design entry tools that generate only BUFGPs or BUFGSs. By default, this option is off.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Spartan Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Spartan Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Spartan Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Spartan VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Spartan device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Spartan	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Spartan EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Spartan Configuration Options Dialog Box

Click the Configuration, Startup, Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan Configuration Tab

Configuration Rate

The Spartan devices use an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (5 Volt Spartan Parts Only)

Note:  These options are supported for the Spartan family only. They are not supported for the SpartanXL family.

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Outputs

Select one of the following output options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible outputs.

CMOS

Select CMOS to specify CMOS-compatible outputs.

Read from Design

Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

Note:  You cannot use these pins to set the configuration mode or use them as user I/Os.

TDO

The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin in Spartan devices. Select this option only if you do not connect an external pull-up resistor to this pin.

Configuration Pins (SpartanXL Only)

Note:  These options are supported for SpartanXL devices only.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

Power Down

The Power Down pin allows the FPGA to exist in a standby mode which consumes less power. The FPGA enters this standby mode when the Power Down pin is driven Low. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Power Down pin. Use this option if you will use the Power Down pin but will not tristate it.

PullUp

Select PullUp to enable an internal pull-up resistor on the Power Down pin. You must use this option if the Power Down pin is not connected in your design, or if the signal driving this pin could be in a tristate condition.

Spartan XL Only

5V Tolerant I/Os

This option allows a 3.3 V device circuitry to tolerate 5 V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3 V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption. By default, this option is on.

Note:  Enabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3 V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.

Enable Configuration Through the JTAG Port

This option allows BSCAN-based configuration after the device is successfully configured. By default, this option is on.

Enable the Status Bits to be Read Through the JTAG Port

This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful. By default, this option is off.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


Spartan Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the Spartan device can be synchronized with the signal on the DONE pin. Deselect this option to begin the sequence when the configuration memory is full. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Start-up Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Spartan Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


Spartan Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select this option to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select this option to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to activate or deactivate the readback capability of the configuration bitstream. To activate this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


Spartan Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


Spartan2 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online Help.


Spartan2 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Spartan2 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Map Options

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Spartan2 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Spartan2 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Spartan2 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan2 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Spartan2 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Spartan2 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Spartan2	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Note:  The following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Spartan2 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Spartan2 Configuration Options Dialog Box

Click the Configuration, Startup, or Readback tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan2 Configuration Tab

Configuration Rate

Spartan2 devices use an internal configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate in megahertz (MHz) for this clock. The default is 4 MHz.

Configuration Pins

Configuration Clk

This pin is used to synchronize to an internal clock provided in the FPGA device. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Configuration Clk pin.

PullUp

Select PullUp to enable a pull-up on the Configuration Clk pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the PROG pin.

PullUp

Select Pullup to enable a pull-up on the PROG pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

Active PullUp

Select Active PullUp to drive the DONE pin High with a CMOS driver.

JTAG Pins

For more information on the following pins, see the JTAG Programmer Guide.

TCK

This pin is the JTAG test clock.The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TCK pin.

PullUp

Select PullUp to enable a pull-up on the TCK pin.

PullDown

Select PullDown to enable a pull-down on the TCK pin.

TDI

This pin is the serial data input to all JTAG instructions and JTAG registers. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDI pin.

PullUp

Select PullUp to enable a pull-up on the TDI pin.

PullDown

Select PullDown to enable a pull-down on the TDI pin.

TDO

The TDO pin is the serial data output for all JTAG instruction and data registers. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

TMS

This pin is the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TMS pin.

PullUp

Select PullUp to enable a pull-up on the TMS pin.

PullDown

Select PullDown to enable a pull-down on the TMS pin.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Enable the User ID Code

Use this option to assign a code in the User Identification Register. Enter an ID code in the Code field. This code comprises eight hexadecimal digits that are placed in the User ID Register. By default, this option is off.


Spartan2 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

JTAG Clock

Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.

Output Events

There are five major output events which occur during a device startup.

•	Done (CFG_DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

•	Release Write Enable (Global Write Enable signal deasserted)

•	Release DLL (DLL allowed to synchronize)

Depending on the setting for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Spartan2 Output Events Options Matrix

	CCLK	User Clock	JTAG Clock
DONE	C1-C6	C1, U2-U6	C1, J2-J6
Enable Outputs	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Set/Reset	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Write Enable	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release DLL	C0-C6, No Wait	C0-C1, U2-U6, No Wait	C0-C1, J2-J6, No Wait
The definitions of the possible output events settings are as follows.

C0	Before the Cclk rising edge after the length count is met

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

C5	Fifth-Cclk rising edge after the length count is met

C6	Sixth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U5	Fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U6	Sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J2	Second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J3	Third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J4	Fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J5	Fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J6	Sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

Done	When the CFG_DONE signal goes High

Keep	Holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High

No Wait	Not synchronized to the startup clock; DLL synchronizes as soon as possible

Enable Internal Done Pipe

Select this option when the startup clock is running at high speeds. If you select this option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself. By default, this option is off.


Spartan2 Readback Tab

Security

Enable Readback and Reconfiguration

This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the RDATA pin. By default, this option is on.

Generate Readback Bitstream

Select this option to create a readback bitstream file. By default, this option is off.

Disable Readback

This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.

Disable Readback and Reconfiguration

This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.


Virtex Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Virtex Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Map Options

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Virtex Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Virtex Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Virtex Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Virtex VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Virtex device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Virtex	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Note:  The following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Virtex EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Virtex Configuration Options Dialog Box

Click the Configuration, Startup, or Readback tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex Configuration Tab

Configuration Rate

Virtex devices use an internal configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate in megahertz (MHz) for this clock. The default is 4 MHz.

Configuration Pins

Configuration Clk

This pin is used to synchronize to an internal clock provided in the FPGA device. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Configuration Clk pin.

PullUp

Select PullUp to enable a pull-up on the Configuration Clk pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the PROG pin.

PullUp

Select Pullup to enable a pull-up on the PROG pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

Active PullUp

Select Active PullUp to drive the DONE pin High with a CMOS driver.

JTAG Pins

For more information on the following pins, see the JTAG Programmer Guide.

TCK

This pin is the JTAG test clock.The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TCK pin.

PullUp

Select PullUp to enable a pull-up on the TCK pin.

PullDown

Select PullDown to enable a pull-down on the TCK pin.

TDI

This pin is the serial data input to all JTAG instructions and JTAG registers. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDI pin.

PullUp

Select PullUp to enable a pull-up on the TDI pin.

PullDown

Select PullDown to enable a pull-down on the TDI pin.

TDO

The TDO pin is the serial data output for all JTAG instruction and data registers. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

TMS

This pin is the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TMS pin.

PullUp

Select PullUp to enable a pull-up on the TMS pin.

PullDown

Select PullDown to enable a pull-down on the TMS pin.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Enable the User ID Code

Use this option to assign a code in the User Identification Register. Enter an ID code in the Code field. This code comprises eight hexadecimal digits that are placed in the User ID Register. By default, this option is off.


Virtex Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP_VIRTEX symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

JTAG Clock

Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.

Output Events

There are five major output events which occur during a device startup.

•	Done (CFG_DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

•	Release Write Enable (Global Write Enable signal deasserted)

•	Release DLL (DLL allowed to synchronize)

Depending on the setting for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Virtex Output Events Options Matrix

	CCLK	User Clock	JTAG Clock
DONE	C1-C6	C1, U2-U6	C1, J2-J6
Enable Outputs	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Set/Reset	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Write Enable	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release DLL	C0-C6, No Wait	C0-C1, U2-U6, No Wait	C0-C1, J2-J6, No Wait
The definitions of the possible output events settings are as follows.

C0	Before the Cclk rising edge after the length count is met

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

C5	Fifth-Cclk rising edge after the length count is met

C6	Sixth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U5	Fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U6	Sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J2	Second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J3	Third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J4	Fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J5	Fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J6	Sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

Done	When the CFG_DONE signal goes High

Keep	Holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High

No Wait	Not synchronized to the startup clock; DLL synchronizes as soon as possible

Enable Internal Done Pipe

Select this option when the startup clock is running at high speeds. If you select this option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself. By default, this option is off.


Virtex Readback Tab

Security

Enable Readback and Reconfiguration

This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the RDATA pin. By default, this option is on.

Generate Readback Bitstream

Select this option to create a readback bitstream file. By default, this option is off.

Disable Readback

This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.

Disable Readback and Reconfiguration

This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.


XC3000 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab or to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC3000 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC3000 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC3000 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC3000 Simulation Template Dialog Box
XC3000 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist. If you select EDIF as your netlist format, this option is on by default.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC3000 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC3000 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC3000	GR	always	active-Low
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC3000 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC3000 Configuration Options Dialog Box

Click the Configuration, Startup/Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 Configuration Tab

Threshold Level

Inputs

This option affects all input pins. You cannot set individual pins. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs except for the special purpose clocks, Tclkin, Bclkin, and Pwrdwn which always require CMOS input signals.

CMOS

Select CMOS to specify CMOS compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Configuration Pin Pullups

Done/Program

Select one of the following options. The default is Pullup.

Float

Select Float to disable an internal pull-up resistor on the Done/Program (D/P) pin. The D/P pin is an open-drain output that requires a pull-up resistor to indicate the end of the configuration. If this option is selected, an external pull-up resistor should be connected to the D/P pin.

Pullup

Select Pullup to enable an internal pull-up resistor on the Done/Program (D/P) pin. This resistor has a value of 2 to 8 kilohms. The D/P pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. Turn off this option only if you intend to connect an external pull-up resistor to this pin.

Crystal Oscillator

The XC3000 family of devices contains an internal high-speed inverting amplifier which you can use to implement an on-chip crystal oscillator. To use this feature, you must include either the GXTL or OSC library element in your design and connect the appropriate external R-C crystal circuit to the amplifier. See the Xilinx Libraries Guide and The Programmable Logic Data Book for more information.

Select one of the following options. The default is Disabled.

Disabled

Select Disabled to disable the crystal oscillator.

Enabled

Select Enabled to enable the crystal oscillator.

Enabled (Divide by 2)

Select Enabled (Divide by 2) to divide the crystal oscillator frequency by two to generate a symmetrical clock signal.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


XC3000 Startup/Readback Tab

Readback

Mode

After an FPGA is configured, data can be read back and compared with the original configuration data. For security reasons, it is sometimes desirable to disable or limit readback capability. The following options control readback. The default is On Command.

Never

Select Never to disable readback completely.

Once

Select Once to enable a one-time readback.

On Command

Select On Command to enable readback on command. This option generates a .ll file.

Output Events

Done

The DONE signal indicates the completion of the configuration sequence. You can program this signal to be asserted before or after I/Os go active. The default is Before I/Os Active.

Before I/Os Active

Select Before I/Os Active to release the DONE signal one Cclk period before the outputs go active.

After I/Os Active

Select After I/Os Active to release the DONE signal one Cclk period after the outputs go active.

Reset

A global reset signal is asserted while the device is configuring during the startup sequence. You can program the release of this signal to occur before or after I/Os go active. The default is After I/Os Active.

Before I/Os Active

Select Before I/Os Active to release the Internal Reset one Cclk period before the outputs go active.

After I/Os Active

Select After I/Os Active to release the Internal Reset one Cclk period after the outputs go active.


XC3000 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use this option, Design Rule Check (DRC) runs first. After DRC, this option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC4000 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC4000 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Use Generic Clock Buffers (BUFGs) in Place of BUFGPs and BUFGSs

Select this option to replace primary and secondary clock buffers with generic clock buffers before mapping occurs. This option is useful when working with design entry tools that generate only BUFGPs or BUFGSs. By default, this option is off.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC4000 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC4000 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC4000 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC4000 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC4000 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC4000	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC4000 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC4000 Configuration Options Dialog Box

Click the Configuration, Startup, Readback, Tie or Advanced tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 Configuration Tab

Configuration Rate

The XC4000 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (XC4000E and XC4000EX Only)

Note:  These options are supported for the XC4000E and XC4000EX subfamilies only.

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Outputs

Select one of the following output options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible outputs.

CMOS

Select CMOS to specify CMOS-compatible outputs.

Read from Design

Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

TDO

The TDO pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

XC4000XLA and XC4000XV Only

5V Tolerant I/Os

This option allows a 3.3 V device circuitry to tolerate 5 V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3 V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption. By default, this option is on.

Note:  Enabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3 V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.

Enable EXPRESS Mode

This option enables express mode configuration. In this mode, configuration data is presented to the device in parallel format, and each new byte is clocked into the target device with every rising edge of the CCLK. This mode is eight times as fast as other configuration modes because data is processed at the rate of one byte per CCLK rather than one bit per CCLK. By default, this option is off.

Enable Configuration Through the JTAG Port

This option allows BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring XLA devices by toggling the TCK/TMS/TDI/TDO lines. By default, this option is on.

Enable the Status Bits to be Read Through the JTAG Port

This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful. By default, this option is off.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


XC4000 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. CCLK is the default.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the XC4000 can be synchronized with the signal on the DONE pin. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. Deselect this option to begin the sequence when the configuration memory is full. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Startup Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

XC4000 Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


XC4000 Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select this option to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select this option to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to activate or deactivate the readback capability of the configuration bitstream. To activate this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


XC4000 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC4000 Advanced Tab

XC4000EX/XL Only

Configuration Address Lines

Use this option to set the number of address lines that will be used by the FPGA during device configuration. Address lines are used to address data from a parallel PROM or flash memory device. Select either 18 or 22. If you choose 22, four extra device pins are activated as configuration address lines. The default is 18.

This option only applies to master parallel mode configuration. You must set this option in addition to setting the mode pins. Refer to The Programmable Logic Data Book for more information on address lines and master parallel mode configuration.


XC5200 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC5200 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC5200 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC5200 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC5200 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC5200 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC5200 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC5200	GR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC5200 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC5200 Configuration Options Dialog Box

Click the Configuration, Startup, Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 Configuration Tab

Configuration Rate

The XC5200 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 0.75 MHz (nominal).

Medium

Select Medium to set the configuration clock rate to 6 MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 12 MHz (nominal).

Threshold Level

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Configuration Pins

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. This resistor has a value of 2 to 8 kohm. Select this option only if you do not connect an external pull-up resistor to this pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the PROG pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the PROG pin.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Oscillator Clock

This option determines whether the XC5200 oscillator will be driven by the internal clock or by a user clock. The default is CCLK.

CCLK

Select CCLK to drive the oscillator clock with the internal 16 MHz clock.

User Clock

Select User Clock to drive the oscillator with a user clock. If you specify User Clock, the clock must be connected to the OSC.CK pin of the device's OSC component.


XC5200 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the XC5200 can be synchronized with the signal on the DONE pin. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. Deselect this option to begin the startup sequence begins as soon as the configuration memory is full. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Startup Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

XC5200 Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


XC5200 Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select User Clock to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to enable or disable the readback capability of the configuration bitstream. To enable this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


XC5200 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC9500 Implementation Options Dialog Box

Click the Translate, Basic, Advanced, Timing Reports, or Programming tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Fit, and Bitstream steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options which are optimized for speed, or click Help to obtain online help.

Note:  In addition to the Balanced optimization default options, there are two preset implementation option templates: Speed Optimization and Area optimization. The defaults described in the online Help only apply to the Balanced optimization options.


XC9500 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the design is read incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC9500 Basic Tab

Use Global Clock(s)

Select this option to convert the p-term clock to a global clock. The global clock may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Output Enable(s)

Select this option to convert the p-term output enable to global output enable. Global output enable may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Set/Reset

Select this option to convert the p-term set/reset to global set/reset. Global set/reset may allow you to meet your timing constraints more easily. By default, this option is on.

Use Timing Constraints

Select this option to indicate that you want the software to use your timing constraints to perform timing-driven optimization in the fitting of your design. For this option to be useful, you must have previously created a timing constraints file or you must have included timing constraints in your design. By default, this option is on.

Use Design Location Constraints

Select this option to indicate that you want to use pinout and macrocell location information in the design file or constraint file. Deselect this option to allow the fitter to place pins and logic anywhere or as specified in the guide file. By default, this option is on.

Create Programmable Ground Pins on Unused I/O

Select this option to indicate that you want all unused I/O pads to be configured as ground pins. This can reduce ground bounce. By default, this option is off.

Macrocell Power Setting

Use this option to control device power consumption. Select Std (standard), Low, or Timing Driven to set the default power mode for the macrocells used to implement the design. The default is Std.

Note:  Any explicit power control statements in the design or constraints file have precedence over the Default Power Setting.

Std

Select Std to set the power mode for the macrocells to higher speed and higher power.

Low

Select Low to reduce power consumption and reduce speed.

Timing Driven

Select Timing Driven to set the power consumption based on your timing constraints.

Output Slew Rate

Use this option to modify the output slew rate. Limiting the slew rate reduces output switching surges in the device. You can control the transition time of device output pins by setting the slew rate to Fast, Slow, or Timing Driven. The default is Fast.

Note:  Any explicit slew rate control statements in the design or constraints file have precedence over the Output Slew Rate. This setting has no effect on third-party tools that create explicit slew rate statements.

Fast

Select Fast to use more current and enable faster logic responses.

Slow

Select Slow to use less current and avoid ground bounce.

Timing Driven

Select Timing Driven to control the transition time based on your timing constraints.


XC9500 Advanced Tab

Use Timing Optimization

Select this option to perform timing optimization. Timing optimization shortens the critical paths and allocates the fastest resources for a design, assuming that all paths are equally critical. In some cases, timing optimization trades density for speed. By default, this option is on.

Use Multi-Level Logic Optimization

This option simplifies the total number of logic expressions in a design, and then collapses the logic in order to meet user objectives such as density, speed and timing constraints. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of p-terms.

Multi-level Logic Optimization optimizes combinatorial logic from your design. Combinatorial logic includes the following types of logic.

•	Register-to-register logic

•	Pad-to-register logic

•	Register-to-pad logic

•	Pad-to-pad logic

Multi-level Logic Optimization operates on combinatorial logic according to the following rules.

•	If timing constraints are set, the program optimizes for speed to meet timing constraints.

•	If timing constraints are not set, the program optimizes either for speed or density, depending on the user setting for the Use Timing Optimization option.

•	If Use Timing Optimization is turned on, the combinatorial logic will be mapped for speed.

•	If Use Timing Optimization is turned off, the combinatorial logic will be mapped for density. The goal of optimization will then be to reduce the total number of p-terms.

•	Logic marked with the attribute MINIMIZE=OFF will not be extracted or optimized.

By default, this option is on.

Enable D <--> T Type Transform Optimization

Select this option to allow the software to convert D-type flip-flops to T-type flip-flops. This option allows the software to choose the implementation that requires the smaller amount of logic resources. By default, this option is on.

Collapsing Pterm Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of product terms in the resulting logic function does not exceed the p-term limit. If the path delay of a logic function is not acceptable, increase the p-term limit to allow the larger functions to be further flattened. Choose a number from 2 to 90. The default p-term limit for the XC9500 family is 25 p-terms.

XC9500 Only — Use Advanced Fitting

Select this option to enable an advanced fitting strategy that favors placing signals with common inputs in the same function block. This usually allows you to pack more logic into the same device. Disable this option if the software has trouble fitting a design that used to fit with an older version of software. By default, this option is on.

XC9500 Only — Use Local Macrocell Feedback

Select this option to enable the software to use local macrocell feedback whenever possible. The local feedback path (from a macrocell-output to an input of the same function block) takes less time than the global feedback path. Using local feedback can speed up your design but can also make it difficult to keep the same timing after a design change.

To take maximum advantage of local feedback, control the placement to group appropriate signals into the same function block. In order to fit a design, the software may require wire-ANDing in the interconnect which can prevent local feedback use. However, you can force a local feedback by applying a timespec and assigning the signals to the same function block. This method prevents wire-ANDing of local feedback signal and works even if you disable the Use Local Macrocell Feedback option. By default, this option is on.

Note:  The XC9536 device does not have local feedback.

XC9500 Only — Use Local Pin Feedback

Select this option to enable the software to use local I/O pin feedback whenever possible. The pin feedback path takes less time than the FastCONNECT path. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have 3-state control or Slow slew rate. By default, this option is on.

XC9500 Only and XC9500XL/XV Only — Collapsing Input Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of inputs in the resulting logic function does not exceed the input limit. If the path delay of a logic function is not acceptable, increase the input limit to allow the larger functions to be further flattened. For XC9500 devices, choose a number from 2 to 36. The default is 36. For XC9500XL and XC9500XV devices, choose a number from 2 to 54. The default is 54.


XC9500 Timing Reports Tab

Produce Post Fitting Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is fitted. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Note:  If you select this option, the report is automatically generated during the Fit step.

Timing Report Format

This option allows you to choose the level of detail given in your timing report. The default is Summary.

Summary

Select Summary to generate a report that contains summary information and design statistics.

Detailed

Select Detailed to generate a report that lists delay information for all nets and paths.


XC9500 Programming Tab

Signature/User Code

Select Use <design name> or enter a unique text string in the Specify As field to identify the configuration data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the JTAG Programmer to identify the configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is Use <design_name>.

Jedec Test Vector File

Use this option to include a TMV file in your JEDEC file. The TMV file is a test vector file generated when ABEL compiles a design containing user test vectors. Click Browse to look for a TMV file.


XC9500 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC9500 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC9500 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC9500 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC9500	PRLD	when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC9500 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Trademarks

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The shadow X shown above is a trademark of Xilinx, Inc.

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Technical Support

You can contact Xilinx for additional information and assistance in a variety of ways. Start by getting answers on the Web at support.xilinx.com.

Xilinx Services and Support on the Web

http://support.xilinx.com

The support.xilinx.com page contains thousands of online technical solutions and product information for Xilinx software and devices. The Xilinx Answers Database is updated daily with the latest patches, problem resolutions, application notes, and data sheets. Receive immediate answers 24 hours a day!

Technical and Applications Support Hotlines

If you cannot find your answers at support.xilinx.com, telephone hotlines give you direct access to Xilinx Application Engineers worldwide. You can also e-mail or fax your technical questions to the same locations.

Location	Telephone	Electronic Mail	Facsimile (Fax)
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 Note:  When e-mailing or faxing inquiries, please provide your complete name, company name, and phone number. Also, please provide a complete problem description including your design entry software and design stage. In North America, call 1-800-255-7778 if you cannot find your answer at support.xilinx.com.

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Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this page. You can also directly access some of these resources using the provided URLs.

Resource	Description/URL
Tutorial	Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm


Glossary

asynchronous debugging

BIT file

bitstream (BIT file)

block

bottom-up design

BUFT

byte-wide PROM

CCLK pin

CLKI pin

CLKO pin

clock input path

clock skew

critical path

daisy chain

debugging

DIN pin

DONE pin

downloading

D/P pin

EDIF

EXORmacs (Motorola)

external clock

fitting

GND pin

group

guide file

HDL

HEX

hold time

INIT pin

instance

internal XChecker clock

IOB (input/output block)

.ll file

loading direction

logic icon

logic synthesis

mapping

MCS-86 (Intel)

net

number of clock cycles

one-to-one logic

optimization

pad

pin

place effort

placer

placing

primitive

probing

PROG pin

programming

PROM

PROM file

RBT file

RD pin

readback

route effort

router

routing

RPM

RST pin

RT pin

schematic

script

SDF

serial PROM

setup time

snapshot

states

static timing analysis

status bar

synchronous debugging

synthesis

TCK pin

TDI pin

TEKHEX (Tektronix)

timing

timing constraints

TMS pin

toolbar

toolbox

top-down design

TRIG pin

trigger

TTY

Universal Interconnect Matrix (UIM)

VCC pin

verification

Verilog

VHDL

waveform

WIR file

workspace


asynchronous debugging (definition)
asynchronous debugging

An FPGA debugging mode in which you capture data without controlling your system clock.


BIT file (definition)
BIT file

Synonym for a bitstream file.


bitstream (definition)
bitstream (BIT file)

A stream of data that contains location information for logic on a device, that is, the placement of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back.

A bitstream file has a .bit extension.


block (definition)
block

A group of one or more logic functions.


bottom-up design (definition)
bottom-up design

Design methodology where already defined HDL blocks are merged into one overall desired design behavior. The lowest level portion of your design is completed first. Only after the low-level building blocks are complete do you finish higher-level hierarchical blocks in your design. This methodology is typically used with schematic capture programs.


BUFT (definition)
BUFT

Tristate buffer.


byte-wide PROM (definition)
byte-wide PROM

A PROM that supplies data one byte at a time. It is used for master parallel mode configuration of FPGAs.


CCLK pin (definition)
CCLK pin

The XChecker pin that provides the configuration clock for the device or daisy chain of devices during a download. This is also the pin on an FPGA that receives the configuration clock.


CLKI pin (definition)
CLKI pin

XChecker clock input pin. CLKI provides an external clock to the Hardware Debugger so that in conjunction with the CLKO pin, the Debugger can control the application of the external clock to the device being debugged.


CLKO pin (definition)
CLKO pin

XChecker clock output pin. CLKO supplies the Hardware-Debugger-controlled clock to the device being debugged. The source of CLKO is one of the following: CLKI, logic 1, logic 0, or the internal XChecker clock.


clock input path (definition)
clock input path

A path starting at either an input of the chip or at the output of a flip-flop, latch, or RAM, and ending at any clock pin on a flip-flip or latch enable. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.


clock skew (definition)
clock skew

The maximum difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop. It is also referred to as clock delay.


critical path (definition)
critical path

A signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which may include I/O pads.


daisy chain (definition)
daisy chain

A series of bitstream files concatenated in one file. It can be used to program several FPGAs connected in a daisy chain board configuration.


debugging (definition)
debugging

The process of reading back or probing the states of a configured device to ensure that the device is behaving as expected while in circuit.


DIN pin (definition)
DIN pin

On an FPGA, the data pin that accepts a serial version of a bitstream. On the XChecker cable, it provides the bitstream data and connects to the DIN pin of the target FPGA.


DONE pin (definition)
DONE pin

Dual-function pin. As an input, it can be configured to delay the global logic initialization or the enabling of outputs. As an output, it indicates the completion of the configuration process.


downloading (definition)
downloading

Configuring or programming a device by sending bitstream data to the device.


D/P pin (definition)
D/P pin

Dual-function pin. As an input (PROGRAM), it initiates a reconfiguration of a configured device. As an output (DONE), signals the end of configuration.


EDIF (definition)
EDIF

Electronic Data Interchange Format, an industry standard file format for specifying a design netlist. It is generated by a third-party design-entry tool.


EXORmacs (definition)
EXORmacs (Motorola)

A PROM format supported by the Xilinx tools. Its maximum address is 16 777 216. This format supports PROM files of up to (8 x 16 777 216) = 134 217 728 bits.


external clock (definition)
external clock

The system clock that XChecker uses from the target board during synchronous mode debugging. To use an external clock, connect the system clock to the XChecker cable using the CLKI pin and the XChecker clock to the FPGA device using the CLKO pin.


fitting (definition)
fitting

The process of putting logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically, and because of the UIM architecture, all designs are routable.


GND pin (definition)
GND pin

Ground (0 volts).


group (definition)
group

A collection of common signals to form a bus. In the case of a counter, for example, the different signals that produce the actual counter values can be combined to form an alias, or group.


guide file (definition)
guide file

A previously placed and routed FPGA or fitted CPLD design file that can be used in a subsequent place and route or fitting operation.


HDL (definition)
HDL

Hardware Description Language. The most common HDLs in use today are Verilog and VHDL. They describe designs in a technology-independent manner using a high level of abstraction.


HEX (definition)
HEX

A simple text dump of the PROM data in HEX format. It has unlimited data capacity.


hold time (definition)
hold time

The time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


INIT pin (definition)
INIT pin

Device pin indicating when a device is ready to receive configuration data after power-up.


instance (definition)
instance

One specific gate or hierarchical element in a design or netlist. The term "symbol" often describes instances in a schematic drawing. Instances are interconnected by pins and nets. Pins are ports through which connections are made from an instance to a net. A design that is flattened to the lowest level constituents is described using primitive instances.


internal XChecker clock (definition)
internal XChecker clock

The clock internal to XChecker cable that can be applied by the XChecker CLKO pin to a device being debugged.


IOB (definition)
IOB (input/output block)

A collection or grouping of basic elements that implement the input and output functions of an FPGA device.


.ll file (definition)
.ll file

The logic allocation file, which indicates the bitstream position of storage elements such as latches, flip-flops, and IOB inputs and outputs. The Hardware Debugger uses this file to locate signal values inside a readback bitstream.


loading direction (definition)
loading direction

The direction of the addresses in which data is stored on your PROM. In the Up direction, the data is stored in ascending address order. In the Down direction, the data is stored in descending address order.


logic icon (definition)
logic icon

Graphical representation of a logic resource, such as a flip-flop, buffer, or register.


logic synthesis (definition)
logic synthesis

A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a netlist using a library containing primitives.


mapping (definition)
mapping

The process of assigning a design's logic elements to the specific physical elements, such as CLBs and IOBs, that actually implement logic functions in a device.


MCS-86 (definition)
MCS-86 (Intel)

A PROM format supported by the Xilinx tools. Its maximum address is 1 048 576. This format supports PROM files of up to (8 x 1 048 576) = 8 388 608 bits.


net (definition)
net

A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.


number of clock cycles (definition)
number of clock cycles

Number of clocks that occur between snapshots during synchronous mode debugging. When capturing multiple snapshots, the number of snapshots is used as a trigger for capturing each snapshot.


one-to-one logic (definition)
one-to-one logic

In the context of Xilinx FPGA devices, the exact correspondence between the logic specified in the design entry phase and the logic implemented in the device. For example, if you draw three inverters in your design, there are three corresponding inverters in the programmed device. This correspondence makes back-annotation of timing delays very straightforward and ensures that there are no differences between your original design and the finished device.


optimization (definition)
optimization

The process that decreases the area or increases the speed of a design.


pad (definition)
pad

The physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.


pin (definition)
pin

A symbol pin or package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.


place effort (definition)
place effort

User-controlled parameter that balances run-time with placement efficiency for the Flow Engine.


placer (definition)
placer

The utility that maps logic from your design into specific locations in the target FPGA chip.


placing (definition)
placing

The process of assigning physical device cell locations to the logic in a design.


primitive (definition)
primitive

A logic element that directly corresponds, or maps, to a basic silicon element.


probing (definition)
probing

The process of examining the states of an FPGA device.


PROG pin (definition)
PROG pin

An XChecker pin that provides a reprogram pulse to XC4000, XC5200, Spartan2, and Virtex devices when connected to the PROG pin of the device.


programming (definition)
programming

The process of configuring the programmable interconnect in the FPGA.


PROM (definition)
PROM

A programmable read-only memory.


PROM file (definition)
PROM file

A file consisting of one or more BIT files (bitstreams) formed into one or more datastreams. The file is formatted in one of four industry-standard formats: Intel MCS-86, Tektronics TEKHEX, Motorola EXORmacs or HEX. The PROM file includes headers that specify the length of the bitstreams, as well as all the framing and control information necessary to configure the FPGAs. It can be used to program one or more devices.


RBT file (definition)
RBT file

A raw BIT format file; the ASCII version of the BIT file.


RD pin (definition)
RD pin

XChecker readback data pin.


readback (definition)
readback

The process of reading the logic downloaded to an FPGA device. There are two types of readback.

•	A readback with a filter that extracts the configuration bits to verify that a design was downloaded in its entirety.

•	A readback with a filter that extracts the states of design storage elements, CLB outputs, and IOB outputs to ensure that the device is behaving as expected.


route effort (definition)
route effort

User-controlled parameter that balances run-time with routing efficiency for the Flow Engine.


router (definition)
router

The utility that determines which wires to use to connect logic.


routing (definition)
routing

The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.


RPM (definition)
RPM

Relationally placed macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.


RST pin (definition)
RST pin

An XChecker pin that can be driven Low after configuration to reset the target FPGA internal latches and flip-flops.


RT pin (definition)
RT pin

The XChecker readback trigger pin.


schematic (definition)
schematic

A hierarchical drawing representing a design in terms of user and library components.


script (definition)
script

A series of commands that automatically execute a complex operation such as the steps in a design flow.


SDF (definition)
SDF

Standard Delay Format, which is an industry-standard file format for specifying timing information. It is usually used for simulation.


serial PROM (definition)
serial PROM

A PROM that is read one bit at a time.


setup time (definition)
setup time

The time prior to a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


snapshot (definition)
snapshot

Readback data that contains the values of all storage elements, CLB outputs, and IOB inputs and outputs of a design at a point in time.


states (definition)
states

A set of values stored in the memory elements of a device (flip-flops, latches, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback. To each state there corresponds a specific set of logical values.


static timing analysis (definition)
static timing analysis

A point-to-point delay analysis of a design network.


status bar (definition)
status bar

An area located at the bottom of a window that provides information about the commands that you are about to select or that are being processed.


synchronous debugging (definition)
synchronous debugging

A debug mode in which you use the XChecker cable to have full control of the clock.


synthesis (definition)
synthesis

A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a netlist using a library containing primitives.


TCK pin (definition)
TCK pin

A pin on the XChecker cable. This output supplies clocks for a boundary scan port on an XC9500 device. The JTAG software must be used to drive the boundary scan port on the Xchecker cable.


TDI pin (definition)
TDI pin

A pin on the XChecker cable. This input receives data from the boundary scan chain. The JTAG software must be used to drive the boundary scan port on the XChecker cable.


TEKHEX (definition)
TEKHEX (Tektronix)

A PROM format supported by Xilinx. Its maximum address is 65 536. This format supports PROM files of up to (8 x 65 536) = 524 288 bits.


timing (definition)
timing

A process that calculates the delays associated with each of the routed nets in a design.


timing constraints (definition)
timing constraints

A user specification of the maximum allowable delay on any given set of paths in a design. Timing constraints can be entered on a schematic or in a user constraints (UCF) file.


TMS pin (definition)
TMS pin

A pin on the XChecker cable. This output drives the mode of the boundary scan state machine. The JTAG software must be used to drive the boundary scan port on the XChecker cable.


toolbar (definition)
toolbar

A field located under the menu bar at the top of a window. It contains a series of buttons that you click on to execute some of the most commonly used commands. These buttons are an alternative to the menu commands.


toolbox (definition)
toolbox

The toolbox is a field located in the Design Manager main window. It contains a series of buttons that you click on to invoke tools such as the Flow Engine, Timing Analyzer, Floorplanner, PROM File Formatter, Hardware Debugger, FPGA Editor, Chip Viewer, and JTAG Programmer.


top-down design (definition)
top-down design

A process that starts a design with the highest level of abstraction and gradually designs underlying blocks until the complete design is implemented in the target technology. Top-down design is often technology-independent at the highest levels of design abstraction.


TRIG pin (definition)
TRIG pin

An XChecker external trigger pin that causes the Hardware Debugger to initiate a readback of the device being debugged.


trigger (definition)
trigger

An external signal that tells the Hardware Debugger to read a snapshot.


TTY (definition)
TTY

Textual command line interface.


Universal Interconnect Matrix (definition)
Universal Interconnect Matrix (UIM)

The routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing 100% routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.


VCC pin (definition)
VCC pin

Power (5 volts).


verification (definition)
verification

The process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.


Verilog (definition)
Verilog

Commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1364-1995. Verilog was originally developed by Cadence Design Systems and is now maintained by OVI.

A Verilog file has a .v extension.


VHDL (definition)
VHDL

An acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High-Speed Integrated Circuits). It can be used to describe the concurrent and sequential behavior of a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. VHDL is IEEE standard 1076-1993.

A VHDL file has a .vhd or .vhdl extension.


waveform (definition)
waveform

A graphical representation of a set of simulation transitions that depicts the digital or electrical values of a node on the schematic.


WIR file (definition)
WIR file

Viewlogic netlist files built by ViewDraw, PROcapture, or ViewSynthesis. A WIR file is an intermediate design file generated by the Viewlogic design tools.


workspace (definition)
workspace

In the PROM File Formatter, workspace is a frame and an empty data stream. When you add files into the data stream, the horizontal arrows indicate the concatenation of files.