Copyright: HH Bridge(c) Bristol Technology Inc. 1993


Overview

The Design Manager is the top-level software module in the Xilinx Development System. Use the Xilinx Development System tool suite for implementing a design into a Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). The Design Manager provides access to all the tools you need to read a design file from a design entry tool and implement it in a Xilinx device.

Design Manager Capabilities

The Design Manager performs the following functions.

•	Organizes and manages your design implementation data

•	Creates multiple design versions for management of design changes

•	Creates multiple implementation revisions for management of implementation strategies

•	Provides access to reports

•	Manages data for and access to the following tools in the Xilinx Design Manager system. The tools differ for FPGA and CPLD families.

•	Flow Engine (FPGA and CPLD)

•	Timing Analyzer (FPGA and CPLD)

•	Floorplanner (All XC4000 families, Virtex, Spartan/XL, and Spartan2 FPGA families only)

•	PROM File Formatter (FPGA)

•	Hardware Debugger (FPGA)

•	FPGA Editor (FPGA)

•	Chip Viewer (CPLD)

•	JTAG Programmer (All XC4000 families, XC5200, Virtex, Spartan/XL, and Spartan2 FPGA families and CPLD families)

Use the Design Manager with the Flow Engine to perform the following functions.

•	Target different devices

•	Generate and export timing simulation data for external simulation tools

•	Generate and export configuration data


Design Management Fundamentals

You can perform multiple functions from within the Design Manager, such as launching Xilinx tools and managing your projects, design versions, and implementation revisions.

Projects

The Design Manager window displays all Xilinx data related to a single project. When you create a project, a design version and implementation revision are automatically created so that you always have a revision on which to run the software tools. A project includes all design versions and implementation revisions that are created as you implement your design. You can work with multiple projects, but only one is active at a time. The hierarchical structure in the Design Manager project view shows the relationships of the project elements.

Design Versions

You create your design using third party front-end tools that support schematic and Hardware Description Language (HDL) entry. The Design Manager reads in the design netlist and creates a design version in the Design Manager project view. If the design netlist changes, the Design Manager reads in the modified design and creates a new design version.

You can try modified versions of your design and easily keep track of them. Each new set of changes becomes a new design version and is assigned a design version name by the Design Manager. You can choose any one of the available design versions for processing.

When you create a new design version, a new implementation revision is automatically created. Each design version can contain multiple implementation revisions.

Note:  The Design Manager saves design versions in the Xilinx database format, not in the format of the front-end editor.

Implementation Revisions

After you create a design version, you can try different implementation strategies on your design. The data associated with each of these implementation strategies is called an implementation revision. Each implementation revision contains the data files and reports that are created based on a specific set of implementation strategies.

This method allows you to vary how your design is implemented in order to achieve your design objectives. For example, you can maximize speed and density in your design by controlling the implementation settings or by targeting a different device family better suited for your design.

Note:  If you are using an HDL flow, it is strongly recommended that you create a new synthesis netlist when you change FPGA or CPLD families. This ensures that the tools make the best use of the target device.

When you create a new revision either manually or automatically, the data from the "last" revision is copied to the new revision by default. The "last" revision is bottommost in the Design Manager project view. You can copy data from other revisions by setting options in the Copy Persistent Data field of the New Version or New Revision dialog box. You can also copy data from other revisions by using the Set Constraint File, Set Guide File(s), and Set Floorplan File(s) menu commands after the revision is created. If you want to change any of the implementation options, use the Options command.

Note:  Because you must always have an implementation revision on which to run the tools, at least one revision must always exist for each version in the Design Manager. If only one revision exists inside a version, you can only delete the revision by deleting the version.


Design Management Procedure

The typical procedure for managing a design is as follows.

1.	In your design entry tool, create a design.

2.	Output your design as an EDF, EDIF, EDN, SEDIF, PLD, SXNF, XNF, or XTF file. The PLD format is supported for CPLDs only.

3.	In the Design Manager, open an existing project file or create a new project file in which to implement your logic design.

4.	Implement your design.

•	If necessary, choose a different target device in which to implement your design. The initial target device is specified in the input design or when you create a new implementation revision.

•	Select implementation, simulation, and configuration options. You can use the default settings, an existing set of options, or set new options.

•	Run your design implementation and create timing simulation files and a device programming file.

5.	Review your design reports to verify that your design fits within the target device and that your timing requirements are met.

6.	If your design requirements are not met, you can do any of the following and process your design again.

•	Change your logic design.

•	Choose a different target device, package, or speed grade.

•	Define a different set of implementation, simulation, or configuration options.


Design Manager Window

The main window is the background against which all other windows are displayed. This window consists of the following parts.

Note:  Menus, dialog boxes, and parts of the application window are documented as they appear on a UNIX workstation. Differences between the PC and the workstation applications are documented if there is a difference in operation between the two platforms.

Title Bar

The title bar displays the program name and the name of the currently loaded design.

Menu Bar

This area contains the menus that control the operation of the Design Manager.

Toolbar

This area contains toolbar buttons that provide access to frequently used commands.

Project View

This area displays a graphical hierarchical view of the project, design versions, and implementation revisions.

Toolbox

The toolbox provides access to the tools in the Design Manager. The toolbox always contains the Flow Engine and Timing Analyzer, but the other tools available in this box depend on whether your target device family is an FPGA or CPLD device.

Status Bar

The status bar shows the project name, the part name if an implementation revision is selected, and the name of the selected item.


Using Dialog Boxes

Many menu commands display dialog boxes in which you can enter information and set options.

Common Fields

The fields shown in the following table are common to most dialog boxes.

Dialog Box Field	Function
OK	Closes the dialog box and implements the intended action according to the settings in the dialog box
Cancel	Closes the dialog box without effecting any action
Help	Displays information on that particular dialog box


How to Use Help

This page is a quick reference guide to the Design Manager Help. The other tools that you can access from the Design Manager have their own online Help.

Help Topics Organization

Getting Started	An overview of the Design Manager and instructions for using the interface
Procedures	Step-by-step instructions for performing tasks.
Commands	Descriptions of commands available from menus, buttons, and keyboard
Help on Help	Instructions for using Help and how to access it
Reference	Glossary, trademark, technical support, and additional resource information
Summary of Help Operations

To	Do this
Go to related topics	Click underlined words
Go to the Help Topics	Click Help Topics
Search in the Help	Click Index or Find, select a topic
Scroll in the Help window	Move the scroll bars with the mouse
Return to the previous topic	Click Back
Return to any previous topic	From the Options menu, select Display History Window and select a topic
Browse forward	Click Browse>>
Browse backward	Click <<Browse
Get detailed help on Help	On the workstation, select How to Use Help from the Help menu
Close the Help window	Select Exit from the Help File menu
Printing Help Topics	On the workstation, select How to Use Help from the Help menu, and select Configure a Printer from the How To list


Obtaining Help

You can obtain help on commands and procedures by clicking the Help button in the toolbar, clicking the Help button in dialog boxes, or pressing the F1 key. The Help button in the toolbar and in some menu command dialog boxes provides context-sensitive help.

Help Menu

The Help menu displays the following commands.

•	Help Topics lists the online help topics available. From the opening screen, you can jump to command information or step-by-step instructions. After you open help, you can click the Help Topics button (first button on the left) in the Help window whenever you want to return to the help topics list.

•	Online Documentation provides access to the Xilinx Software Manuals Online.

•	Xilinx on the Web Support and Services provides access to the support.xilinx.com page on the Web.

•	Xilinx on the Web Xilinx Home Page command provides access to the Xilinx home page on the Web.

•	About Design Manager displays a popup window that shows the version number of the software.

Toolbar

You can obtain context-sensitive help from the toolbar.

1.	Click the Help button.

The cursor changes to a question mark.

2.	Click once with the left mouse button on the menu item or toolbar button for which you want information.

Online help information about the selected command appears in a popup window.

Help Button in Dialog Boxes

Many of the dialog boxes have a Help button that you can click to obtain help on that dialog box. A window opens that displays information.

F1 Key

Pressing the F1 key when the cursor is placed on a dialog box displays help on that dialog box. The F1 key functions the same as selecting Help Topics from the Help menu, if no dialog boxes are displayed.


Creating a New Project

When you open the Design Manager for the first time you must create a new project for your design before you can use the Design Manager. A project includes all design versions, implementation revisions, reports, and any other Xilinx data created as you work with a design.

The Design Manager graphically displays information about these items in the project view. When you create a new project, you specify a design to open and a directory for the project. You can create as many projects as you want, but you can only work with one at a time.

To create a new project

1.	Select New Project from the File menu or click the New Project toolbar button.

2.	In the New Project dialog box, specify a design file to open in the Input Design field, or click Browse to select a file from the Open dialog box. Use only the following file formats.

	.edf, .edn, .edif, .sedif	EDIF netlist file
	.pld	PLUSASM file (CPLD only)
	.xnf, .xtf, .sxnf	Xilinx hierarchical netlist file
3.	To change this default work directory, type a path in the Work Directory field or use Browse to select a directory.

Note:  The Design Manager automatically creates a subdirectory named xproj under the input design directory and uses it as the work directory. The Design Manager uses the xproj subdirectory to store all the data files for the project.

4.	Enter any comments in the Comment field. Use this field to note options and strategies.

5.	In the New Project dialog box, click OK.

After your design is loaded, the Design Manager window appears, configured for the loaded design.


Creating a New Design Version

While working on a project, you may need to modify the initial input design and bring these changes into an existing project in the Design Manager. You can do this with the New Version command. The Design Manager automatically assigns a name for the design version, but you can enter a different name in the New Version dialog box. A new implementation revision is automatically created when you create a new version.

Note:  When implementing your design, the New Version dialog box appears automatically if you made changes to your design netlist.

To create a new design version

1.	Select New Version from the Design menu.

2.	In the New Version dialog box, enter a name in the Version Name field if you do not want to use the default name. Use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only. The name should be unique within the project.

3.	Enter any comments in the Version Comment field. Use this field to note options and strategies.

4.	To choose a device from the Part Selector, click Select.

5.	In the Part Selector dialog box, specify the desired settings in the Family, Device, Package, and Speed Grade pulldown menus.

6.	Click OK.

7.	Enter the name for the new implementation revision in the Revision Name field. Use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only. The name should be unique within the design version.

8.	Enter any comments in the Revision Comment field. Use this field to note options and strategies.

9.	To copy data to your new revision from another revision or from a custom file, use the settings in the Copy Persistent Data field. Select None if you do not want to copy data.

Note:  By default, the Design Manager copies floorplan and constraints file data from the "last" revision. The "last" revision is the bottommost revision in the Design Manager project view. When initially creating a project, the Design Manager copies constraints file data from the project directory to the revision directory.

10.	Click the OK button in the New Version dialog box.

The Design Manager displays a new design version and implementation revision icon in the project view.


Creating a New Implementation Revision

After you create a design version, you can try different implementation strategies on that design. For instance, you can reduce area, increase speed, and vary placement effort. Each set of implementation strategies makes up a new implementation revision. Generating new implementation revisions allows you to vary how your design is implemented in order to achieve your design objectives.

You can select new options or target a new device to change the way your design is implemented. Targeting a new device allows you to try your design in various devices to determine the most suitable fit. For example, if a particular device proves to be too large or too slow for your needs, you can select a smaller or faster target device from a different family.

Note:  If you are using an HDL flow, it is strongly recommended that you create a new synthesis netlist when you change FPGA or CPLD families. This ensures that the tools make the best use of the target device.

When you create an implementation revision, an implementation revision icon is placed in the Design Manager project view. Each time you create a new implementation revision, a default revision name and the part used in the "last" revision are automatically selected. If you want to change these default values, you can enter your own revision name and change the target part. The implementation revision name, implementation state, implementation status, and any user comments for the implementation revision are indicated next to its icon in the project view when you process the implementation. Replace or delete implementation revisions that are no longer useful.

To create a new implementation revision

1.	In the Design Manager project view, select a design version icon.

2.	Choose New Revision from the Design menu or click the New Revision toolbar button.

3.	In the New Revision dialog box, click the Select button to choose a device from the Part Selector.

4.	In the Part Selector dialog box, select the desired settings for the Family, Device, Package, and Speed Grade pull-down menus.

5.	Click OK.

6.	In the New Revision dialog box, enter the name for the new implementation revision in the Revision Name field. Use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only. The name should be unique within the design version.

7.	Enter any comments in the Revision Comment field. Use this field to note options and strategies.

8.	To copy data to your new revision from another revision or from a custom file, use the settings in the Copy Persistent Data field. Select None if you do not want to copy data.

Note:  By default, the Design Manager copies floorplan and constraints file data from the "last" revision. The "last" revision is the bottommost revision in the Design Manager project view. When initially creating a project, the Design Manager copies constraints file data from the project directory to the revision directory.

9.	In the New Revision dialog box, click OK.

The Design Manager creates a new implementation revision and displays its icon in the project view.


Setting a Part

Use the Set Part command to set the part number for a new implementation revision. Changing the part number allows you to select the device best suited for your design.

Note:  You cannot change the part number of an existing implementation revision.

To set a part

1.	Choose Set Part from the Design menu or click the Set Part toolbar button.

2.	In the Set Part dialog box, click Select to choose a device from the Part Selector.

3.	In the Part Selector dialog box, specify the desired settings in the Family, Device, Package, and Speed Grade pulldown menus.

4.	Click OK.

5.	In the Set Part dialog box, click OK.

The Design Manager displays the new implementation revision in the project view and the part number in the status bar.


Deleting Items from the Project View

Warning:  When deleting an item from the project view, the Design Manager immediately deletes the item and all accompanying data. Deleted data cannot be recovered.

Use the Delete command to delete a project, design version, or implementation revision from the project view.

To delete an item from the project view

1.	In the Design Manager project view, select the icon of the project, design version, or implementation revision that you want to delete.

2.	Select Delete from the Design menu.

3.	A confirmation box appears asking if you want to delete the selected item. Click OK.


Specifying Implementation Flow Options

You can specify options that control how the Flow Engine implements a design, configures a device, creates netlist files, and generates reports, timing data, and configuration data. The available options depend on the target device family.

You can specify these options by choosing settings within the Options dialog box. You can set implementation, simulation, and configuration options. The implementation options control how the software translates, maps, places, routes, and optimizes an FPGA design and how it translates and fits a CPLD design. The simulation options control the creation of netlists in terms of Xilinx primitives, allowing you to perform simulation and back-annotation. The configuration options define the initial configuration parameters, the startup sequence, and readback capabilities.

Changes you make in the Options dialog box are applied to the implementation revision that was selected when you invoked the dialog box. The Flow Engine picks up changes after the currently running process is finished if a flow is running, or when you implement your design if no flow is running.

To specify implementation flow options

1.	To open the Options dialog box, select Options from the Design menu or click the Set Options toolbar button.

2.	If you are targeting an FPGA, do the following in the Options dialog box.

a.	Select a Place & Route Effort Level setting. A setting closer to High Effort provides better place and route results at the expense of longer run times.

b.	To modify the default implementation options, click the Edit Options button to the right of the Implementation field. These options affect the Translate, Map, and Place&Route steps in the implementation flow.

c.	To create timing simulation data, select one of the simulators in the drop-down list box next to the Simulation field. To edit the default option settings, click the Edit Options button to the right of the Simulation field. Select OFF if you do not want to generate simulation data.

Note:  The Edit Options button is disabled if you set Simulation to OFF.

d.	To modify the default configuration options, click the Edit Options button to the right of the Configuration field. These options affect the Configure step in the implementation flow. Select OFF if you do not want to generate configuration data.

Note:  The Edit Options button is disabled if you set Configuration to OFF.

e.	Click OK.

3.	If you are targeting a CPLD, do the following in the Options dialog box.

a.	In the Implementation Options field, select Area, Balanced, or Speed for the CPLD Optimization Style, or select User Defined and choose a set of default options you can edit or an option template you created with the Template Manager from the drop-down list.

b.	To edit your User Defined options, click the Edit Options button. These options affect the Translate, Fit, and Bitstream steps in the implementation flow.

c.	To create timing simulation data, select one of the simulators in the drop-down list box next to the Simulation field. To edit the default option settings, click the Edit Options button to the right of the Simulation field. Select OFF if you do not want to generate simulation data.

Note:  The Edit Options button is disabled if you set Simulation to OFF.

d.	Click OK.

4.	Click OK to maintain your settings and exit the Options dialog box.

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See also

Working with Templates


Implementing a Design

You can implement your design in an automatic step from the Design Manager. When you implement your design automatically, the Flow Engine implements your design to completion. The Flow Engine implements the "last" revision, the revision that is bottommost in the Design Manager project view.

You can implement your design with default values set for copying guide, floorplan, and constraint file data and default values for implementation flow options, or you can set your own values. If you want to set your own values, follow the procedures described in the following sections.

Specifying Implementation Flow Options

Setting a Constraints File

Setting a Guide File

Setting Floorplan Files

Note:  If you want to implement your design in separate steps, obtain help from within the Flow Engine.

To implement a design

1.	Select Implement from the Design menu or click the Implement toolbar button.

One of the following occurs.

•	If you altered your source design, the software opens the New Version dialog box. The Design Manager creates a new version and revision and the Flow Engine implements this new revision.

See Creating a New Design Version for more information on setting the options in this dialog box.

•	If you did not alter the source design or part type, the Smart Flow Engine appears and implements your design starting with the appropriate step.

When processing is complete, the Smart Flow Engine closes and the Implement Status dialog box appears.

Note:  The Flow Engine is run on the "last" revision regardless of the currently selected revision. To implement a revision other than the "last" one, follow the procedure in Re-Implementing a Design.

2.	In the Implement Status dialog box, click Reports to view the reports generated by the Flow Engine or click View Log File to view the implementation log file.

Note:  At this point you can also perform timing simulation, if you set options as described in Producing Timing Simulation Data, and program the device. Timing simulation is described in the interface user guide for your system. Device programming is described in the programmer user guide for your system.


Re-Implementing a Design

If you want to automatically implement an implementation revision that is not your "last" revision, use the following procedure.

To re-implement a design

1.	In the Design Manager, select an implementation revision.

2.	Right-click on the revision.

3.	Select Re-Implement.

The Flow Engine determines where it should start running in the flow and implements your revision to completion.

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See also

Implementing a Design


Setting a Constraints File

You can use a user constraints file (design_name.ucf) to control the implementation of your design. The constraints file can contain information on the placement of I/O pins and blocks of logic and timing requirements for the design.

If you want to control the implementation of your design with a constraints file, you can specify this file in the Set Constraints File dialog box. The software tries to implement your design to meet the specified timing requirements and other constraints.

To set a constraints file

1.	Select Set Constraints File from the Design menu.

2.	In the Set Constraints File dialog box, make sure Copy Constraints Data From is selected.

3.	In the drop-down list box, select one of the following.

•	A revision that contains the user constraints file (UCF) you want to use for this implementation

•	None if you do not want to copy constraints data

•	Custom to guide from a specific file

If you select Custom, type the name of a specific file in the Constraints File field of the Custom dialog box, or click Browse to open a file selection dialog box in which you can select an existing UCF file.

4.	In the Set Constraints File dialog box, click OK.

When you implement the design, the Flow Engine uses the copied data to constrain the implementation.

Note:  This procedure describes how to copy data to an existing implementation revision. If you want to copy data to a new design version or implementation revision, use the Copy Persistent Data option described in Creating a New Design Version or Creating a New Implementation Revision.

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See also

Generating Pin Locking Constraints


Setting a Guide File

You can select a previously routed, or fitted implementation revision or a guide file to use as a guide for implementation. The procedure for guiding your implementation is the same for FPGAs and CPLDs. However, the way the design is guided differs between the two.

When guiding an FPGA design, the software attempts to use the guide for placing logic and routing signals for the current implementation revision of the design. This can reduce the amount of time the software takes to place and route. Guiding a design for an FPGA works as follows.

•	If a component in the new design has the same name as that of the guide design or file, it is placed as in the guide.

•	If an unnamed component in the new design is the same type as a component within the guide, it is placed as in the guide.

•	If the signals attached to a component in the new design match the signals attached to the component of the guide, the pins are swapped to match the guide, where possible.

•	If the signal names in the input design match the guide, and have the same sources and loads, the routing information from the guide design is copied to the new design.

After these components and signals are placed and routed, the remainder of the logic is placed and routed. If you have made only minor changes to your design and want the remaining logic placed and routed exactly as in your guide design, select the Match Guide Design Exactly option. This option locks the placement and routing of the matching logic so that it cannot change to accommodate additional logic.

Note:  Setting the Match Guide Design Exactly option is not recommended for synthesis based designs.

For CPLDs, each time you implement your design, a guide file is created (design_name.gyd) which contains your pinout information. You can reuse this file in subsequent iterations of your design if you want to keep the same pinouts. If you select a valid implementation revision or guide file name, the pinouts from that file will be used when the design is processed.

Note:  You can override guide file locations by assigning locations in your design file or constraints file.

To set a guide file

1.	Select Set Guide File(s) from the Design menu.

2.	In the Set Guide File(s) dialog box, make sure Copy Guide Data From is selected.

3.	In the drop-down list box, select one of the following.

•	A revision that contains the guide file you want to use for this implementation

•	None if you do not want to copy a guide file

•	Custom to guide from any mapped or routed file for FPGAs or fitted file for CPLDs, including designs not generated from within the Design Manager

If you select Custom, type the name of a mapped, routed, or fitted file in the Guide File field of the Custom dialog box, or click Browse to open a file selection dialog box in which you can select an existing file. Choose an NCD file for FPGAs or a GYD file for CPLDs. You can also specify a mapping guide file for FPGAs.

Note:  The implementation revision or revision data is based on a placed and routed design. Guide from a placed and routed file rather than a mapped file to reduce runtime. To guide from a mapped file, you must use the Custom option. If you use this option, you cannot guide mapping using the Set Floorplan File(s) command. Guided mapping is not supported for Virtex devices.

4.	In the Set Guide File(s) dialog box, make sure Enable Guide is selected.

By default, this option is enabled and instructs the software to use the specified guide file. If you do not want to constrain your design but want to keep your guide file intact, disable this option.

5.	For FPGA devices, select Match Guide Design Exactly if you want to lock the placement and routing of matching logic.

If you do not select this option, the guide files are used as a starting point only. This allows the mapper, placer, and router greater flexibility in accommodating design modifications, often resulting in greater overall success.

Note:  For synthesis-based designs, use the Match Guide Design Exactly option only if the guide file is from the same design version.

6.	Click OK.

When you implement the design, the Flow Engine uses the specified file to guide the implementation.

Note:  This procedure describes how to copy data to an existing implementation revision. If you want to copy data to a new design version or implementation revision, use the Copy Persistent Data option described in Creating a New Design Version or Creating a New Implementation Revision.

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See also

Setting Floorplan Files


Setting Floorplan Files

When you use the Floorplanner, an MFP file is generated that contains mapping information. You can instruct the Design Manager to use this file as a guide for mapping an implementation revision using the Set Floorplan File(s) command. To use this command, you must select an implementation revision that has been mapped and modified using the Floorplanner. For more information on using the Floorplanner, see the Floorplanner Guide.

Note:  If you use the Set Floorplan File(s) command you cannot guide mapping using the Set Guide File(s) command Custom option. The Set Floorplan File(s) command is available for the XC4000, Virtex, Spartan, and Spartan2 device families only.

To set floorplan files

1.	Select Set Floorplan File(s) from the Design menu.

2.	In the Set Floorplan File(s) dialog box, make sure Copy Floorplan Data From is selected.

3.	In the drop-down list box, select one of the following.

•	A revision that contains the floorplan files you want to use for this implementation

•	None if you do not want to copy floorplan data

•	Custom to guide from any mapped file in your file system, including designs not generated from within the Design Manager

If you select Custom, type the name of a specific file in the Floorplanning File field of the Custom dialog box, or click Browse to open a file selection dialog box in which you can select an existing file. Specify an FNF file for the Floorplanning File field and an MFP file for the Floorplanned Guide File field.

4.	In the Set Floorplan File(s) dialog box, make sure Enable Floorplan is selected.

Note:  By default, this option is enabled and instructs the software to use the specified floorplan file. If you do not want to guide your design but want to keep your floorplan file intact, disable this option.

5.	Click OK.

The Flow Engine uses the selected file to guide the implementation.

Note:  This procedure describes how to copy data to an existing implementation revision. If you want to copy data to a new design version or implementation revision, use the Copy Persistent Data option described in Creating a New Design Version or Creating a New Implementation Revision.

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See also

Setting a Guide File


Viewing Reports

The Flow Engine generates various reports which you can view in the Report Browser. The Report Browser opens reports for the selected implementation revision.

To view reports

1.	Select Report Browser from the Utilities menu or click the Browse Reports toolbar button.

The Report Browser window opens and displays reports for the active implementation revision.

2.	In the Report Browser window, double-click the report icon for the report you want to view.

The report is displayed in the standard text editor that you specified using the Preferences command from the File menu.

Note:  The icons change appearance to indicate whether or not you have read a report. A yellow mark in the upper left corner of the report icon indicates that the report has been generated but not read. A report icon without this mark indicates that the report has been generated and read.


Producing Timing Reports

You can generate timing reports after you implement your design using the Produce Timing Reports command. You can use this command if Map for FPGAs or Fit for CPLDs has completed successfully. The timing report created is based on the state of your design when you run the command.

Note:  If you select the appropriate options in the Timing Reports tab of the Implementation Options dialog box before you implement your design, the software automatically generates timing reports with the Map and Place&Route steps. See Specifying Implementation Flow Options for more information on making settings in the Implementation Options dialog box.

To produce timing reports

1.	Select Produce Timing Reports from the Utilities menu.

2.	In the Produce Timing Report dialog box, select a timing report format.

The timing report is created and placed in the Report Browser.

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See also

Viewing Reports


Generating Pin Locking Constraints

You can generate pin locking constraints in your UCF file for use with other Xilinx implementation tools. Pinout information is taken from a placed and routed NCD file for FPGAs or a fitted GYD file for CPLDs.

To generate pin locking constraints

1.	Select Lock Pins from the Design menu.

2.	In the confirmation dialog box, click Yes.

Pin locking constraints that you created with this command are added to your UCF file in the PINLOCK section.

3.	After the constraints are added, the Lock Pins Status dialog box appears. Click View Lock Pins Report to view the report.

You can view the pinouts using the Constraints Editor. See the Constraints Editor Guide for more information.

Note:  If you want to view the report after you have dismissed the Lock Pins Status dialog box, use the Lock Pins Report command from the Utilities menu.

_______

See also

Setting a Constraints File


Producing Timing Simulation Data

The Flow Engine can produce timing simulation data for use in a third party simulation tool. This data is produced for the selected implementation revision.

To produce timing simulation data

1.	To open the Options dialog box, select Options from the Design menu or click the Set Options toolbar button.

2.	Select one of the simulators in the drop-down list box next to the Simulation field.

3.	To edit the default option settings, click the Edit Options button to the right of the Simulation field.

Note:  If you set Simulation to OFF, no timing simulation data is created and the Edit Options button is disabled.

4.	Make settings in the Simulation Options dialog box and click OK.

5.	Click OK.

When you implement the design, the Flow Engine produces timing simulation data files. Each time the data is produced, it is automatically exported to your design directory. You can use these files to simulate the design with a supported third party simulation tool.


Exporting Design Data

You can export design data created in the Design Manager to other environments. The Design Manager exports design data for the selected implementation revision.

To export design data

1.	Select Export from the Design menu.

2.	In the Export Options field of the Export dialog box, select the type or types of data to export, whether Physical Design Data, Timing Simulation Data, or Configuration Data.

The associated files appear in the Files to Export field.

3.	Enter a directory path in the Export To field or click Browse to browse for a directory.

4.	Click OK.


Running Multiple Place and Route Passes

Running multiple place and route passes allows you to automatically generate multiple place and route solutions for a design. The Place and Route process offers both the ability to generate a determinate, repeatable solution by using the same starting point, or cost table, and the ability to generate a range of unique solutions by using different cost tables.

The FPGA Multi-Pass Place & Route command automates the ability to run Place and Route several times with different cost tables. It scores each place and route pass and uses the score to determine the best passes to save. Scores are based on factors such as the number of unrouted nets, the delays on nets, and conformity to your timing constraints. The passes you save appear as implementation revisions in the Design Manager project view.

On average, design speed from an arbitrary multiple pass place and route will vary plus or minus 5 to 10% from the median design speed across all cost tables. About 1/3 of the cost tables will result in speeds within 5% of the median, 1/3 in the 5 to 10% range, and 1/3 in 10 to 15% range. When comparing performance from the absolute worst cost table to the absolute best, a spread of 25 to 30% is possible.

Note:  Ranges are narrower for Virtex devices and higher for XC4000 devices.

Use the FPGA Multi-Pass Place & Route command in the following situations.

•	You want to evaluate whether worse than expected results are due to a poor starting point or cost table.

In this case, run multiple place and route passes at any time during the design cycle by running 3 or 4 cost tables.

•	You made small changes to a design at the end of the design cycle and performance falls 5 to 10% as a result of these changes.

In this case, run 5 to 10 cost tables.

If you are working on a workstation, you can use the Nodelist File option to execute the place and route process on multiple machines. This significantly reduces the run time.

Note:  The FPGA Multi-Pass Place & Route command is supported for the FPGA device families only. Using the FPGA Multi-Pass Place & Route command is not recommended for every design iteration. If you need the top performing cost tables to meet design performance, your design should be modified to remove one or more logic levels.

To run multiple place and route passes

1.	Select FPGA Multi-Pass Place & Route from the Design menu.

2.	In the FPGA Multi-Pass Place & Route dialog box, specify a placement initialization value in the Initial Placement Seed (Cost Table) field.

The placement initialization value sets the number with which to begin the place and route attempts. Each pass receives an incremental value. The value you choose corresponds to a cost table index which initializes the place and route algorithms.

3.	In the Place & Route Passes to Execute field, specify the number of place and route passes to attempt.

4.	In the Save N Best Passes field, specify the number of place and route passes to save.

The software saves the best passes based on the iteration design scores.

5.	To change the default prefix of the pass names, enter a new name in the Prefix for Derived Revisions field. The default prefix is rev#.

6.	If you are working on a workstation, you can click the Nodelist File Browse button to choose a nodelist file that you generated.

This file allows you to use multiple machine (nodes) that are networked together to run the place and route passes. For more information on generating a nodelist file and setting up environment variables, see the Development System Reference Guide.

7.	In the FPGA Multi-Pass Place & Route dialog box, click Run.

The Design Manager creates implementation revisions for the number of passes you specified in the Save N Best Passes field. After the passes are complete, the FPGA Multi-Pass Place & Route Status dialog box appears. Click View Log File to view the logfile or click View Summary Report to view the summary report.


Working with Templates

An option template is a group of implementation flow option settings. Instead of setting options each time you create an implementation revision, templates provide a convenient way to have several groups of option settings that you can select from when you implement a design. For example, you can have a template for quick place and route and another one for maximum placement effort.

The three types of option templates are implementation, simulation, and configuration templates. The implementation templates control how the software translates, maps, places, routes, and optimizes an FPGA design and how it translates and fits a CPLD design. The simulation templates control the creation of netlists in terms of the Xilinx primitive set, allowing you to perform simulation and back-annotation. The configuration templates set options which define the initial configuration parameters, the startup sequence, and readback capabilities.

To work with templates

1.	In the Design Manager, select Template Manager from the Utilities menu.

In the Template Manager dialog box, select the appropriate device family in the Family drop-down list.

2.	Select either Implementation Templates, Simulation Templates, or Configuration Templates to specify the type of template with which to work.

Note:  Configuration options are supported for the FPGA device families only. There are no configuration options for the CPLD family.

3.	Create and modify templates from this dialog box as described in the following sections.

Creating a Template

Editing a Template

Setting Custom Template Options

Using a Template


Template Manager Family Usage

The following table shows which template family to select based on the FPGA or CPLD family you are targeting.

	Targeted Device Family	Template Family
	XC3000A/L	xc3000
	XC3100A/L	xc3000
	XC4000E/L	xc4000
	XC4000EX/XL/XV/XLA	xc4000
	XC5200	xc5200
	Spartan/XL	spartan
	Spartan2	spartan2
	Virtex	virtex
	XC9500/XL/XV	xc9500


Creating a Template

You can choose to alter the default templates or create your own. To create your own, use the following procedure.

To create a new template

1.	In the Template Manager dialog box, Click New.

2.	In the New dialog box, type a name for the new template.

3.	Click OK.

The name of the new template is added to the option templates list in the Template Manager dialog box.

_______

See also

Editing a Template

Setting Custom Template Options

Using a Template


Editing a Template

After you create an option template, you can edit the template using the following procedure.

To edit a template

1.	In the Template list of the Template Manager dialog box, click the name of the template that you want to edit.

2.	Click Edit.

The Implementation, Simulation, or Configuration Options dialog box opens, depending on which type of template you are working with.

3.	Select the desired settings.

The available settings depend on the device family and the template type.

4.	Click OK.

The Template Manager saves the options settings and closes the Implementation, Simulation, or Configuration Options dialog box.

_______

See also

Creating a Template

Setting Custom Template Options

Using a Template


Implementation, Simulation, and Configuration Options Dialog Boxes

The options in the Implementation, Simulation, and Configuration Options dialog boxes vary depending on the device family. Click the following links for more information.

•	For information on the settings in the Implementation Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

XC9500

•	For information on the settings in the Simulation Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

XC9500

•	For information on the settings in the Configuration Options dialog box, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200


Setting Custom Template Options

The options available in the option templates permit you to set the most commonly used options. If you want to set more advanced options, use the Customize feature in the Template Manager.

To set custom template options

1.	In the Template Manager dialog box, select a template from the Template List.

2.	Click Customize.

3.	In the Customize Options dialog box, select the program name from the Program Name drop down list box.

4.	Enter the option names in the Program Options field. Enter the options as they would appear on the command line. To open a file that lists the options and usage messages associated with the selected program name, click List Options.

Note:  Any program options you have entered previously are saved and appear the next time you open this dialog box.

5.	Click Set.

The program and option names are added to the Template Custom Options list box.

6.	Repeat steps 3 through 5 for each program and option you want to enter.

7.	To remove a program, click the program in the Template Custom Options field and click Delete.

8.	Click OK in the Customize Options dialog box.

Note:  It is possible to enter options in the Customize Options dialog box that can conflict with normal Flow Engine options.

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See also

Creating a Template

Editing a Template

Using a Template


Using a Template

After you create a template, you must specify the template to use in the Options dialog box before you implement your design.

To use the template

1.	To open the Options dialog box, select Options from the Design menu or click the Set Options toolbar button.

2.	If you are targeting an FPGA, do the following in the Options dialog box.

a.	If you created an implementation options template, select the appropriate template name from the drop-down list box next to the Implementation field.

b.	If you created a simulation options template, select the appropriate template name from the drop-down list box next to the Simulation field.

c.	If you created a configuration options template, select the appropriate template name from the drop-down list box next to the Configuration field.

3.	If you are targeting a CPLD, do the following in the Options dialog box.

a.	If you created an implementation options template, select User Defined in the Implementation Options group box and select the appropriate template name from the drop-down list box.

b.	If you created a simulation options template, select the appropriate template name from the drop-down list box next to the Simulation field.

4.	Click OK to maintain your settings and exit the Options dialog box.

5.	Implement your design.

_______

See also

Creating a Template

Editing a Template

Setting Custom Template Options


1 2 3 4 (File Menu)
1, 2, 3, 4 (File Menu)

The File menu displays up to four of the most recently used projects. To open a project, click on the appropriate file listed in the menu.


About Design Manager (Help Menu)

Use this command to display program information, including the software version and serial number, and the copyright notice. A dialog box displays this information.


Chip Viewer (Tools Menu)

Use this command to launch the Chip Viewer. This tool presents a graphical view of the final fitting report for CPLDs. You can use the Chip Viewer before or after the Fitting process.

If you run the Chip Viewer before Fitting, the viewer reads from the design netlist. Select a device to get basic design information, set I/O assignments and pin-locking, and modify the UCF file.

If you run it after Fitting, the viewer reads the fitting results in the .vm6 file. It allows you to view the final fit and all pin assignments, connections between macrocells and details about macrocell use, and power settings and slew rates.

Note:  The Chip Viewer is supported for CPLD device families only.


Constraints Editor (Utilities Menu)

Use this command to launch the Constraints Editor. This tool allows you to create new constraints and edit existing ones after running the Translate step in the Flow Engine.

The Constraints Editor accepts NGD and, optionally, UCF files as input and writes out a valid UCF file. You can use this valid UCF file as input to an automatic implementation of a revision or to the Translate step, if you are implementing a revision in separate steps.

For additional information, see the Constraints Editor Guide.


Copy Revision (Design Menu)

Use this command to make a copy of the currently selected implementation revision. This creates a new implementation revision which contains the same data as the selected implementation revision. When you use the Copy Revision command, the Copy As dialog box opens in which you can type a name for the implementation revision copy. The Design Manager displays a new implementation revision icon in the project view.

Copy Revision Dialog Box

Copy As

Type a name for the implementation revision copy.


Delete (Design Menu)

Warning:  When deleting an item from the project view, the Design Manager deletes the item and all accompanying data. Deleted data cannot be recovered.

Use this command to delete the currently selected project, design version, or implementation revision. Select the appropriate icon and select Delete from the Design menu or press the Delete key on your keyboard. You are prompted to confirm that you really want to delete the selected data.

_______

See also

Deleting Items from the Project View


Delete Project (File Menu)

Warning:  When deleting a project, the Design Manager deletes the project and all accompanying data. Deleted data cannot be recovered.

Use this command to delete a project along with all its associated files in the project directory. This command opens the Delete Project dialog box. You are presented with a list of projects from which you can select a project to delete. To delete a project, select a project and click Delete.


Delete Project Dialog Box

Xilinx Projects

Select a project to delete.

Delete

Click Delete to exit the dialog box and delete the selected project.

Remove From List

Click Remove From List to exit the dialog box and remove the project from the most recently used project list in the File menu. This option removes the project from the list but does not delete the project and all accompanying data.

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See also

Delete Project (File Menu)


Exit (File Menu)

Use this command to close the current project and exit the Design Manager. All data is saved automatically upon exit. You are prompted to confirm that you really want to quit.


Export (Design Menu)

Use this command to open the Export dialog box and export your design data. This command is useful for transferring design data created in the Design Manager to other environments.

Note:  The Flow Engine automatically exports certain files to your design directory based on the targets selected in the Options dialog box.

_______

See also

Exporting Design Data


Export Dialog Box

Use this dialog box for the following.

Exporting Design Data

Export Options

Physical Design Data

Export physical design data (design_name.ncd file for FPGAs and design_name.vm6 or design_name.gyd file for CPLDs).

Timing Simulation Data

Export timing simulation data (time_sim.edn, time_sim.sdf, time_sim.v, time_sim.vhd, and time_sim.xmm files).

Configuration Data

Export configuration data (design_name.bit and design_name.ll files for FPGAs and design_name.jed for CPLDs).

Files To Export

This list box shows the files to be exported based on the selections made in the Export Options area.

Export To

Type the directory path and name in which to save the exported data. Click Browse to open a directory selection dialog box in which you can select a directory for the exported data.

_______

See also

Export (Design Menu)


Floorplanner (Tools Menu)

Use this command to launch the Floorplanner. The Floorplanner is a graphical placement tool that gives you control over placing a design into a target FPGA using a "drag and drop" paradigm with the mouse pointer.

The Floorplanner's Design window displays a hierarchical representation of the design, using hierarchy structure lines and colors to distinguish the different hierarchical levels. The Floorplan window displays the floorplan of the target device into which you place logic from the hierarchy.

For additional online help for this tool, obtain Help from within the Floorplanner.

Note:  The Floorplanner is supported for all XC4000 families, Virtex, Spartan/XL, and Spartan2 FPGA device families only.


Flow Engine (Tools Menu)

Use this command to launch the Flow Engine. Use the Flow Engine to implement a design. You can set implementation and flow options from within the Flow Engine.

For additional online help for this tool, obtain Help from within the Flow Engine.

_______

See also

Implementing a Design


Flow Log File (Utilities Menu)

Use this command to view the Flow Engine log file in a separate window. The log file contains all of the messages displayed for the programs run during the implementation process.


FPGA Design Editor (Tools Menu)
FPGA Editor (Tools Menu)

Use this command to launch the FPGA Editor. The FPGA Editor is a graphical tool that allows you to display and configure FPGAs. You can use the FPGA Editor to edit design logic, logic placement, and signal routing.

Use the FPGA editor before the Place&Route step to place and route critical components. You can also use the editor to manually finish placement and routing if the Route process does not completely route your design.

For additional online help for this tool, obtain Help from within the FPGA Editor.

Note:  The FPGA Editor is supported for the FPGA device families only.


FPGA Multi-Pass Place & Route (Design Menu)

Use this command to run multiple place and route passes on an implementation revision. You can indicate the number of place and route passes the software should run and the number of passes you want to save. Each pass you save is added as an implementation revision in the Design Manager project view. When you use this command, the FPGA Multi-Pass Place & Route dialog box appears in which you can make these settings.

After you run the multi-pass place and route (MPPR) passes, the FPGA Multi-Pass Place & Route Status dialog box appears. This dialog box shows the design version name and the status of your placed and routed design.

For more information on cost tables, best passes, and on generating a nodelist file, see the Development System Reference Guide.

Note:  This command is supported for the FPGA device families only. In order to accomplish the MPPR runs, the Flow Engine generates temporary (tmp) files in your working directory. If MPPR does not complete successfully, the tmp files remain in the Design Manager project view.

_______

See also

Running Multiple Place and Route Passes


FPGA Multi-Pass Place & Route Dialog Box

Use this dialog box for the following.

Running Multiple Place and Route Passes

Initial Placement Seed (Cost Table)

Specify a placement initialization value with which to begin the place and route attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value.

The number you choose corresponds to a cost table index and results in different place and route strategies. Cost tables assign weighted values to relevant factors such as constraints specified in the input file (for example, certain components must be in certain locations), the length of connections, and the available routing resources. Choose a number from 1 to 100. The default is 1.

Note:  Cost tables are fixed from one run to the next.; however, cost tables are not an ordered set. There is no correlation between a cost table's number and its relative value.

Place & Route Passes to Execute

Specify the number of place and route passes to attempt. Choose a number from 1 to 100. The default is 1.

Save N Best Passes

Specify the number of place and route passes to save. The software saves the specified number of passes. Choose a number from 1 to 100. The default is 1.

This option compares every result to every other result and leaves you with the best passes. The best outputs are determined by a score assigned to each output design. This score takes into account such factors as the number of unrouted nets, the delays on nets, and conformance to your timing constraints. The lower the score, the better the design.

Prefix for Derived Revisions

Enter a prefix for the name of the passes to be run, if you do not want to use the default, rev#. Passes saved as revisions in the Design Manager project view follow different default naming conventions than normal revisions. The passes are named rev#_p#_#_#_#.

The default prefix, rev#, indicates the number of the revision on which the pass was based. The rest of the pass name is fixed, that is you cannot alter it. The second number, p#, indicates the number of the Multi-Pass Place & Route (MPPR) run within a given version. For example, if you run MPPR once, p will be followed by a 1. If you run MPPR a second time on a different revision within the same version, p is followed by 2. The last three numbers are based on the initial cost table, the pass number, and the number of passes saved.

Nodelist File

Click Browse to choose a nodelist file that you have generated. Choosing a nodelist file allows you to use multiple machines (nodes) that are networked together for a multi-run place and route job, significantly reducing the total amount of elapsed time to completion. The nodelist file contains a list of the node names, one per line.

Note:  The Nodelist File option is only available on UNIX workstations. See the Development System Reference Guide for more information.

Run

Click Run to exit the dialog box and launch the FPGA Multi-Pass Place & Route Flow Engine.

_______

See also

FPGA Multi-Pass Place & Route (Design Menu)


FPGA Multi-Pass Place & Route Status Dialog Box

OK

Click OK to exit the dialog box.

View Log File

Click this button to view the log file.

View Summary Report

Click this button to launch the Report Browser and view the summary report generated by the FPGA Multi-Pass Place & Route Flow Engine.

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See also

FPGA Multi-Pass Place & Route (Design Menu)


Hardware Debugger (Tools Menu)

Use this command to launch the Hardware Debugger. Use the Hardware Debugger to download a design to a device, verify the downloaded configuration, and display the internal states of the programmed device.

For additional online help for this tool, obtain Help from within the Hardware Debugger.

Note:  The Hardware Debugger is supported for the FPGA device families only.


Implement (Design Menu)

Use this command to start the implementation process. This command opens the Flow Engine and begins an automatic implementation on the last implementation revision. The "last" revision is the bottommost revision in the Design Manager project view. However, if you changed your source design for the "last" revision, the New Version dialog box appears. You must set options in this dialog box before implementation can take place.

If you want to set implementation, simulation, and configuration options before you implement your design, set them in the Options dialog box. If you want to implement a revision that is not the "last" revision, right-click on a revision and select Re-implement.

After you implement a design, the Implement Status dialog box appears.

_______

See also

Implementing a Design


Implement Status Dialog Box

OK

Click OK to exit the dialog box.

View Log File

Click this button to view the log file for this implementation.

Reports

Click this button to launch the Report Browser and view reports generated by the Flow Engine.

_______

See also

Implement (Design Menu)


JTAG Programmer (Tools Menu)

Use this command to launch the JTAG Programmer. Use the JTAG Programmer to download your design and configure a a device from the XC4000, XC5200, Virtex, Spartan/XL, or Spartan2 FPGA families or XC9500 CPLD family

For additional online help for this tool, obtain Help from within the JTAG Programmer.


Lock Pins (Design Menu)

Use this command to perform pin locking by placing pinout information in the user constraints file (UCF). This command allows you to include pinout information in the UCF file for use with other Xilinx implementation tools. For FPGAs, pin locations and logical pad names are read from a placed NCD file. For CPLDs, this information is read from a fitted GYD file.

This command creates a UCF file if one does not exist. If one exists, the existing user constraints are maintained, but additional pin locking constraints are added to the file. All pinlocking constraints created by this option are written in a PINLOCK section within the UCF file.

After the constraints are generated, you can review the Lock Pins report by clicking View Lock Pins Report in the Lock Pins Status dialog box or by using the Lock Pins Report command from the Utilities menu.

_______

See also

Generating Pin Locking Constraints


Lock Pins Status Dialog Box

OK

Click OK to exit the dialog box.

View Lock Pins Report

Click this button to view the report generated during the creation of pin locking constraints in your user constraints (UCF) file.

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See also

Lock Pins (Design Menu)


Lock Pins Report (Utilities Menu)

Use this command to open the report file generated during the execution of the Lock Pins command from the Design menu. This report contains information on the constraint conflicts between the pin locking constraints in the UCF file and the design file.


New Project (File Menu)

Use this command to create a new project. This command opens the New Project dialog box in which you can specify the design file for creating your new project.

Note:  To open an existing project, use the Open Project command.

_______

See also

Creating a New Project


New Project Dialog Box

Use this dialog box for the following.

Creating a New Project

Input Design

Specify the name of the design file you want to open. You can either type the name or click Browse to open a file selection dialog box in which you can select a design file to open. The Design Manager can open the following file types.

.edf, .edn, .edif, .sedif	EDIF netlist file
.pld	PLUSASM file (CPLD only)
.xnf, .xtf, .sxnf	Xilinx hierarchical netlist file
Work Directory

Specify the name of the directory in which to put the project data files. To modify the work directory, type the path or click Browse to open a directory selection dialog box. The software automatically appends the subdirectory xproj to the selection made in the directory selection dialog box. The xproj subdirectory stores all the data files for the project.

If you want to change the name of the work directory, type over the name using the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only.

Note:  When you browse for the input design, the software automatically fills the Work Directory field with the input design directory followed by the xproj subdirectory.

Comment

Enter any comments, including options and strategies. Comments appear in the main window next to the project icon.

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See also

New Project (File Menu)


New Revision (Design Menu)

Use this command to create a new implementation revision. A new implementation revision allows you to attempt a new implementation of the design using different compile options or a different target part. When you use the New Revision command, you must make settings in the New Revision dialog box. After the new implementation revision is created, a new implementation revision icon is displayed in the project view.

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See also

Creating a New Implementation Revision


New Version (Design Menu)

Use this command to create a new design version. A new design version allows you to manage changes to the input design or logic of your design. For instance, any time your netlist data or schematic changes, you must generate a new design version.

When you use the New Version command, the New Version dialog box appears. In the New Version dialog box, enter the information necessary to define the new design version. After the new design version is created, a new design version icon is immediately added and displayed in the project view.

_______

See also

Creating a New Design Version


New Version/New Revision/Set Part Dialog Box

Use this dialog box for the following.

Creating a New Design Version

Creating a New Implementation Revision

Setting a Part

Note:  When naming versions and revisions, use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only.

Version Name

Enter the design version name.

Note:  This option is disabled when creating a new revision or setting a part.

Version Comment

Type any comments, including options and strategies. Comments appear in the main window next to the design version icon.

This option is disabled when creating a new revision or setting a part.

Part

Note:  Click Select to the right of the Part field to select a part type using the Part Selector.

Revision Name

Enter the revision name for your implementation revision.

Revision Comment

Enter any comments, including options and strategies. Comments appear in the main window next to the implementation revision icon.

Copy Persistent Data

Use the drop down list boxes to the right of the following options to copy constraint, guide, and floorplan data to the new revision.

•	Constraint File

•	Floorplan File(s)

•	Guide File(s)

When initially creating a project, the Design Manager copies constraints file data from the project directory to the revision directory. By default, floorplan and constraint file data is copied from the "last" revision, that is the bottommost revision in the project view. Guide file data is copied based on your previous setting. You can choose to copy data from a previous revision or a custom file or choose None if you do not want to copy data.

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See also

New Version (Design Menu)

New Revision (Design Menu)

Set Part (Design Menu)


Part Selector Dialog Box

Family

Select the family type.

Device

Select the device type. Only the devices that are in the family that you select in the Family field are displayed in the Devices field.

Package

Select the package type, such as PC84, PQ100, or BGA225.

Speed Grade

Select the speed grade of the device.

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See also

New Version/New Revision/Set Part Dialog Box


Open Project (File Menu)

Use this command to open an existing project. The project consists of several files but is represented in the Xilinx Project dialog box as a single file with the .xpj extension. The Open Project command opens the Open Project dialog box in which you can select a project.

To open one of the four most recently used projects, select a project from the project name list in the File menu.

Note:  To create a new project, use the New Project command.


Open Project Dialog Box

Xilinx Projects

Select the project file you want to open.

Open

Click Open to exit the dialog box and open the selected project.

Browse

Click Browse to search for a project to add to the Xilinx Projects list.

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See also

Open Project (File Menu)


Options (Design Menu)

Use this command to open the Options dialog box. This dialog box allows you to set options used in the implementation flow. Changes made in this dialog box apply to the selected implementation revision.

_______

See also

Specifying Implementation Flow Options

Producing Timing Simulation Data


Preferences (File Menu)

Use this command to open the Preferences dialog box. Use this dialog box to customize program settings, such as specifying the text editor for viewing reports. The settings you make in this dialog box are applied to all projects.

Note:  The text that specifies the editor and Web browser is not validated and is sent directly to the operating system. Verify the text before sending it.


Preferences Dialog Box

Editor for Viewing Files

Specify the text editor you want to use. This option sets the text editor for all tools in the Xilinx tool suite. Click Browse to search for an executable to use as your text editor. Click Default to select the default text editor.

Web Browser

Specify the Web browser you want to use. Click Browse to search for an executable to use as your browser. Click Default to select the default browser.

Overwrite Last Version on Implement Command

Select this option to overwrite the "last" version when you select Implement. The "last" version is the bottommost version in the Design Manager project view. By default, this option is off.

Use Part Specified in Input Design

By default, the Design Manager reads the part you set using the Part Selector. Select this option if you want the Design Manager to read the part from the input design instead. By default, this option is off.

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See also

Preferences (File Menu)


File Overwrite Dialog Box

This dialog box asks if you really want to overwrite the last version. Click Yes to confirm. If you do not want to overwrite the version, make sure the Overwrite Last Version on Implement Command is not selected in the Preference dialog box.


PROM File Formatter (Tools Menu)

Use this command to launch the PROM File Formatter. Use the PROM File Formatter to format BIT files into a PROM file compatible with Xilinx and third party PROM programmers. You can also use it to concatenate multiple bitstreams into a single PROM file for daisy chain applications.

For additional online help for this tool, obtain Help from within the PROM File Formatter.

Note:  The PROM File Formatter is supported for the FPGA device families only.


Properties (Design Menu)

Use this command to display information about a selected project, design version, or implementation revision. Depending on the selected object, this command opens the Project Properties dialog box, Version Properties dialog box, or Revision Properties dialog box.


Project Properties Dialog Box

Input Design

This field shows the name of the input design file and its directory path.

Name

This field shows the name of the selected project

Comment

This field contains the comments entered in the New Project dialog box. Use this field to edit comments and note options and strategies.

Directory

This field shows the path for the directory that contains the project files.

File List

Version List

Click this button to open the Files List dialog box for design versions.

Revision List

Click this button to open the Files List dialog box for implementation revisions.

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See also

Properties (Design Menu)


Files List Dialog Box Options
Files List Dialog Box

File

This area lists the files you specify in the Filename field.

Subdir

This area lists the subdirectories you specify in the Subdirectory field.

Filename

Specify the file or files you want to copy to the version or revision directory or subdirectory you specify. Use wildcard characters to specify multiple file names. Click Browse to search for a file.

Subdirectory (optional)

Specify the subdirectory into which you want to copy files. The subdirectory is created under the version or revision directory.

Set

Click Set to set the files and subdirectories you specify.

Delete

Click Delete to remove the selected file or subdirectory


Version Properties Dialog Box Options
Version Properties Dialog Box

Name

This field shows the name of the selected design version.

Comment

This field contains the comments entered in the New Version dialog box. Use this field to edit comments and note options and strategies.

Directory

This field shows the path for the directory that contains the design version files.

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See also

Properties (Design Menu)


Revision Properties Dialog Box Options
Revision Properties Dialog Box

Name

This field shows the name of the selected implementation revision.

Comment

This field contains the comments entered in the New Revision dialog box. Use this field to edit comments and note options and strategies.

Directory

This field shows the path for the directory that contains the implementation revision files.

Part

This field shows the part type used for the selected implementation revision.

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See also

Properties (Design Menu)


Save Project (File Menu)

Use this command to save the current project. Using this command ensures that all comments and the state of the project and design version icons are saved.

Note:  The Design Manager saves frequently so that data is almost always up to date.


Set Constraints File (Design Menu)

Use this command to bring up the Set Constraints dialog box. This dialog box allows you to identify a UCF file to constrain your design. You can specify logic placement and timing requirements in the UCF file.

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See also

Setting a Constraints File


Set Constraints File Dialog Box

Use this dialog box for the following.

Setting a Constraints File

Copy Constraints Data From

Select this option to copy a constraints file into the selected implementation revision. The software uses this file to implement the design.

From the drop-down list box, select a revision that contains the UCF file you want to use, or select Custom to open the Custom dialog box and select a specific file. Select None if you do not want to constrain your design based on a previous revision or custom file.


Custom (Constraints File) Dialog Box
Custom Dialog Box

Constraints File

In the Constraints File field, type the name of a specific file, or click Browse to open a file selection dialog box in which you can select an existing UCF file.


Set Floorplan File(s) (Design Menu)

Use this command to open the Set Floorplan File(s) dialog box. Use this dialog box to instruct the Design Manager to use information generated by the Floorplanner as a guide for mapping. The Design Manager obtains this information from the Floorplanner MFP file. For information on how to create the MFP file, refer to the Floorplanner Guide.

Note:  This command is available for the XC4000, Virtex, Spartan, and Spartan2 device families only. If you use this command, you cannot guide mapping using the Set Guide File(s) command Custom option.

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See also

Setting Floorplan Files


Set Floorplan File(s) Dialog Box

Use this dialog box for the following.

Setting Floorplan Files

Copy Floorplan Data From

Select this option to copy a floorplan file into the selected implementation revision. If the Enable Floorplan option is selected, the software uses this file to implement the design.

From the drop-down list box, select a revision that contains the floorplan files you want to use, or select Custom to open the Custom dialog box and guide from a specific file. Select None if you do not want to copy floorplan data from a previous revision or custom file.

Enable Floorplan

By default, this option is enabled and instructs the software to use the specified floorplan file. If you do not want to guide your design in this revision but want to keep your floorplan file intact, disable this option.

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See also

Set Floorplan File(s) (Design Menu)


Custom (Floorplan Files) Dialog Box
Custom Dialog Box

Floorplanning File

Select an FNF file. Click Browse to search for a file.

Floorplanned Guide File

Select an MFP file. Click Browse to search for a file.


Set Guide File(s) (Design Menu)

Use this command to open the Set Guide File(s) dialog box in which you can specify the guide file. A guide file is created each time you implement your design and you can reuse this data to maintain mapping, placing, and routing consistency for FPGAs and fitting consistency for CPLDs. You can guide from an implementation revision or from a custom guide file. Guiding your design can reduce the amount of time taken for implementation.

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See also

Setting a Guide File


Set Guide File(s) Dialog Box

Use this dialog box for the following.

Setting a Guide File

Copy Guide Data From

Select this option to copy a guide file into the selected implementation revision. If the Enable Guide option is selected, the software uses this file to implement the design.

From the drop-down list box, select a revision that contains the guide files you want to use, or select Custom to open the Custom dialog box and guide from a specific file. Select None if you do not want to guide from a previous revision or custom file.

Note:  If you select a revision, it must be a placed and routed revision. If you want to guide from a mapped file, you must use the Custom option.

Enable Guide

By default, this option is enabled and instructs the software to use the specified guide file. If you do not want to guide your design in this revision but want to keep your guide file intact, disable this option.

Match Guide Design Exactly (FPGA only)

Select this option to lock the placing and routing of the matching logic. This option is useful when you have made minor changes to the design and want to ensure that matching logic is not changed to accommodate additional logic.

If you do not select this option, the guide files are used as a starting point only. This allows the mapper, placer, and router greater flexibility in accommodating design modifications.

Note:  This option is not recommended for synthesis based designs. This option is supported for the FPGA device families only.

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See also

Set Guide File(s) (Design Menu)


Custom (Guide Files) Dialog Box
Custom Dialog Box

Guide File

Specify an NCD file to guide placing and routing for FPGAs. Specify a GYD file to guide fitting for CPLDs. Click Browse to search for a file.

Mapping Guide File

Specify a file to guide mapping for FPGAs. This option is not supported for CPLDs. Click Browse to search for a file.

Note:  If you use this option, you cannot guide mapping using the Set Floorplan File(s) command.


Set Part (Design Menu)

Use this command to open the Set Part dialog box. This command allows you to create a new implementation revision targeted for the part you choose.

Note:  After the implementation revision is created, the part cannot be changed.


Template Manager (Utilities Menu)

Use this command to create or modify your implementation, simulation, and configuration option templates using the Template Manager dialog box. Templates provide a convenient way to have several groups of option settings that you can select from when you implement a design. Implementation and simulation options are supported for FPGAs and CPLDs. Configuration options are supported for FPGAs.

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See also

Working with Templates


Template Manager Dialog Box

Use this dialog box for the following.

Working with Templates

Family

Select the device family of the option templates you want to create or modify.

Implementation Templates

Select this option to work with implementation option templates. Implementation options control how an FPGA design is translated, mapped, optimized, placed, and routed and how a CPLD design is translated and fitted.

Simulation Templates

Select this option to work with simulation option templates. Simulation options control the creation of netlists for front and back-end simulation. Simulation can be performed on both pre- and post-routed designs.

Configuration Templates

Select this option to work with configuration option templates. Configuration options control the configuration startup, readback, and parameters for the device.

Note:  Configuration templates are available for the FPGA device families only.

Template List

Select an option template with which to work. If you are working with simulation options, select the name of your simulator.

Close

Close the Template Manager.

New

Add a new option template. This option allows you to create multiple templates with different settings.

Edit

Open the Implementation, Simulation, or Configuration Options dialog box to view and modify the settings for a particular option template.

Copy

Make a copy of the selected option template.

Rename

Rename the selected option template. You cannot rename the default set of options.

Delete

Delete the selected option template. You cannot delete the default set of options.

Import

Import a template file. A template file contains one or more option templates. Clicking Import opens a standard file selection dialog box in which you can choose a template file to import. The templates read from the file appear in the Template List area of the Template Manager. You can transfer a template from one Design Manager project to another by using the Export command followed by the Import command.

Export

Export option templates to a template file. A template file contains one or more option templates. You can select the templates you want to export from the Template List area of the Template Manager. Clicking Export opens a standard file selection dialog box in which you can specify the template file name. You can transfer a template from one Design Manager project to another by using the Export command followed by the Import command.

Customize

Open the Customize Options dialog box. Use this dialog box to specify custom template options that are not supported by the standard options provided in the Design Manager. You can use any options that the programs support. For more information on the commands and options for the programs, refer to their user manuals.

Note:  It is possible to enter options in the Customize Options dialog box that conflict with normal Flow Engine options.

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See also

Template Manager (Utilities Menu)


Customize Options Dialog Box

Use this dialog box for the following.

Setting Custom Template Options

Note:  It is possible to enter options in the Customize Options dialog box that conflict with normal Flow Engine options. The title of this dialog box changes based on whether you are working with implementation, simulation, or configuration options.

Template Custom Options

This area lists the programs and options you specify in the Program Name and Program Options fields.

Program Name

Select name of the program or programs that you want to use from the drop-down list box. This list box contains only the programs that apply for the template type and part family that you chose.

Program Options

Specify the program options that you want to use. Enter the options as they would appear on the command line.

Note:  Any options you entered previously are saved and appear the next time you open this dialog box.

List Options

Click List Options to open a file that lists the options and usage messages associated with the selected program. If the options differ according to a device family, the options are listed broken into families. The file opens in the text editor you set using the Preferences command.

Delete

Click Delete to remove the selected program or option.

Set

Click Set to set the programs and options that you specify.

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See also

Template Manager Dialog Box


Timing Analyzer (Tools Menu)

Use this command to launch the Timing Analyzer. Use the Timing Analyzer after a design has been mapped, routed, or fitted. The Timing Analyzer performs a static timing analysis of a mapped or routed FPGA or fitted CPLD design. The static timing analysis does not include insertion of stimulus vectors.

The Timing Analyzer verifies that the delay along a given path or paths meets your specified timing requirements. It organizes and displays data that indicate the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths, and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the design.

The Timing Analyzer works with synchronous systems composed of flip-flops and combinatorial logic. In a synchronous design, signals must be stable long enough to allow the clocks to change so that setup and hold violations are avoided.

For additional online help for this tool, obtain Help from within the Timing Analyzer.


Toolbox (View Menu)

Use this command to show or hide the toolbox. For more information about the toolbox, see the Toolbox section.


Recovery Dialog Boxes

The Recover Project, Recover Version, and Recover Revision dialog boxes allow you to recover a corrupted project, version, or revision.


Recover Project Dialog Box

Input Design

Specify the name of the input design file. You can either type the name or click Browse to open a file selection dialog box in which you can select the file.

Comment

Enter any comments, including options and strategies. Comments appear in the main window next to the project icon.


Recover Version Dialog Box

Comment

Enter any comments, including options and strategies. Comments appear in the main window next to the design version icon.


Recover Revision Dialog Box

Part

Click Select to the right of the Part field to select a part type using the Part Selector.

Comment

Enter any comments, including options and strategies. Comments appear in the main window next to the implementation revision icon.


Xilinx on the Web Support and Services (Help Menu)

Use this command to open the Xilinx technical support page. Use this page to access the latest design information, to search across various resources, and to access online resources directly.

Use the Preferences command to set the Web browser of your choice. You must have Web access to use this command.


Xilinx on the Web Xilinx Home Page (Help Menu)

Use this command to open the Xilinx home page. This page contains links to the latest Xilinx announcements, technical support, and information on the company, its products, and investor relations.

Use the Preferences command to set the Web browser of your choice. You must have Web access to use this command.


Toolbar

The toolbar provides convenient access to frequently used commands. Click once on a toolbar button to execute a command. The following section briefly describes each Design Manager toolbar button and, where appropriate, provides a link to the corresponding menu command.

When you position the mouse pointer over a toolbar button, a short description, called a tool tip, appears next to the button. A longer description appears in the status bar at the bottom of the main window.

Toolbar Buttons

 Implement runs the implementation flow.

 	Set Options opens the Options dialog box.

 New Project creates a new project.

 	Open Project opens an existing project.

 	Save Project saves the current project.

 	Set Part allows you to select the device to use.

 	New Revision creates a new implementation revision.

 	Copy Revision makes a copy of the selected implementation revision.

 	Browse Reports opens the Report Browser for viewing reports.

 	Edit Project Notes opens a text editor window in which to enter notes for the project.

 	View Command History opens a command history window for viewing the history of implementation commands.

 	support.xilinx.com opens the Xilinx technical support page. Use this page to access the latest design information, to search across various resources, and to access online resources directly. You must have Web access to use this toolbar button.

Help activates context-sensitive help. After clicking this button, select a menu item or toolbar button for which you want help.


Toolbox

The toolbox provides buttons to access tools from the Xilinx Design Manager. Click once on a toolbox button to launch a tool. You can also launch these tools from the Tools menu. The following section shows each toolbox button and, where appropriate, provides a link to the corresponding menu command.

The toolbox contents depend on the implementation revision that you have chosen. Each time you select a implementation revision, the toolbox changes automatically. The toolbox contents differ for FPGA devices and CPLDs as indicated in the following section.

When you position the mouse pointer over a toolbox button, a short description, called a tool tip, appears next to the button. A longer description appears in the status bar at the bottom of the Design Manager window.

Toolbox Buttons

Flow Engine (FPGA and CPLD)

Timing Analyzer (FPGA and CPLD)

Floorplanner (XC4000, Virtex, Spartan, and Spartan2 device families only)

PROM File Formatter (FPGA only)

Hardware Debugger (FPGA only)

FPGA Editor (FPGA only)

JTAG Programmer (XC4000, XC5200, Virtex, Spartan/XL, or Spartan2 FPGA families or XC9500 CPLD family)

Chip Viewer (CPLD only)


Shortcuts

The following command shortcuts are available in the Design Manager.

Popup Menu

The following commands are active in the project view of the Design Manager main window. To access a command, select a project, design version, or implementation revision icon, press the right mouse button while positioned in the horizontal line of the selected object, and choose the command from the popup menu.

Collapse/Expand

This command expands or collapses the project or design version hierarchy. This command is the same as double-clicking on the project or design version icon. There is no equivalent menu command.

Note:  The Collapse/Expand command only applies to selected projects and design versions.

Re-Implement

Select Re-Implement to launch the Flow Engine on the selected implementation revision. The Flow Engine automatically runs on the next process that needs to be run on the revision. There is no equivalent menu command.

Note:  This command is only available when positioned over an implementation revision.

Implement

Implement to implement the "last" implementation revision, that is the bottommost revision in the Design Manager project view.

Note:  This command is only available when positioned over a project or design version.

Delete

Delete deletes the selected project, design version, or implementation revision.

Properties

Properties displays information about a selected project, design version, or implementation revision.

Keyboard

Ctrl N

Press Ctrl N to access the New Project command from the File menu.

Ctrl O

Press Ctrl O to access the Open Project command from the File menu.

Ctrl S

Press Ctrl S to access the Save Project command from the File menu.


Command History (Utilities Menu)

Use this command to open the Command History utility and display the commands and options that have already been run in the flow for the current implementation revision. This command is useful for reviewing the commands and options that were used while executing the flow.


Command History Utility

Mode

Process

This mode displays high level flow information about previously executed commands, such as optimize, map, place, and route.

Command Line

This mode displays the executed operating system commands and command line options.

Show Date and Time

This mode displays the date and time that the commands were run on the selected implementation revision.

Close

Click Close to exit the utility.

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See also

Command History (Utilities Menu)


Help Topics (Help Menu)

Use this command to display the opening screen of the Help. From the opening screen you can jump to step-by-step instructions and to various types of reference information.

After you open help, you can click the Help Topics button in the Help window whenever you want to return to the opening screen of Help.

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See also

How to Use Help


Online Documentation (Help Menu)

Use this command to open the software manuals in the default Web browser.


Options Dialog Box

The Options dialog box allows you to set implementation and simulation options for FPGAs and CPLDs and configuration options for FPGAs. The dialog box differs for FPGAs and CPLDs. Click one of the following links for more information.

Options Dialog Box (FPGA)

Options Dialog Box (CPLD)


Options Dialog Box (FPGA)

Use this dialog box for the following.

Specifying Implementation Flow Options

Producing Timing Simulation Data

Place & Route Effort Level

Use this option to specify the algorithms that the placer and router use to place and route a design. Use the Place & Route Effort Level slider bar to select an effort level setting. A setting closer to High Effort provides better place and route results at the expense of longer run times.

Program Options

Implementation

Select a set of implementation options to use from the Implementation drop-down list. Implementation options control how the software translates, maps, places, routes, and optimizes a design. These options affect the Translate, Map, and Place&Route steps in the implementation flow. A set of default implementation options and any option templates you created appear when you click this drop-down list.

Click the Edit Options button to the right of the Implementation drop-down list to open the Implementation Options dialog box. The options in this box depend on the target device family. For information on the implementation options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

Simulation

Select one of the simulators or a template you created from the drop-down list box to produce timing simulation data. This data is produced after the design is placed and routed. If you do not want to produce timing simulation data, select OFF.

Click the Edit Options button to the right of the Simulation drop-down list to open the Simulation Options dialog box. Simulation options control the creation of netlists in terms of the Xilinx primitive set, which allow you to simulate and back-annotate your design. In back-annotation, physical design data is distributed back to the logic design to perform back-end simulation. You can perform front and back-end simulation on both pre- and post-routed designs. For information on the simulation options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

Configuration

Select a set of configuration options to use in this implementation from the Configuration drop-down list. Configuration options control the configuration parameters of a device, the startup sequence, and readback capabilities. These options affect the Configure step in the implementation flow. A set of default configuration options and any option templates you created appear when you click on this drop-down list. Selecting a set of options produces configuration data after design implementation. The configuration data is used to program a device. Select OFF if you do not want to produce configuration data.

Click the Edit Options button to the right of the Configuration drop-down list to open the Configuration Options dialog box. The options in this dialog box depend on the target device family. For information on the configuration options, click one of the following device families.

Spartan

Spartan2

Virtex

XC3000

XC4000

XC5200

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See also

Options (Setup Menu)


Options Dialog Box (CPLD)

Use this dialog box for the following.

Specifying Implementation Flow Options

Producing Timing Simulation Data

Implementation Options

Select a CPLD Optimization Style, whether optimized for area, a balance of both area and speed, or speed. Implementation options control how the software translates and fits a design. These options affect the Translate, Fit, and Bitstream steps in the implementation flow.

If you want to use your own options, click User Defined as your CPLD Optimization Style and select the default set of options or an option template you created from the drop-down list box. If you want to edit these user defined options, click the Edit Options button to the right of the drop-down list to open the Implementation Options dialog box. See XC9500 Implementation Options Dialog Box for more information.

Simulation Options

Select one of the simulators or a template you created in the drop-down list box to produce timing simulation data. This data is produced after the design is fitted. If you do not want to produce timing simulation data, select OFF.

Click the Edit Options button to the right of the Simulation drop-down list to open the Simulation Options dialog box. Simulation options control the creation of netlists in terms of the Xilinx primitive set, which allow you to simulate and back-annotate your design. In back-annotation, physical design data is distributed back to the logic design to perform back-end simulation. You can perform front and back-end simulation on both pre- and post-fitted designs. See XC9500 Simulation Options Dialog Box for more information.

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See also

Options (Setup Menu)


Produce Timing Report (Utilities Menu)

Use this command to generate timing reports. You can use this command if at least Map (for FPGAs) or Fit (for CPLDs) has completed successfully. The type, title, and file name of the report depend on the state of your design when you run this command. You cannot change the file name of the report. The following table shows the report that is generated given a particular state. The timing reports are placed in the Report Browser when complete.

State	File Name	Title
Mapped (FPGA)	map_number.twr	Logic Level Timing Report #number
Routed (FPGA)	design_name_number.twr	Post Layout Timing Report #number
Fitted (CPLD)	design_name_number.twr	Post Fitting Timing Report #number
Timed	design_name_number.twr	Post Layout Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD)
Implemented	design_name_number.twr	Post Bitgen Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD)
 This command opens the Produce Timing Report dialog box in which you can set the report format.

Note:  If you step back over a state that was necessary to generate a report, the report associated with that state is removed from the Report Browser. To restore the state and the associated reports, use the Step command from the Flow menu in the Flow Engine.

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See also

Producing Timing Reports


Produce Timing Report Dialog Box

This command opens one of the following dialog boxes, depending on whether you are targeting an FPGA or CPLD. Use this dialog box to set the report format.

Produce Timing Report Dialog Box (FPGA)

Produce Timing Report Dialog Box (CPLD)


Produce Timing Report Dialog Box (FPGA)

Use this dialog box for the following.

Producing Timing Reports

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist. The default setting is 3.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSETs for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option. This is the default format.

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See also

Produce Timing Report (Utilities Menu)


Produce Timing Report Dialog Box (CPLD)

Use this dialog box for the following.

Producing Timing Reports

Summary

Select Summary to generate a report that contains summary information and design statistics.

Detailed

Select Detailed to generate a report that lists delay information for all nets and paths.

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See also

Produce Timing Report (Utilities Menu)


Project Notes (Utilities Menu)

Use this command to open a standard text editor window in which to make notes for the current project.


Report Browser (Utilities Menu)

Use this command to view reports. This command opens the Report Browser utility. This utility contains icons that represent the reports generated by the Flow Engine.

The icons change appearance to indicate whether or not you have read a report. A yellow mark in the upper left corner of the report icon indicates that the report has been generated but not read. A report icon without this mark indicates that the report has been generated and read. To read a report, double-click the report icon.

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See also

Viewing Reports


Status Bar (View Menu)

Use this command to show or hide the status bar.


Toolbar (View Menu)

Use this command to show or hide the toolbar.


Spartan Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online Help.


Spartan Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Spartan Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing minimum signal combining requirements. The default is Fit Device.

Note:  Although the CLB Packing Strategy option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Use Generic Clock Buffers (BUFGs) in Place of BUFGPs and BUFGSs

Select this option to replace primary and secondary clock buffers with generic clock buffers before mapping occurs. This option is useful when working with design entry tools that generate only BUFGPs or BUFGSs. By default, this option is off.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Spartan Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Spartan Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Spartan Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Spartan VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Spartan device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Spartan	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Spartan EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Spartan Configuration Options Dialog Box

Click the Configuration, Startup, Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan Configuration Tab

Configuration Rate

The Spartan devices use an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (5 Volt Spartan Parts Only)

Note:  These options are supported for the Spartan family only. They are not supported for the SpartanXL family.

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Outputs

Select one of the following output options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible outputs.

CMOS

Select CMOS to specify CMOS-compatible outputs.

Read from Design

Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

Note:  You cannot use these pins to set the configuration mode or use them as user I/Os.

TDO

The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin in Spartan devices. Select this option only if you do not connect an external pull-up resistor to this pin.

Configuration Pins (SpartanXL Only)

Note:  These options are supported for SpartanXL devices only.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

Power Down

The Power Down pin allows the FPGA to exist in a standby mode which consumes less power. The FPGA enters this standby mode when the Power Down pin is driven Low. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Power Down pin. Use this option if you will use the Power Down pin but will not tristate it.

PullUp

Select PullUp to enable an internal pull-up resistor on the Power Down pin. You must use this option if the Power Down pin is not connected in your design, or if the signal driving this pin could be in a tristate condition.

Spartan XL Only

5V Tolerant I/Os

This option allows a 3.3 V device circuitry to tolerate 5 V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3 V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption. By default, this option is on.

Note:  Enabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3 V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.

Enable Configuration Through the JTAG Port

This option allows BSCAN-based configuration after the device is successfully configured. By default, this option is on.

Enable the Status Bits to be Read Through the JTAG Port

This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful. By default, this option is off.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


Spartan Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the Spartan device can be synchronized with the signal on the DONE pin. Deselect this option to begin the sequence when the configuration memory is full. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Start-up Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Spartan Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


Spartan Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select this option to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select this option to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to activate or deactivate the readback capability of the configuration bitstream. To activate this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


Spartan Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


Spartan2 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online Help.


Spartan2 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Spartan2 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Map Options

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Spartan2 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Spartan2 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Spartan2 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan2 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Spartan2 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Spartan2 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Spartan2	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Note:  The following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Spartan2 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Spartan2 Configuration Options Dialog Box

Click the Configuration, Startup, or Readback tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Spartan2 Configuration Tab

Configuration Rate

Spartan2 devices use an internal configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate in megahertz (MHz) for this clock. The default is 4 MHz.

Configuration Pins

Configuration Clk

This pin is used to synchronize to an internal clock provided in the FPGA device. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Configuration Clk pin.

PullUp

Select PullUp to enable a pull-up on the Configuration Clk pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the PROG pin.

PullUp

Select Pullup to enable a pull-up on the PROG pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

Active PullUp

Select Active PullUp to drive the DONE pin High with a CMOS driver.

JTAG Pins

For more information on the following pins, see the JTAG Programmer Guide.

TCK

This pin is the JTAG test clock.The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TCK pin.

PullUp

Select PullUp to enable a pull-up on the TCK pin.

PullDown

Select PullDown to enable a pull-down on the TCK pin.

TDI

This pin is the serial data input to all JTAG instructions and JTAG registers. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDI pin.

PullUp

Select PullUp to enable a pull-up on the TDI pin.

PullDown

Select PullDown to enable a pull-down on the TDI pin.

TDO

The TDO pin is the serial data output for all JTAG instruction and data registers. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

TMS

This pin is the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TMS pin.

PullUp

Select PullUp to enable a pull-up on the TMS pin.

PullDown

Select PullDown to enable a pull-down on the TMS pin.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Enable the User ID Code

Use this option to assign a code in the User Identification Register. Enter an ID code in the Code field. This code comprises eight hexadecimal digits that are placed in the User ID Register. By default, this option is off.


Spartan2 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

JTAG Clock

Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.

Output Events

There are five major output events which occur during a device startup.

•	Done (CFG_DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

•	Release Write Enable (Global Write Enable signal deasserted)

•	Release DLL (DLL allowed to synchronize)

Depending on the setting for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Spartan2 Output Events Options Matrix

	CCLK	User Clock	JTAG Clock
DONE	C1-C6	C1, U2-U6	C1, J2-J6
Enable Outputs	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Set/Reset	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Write Enable	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release DLL	C0-C6, No Wait	C0-C1, U2-U6, No Wait	C0-C1, J2-J6, No Wait
The definitions of the possible output events settings are as follows.

C0	Before the Cclk rising edge after the length count is met

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

C5	Fifth-Cclk rising edge after the length count is met

C6	Sixth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U5	Fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U6	Sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J2	Second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J3	Third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J4	Fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J5	Fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J6	Sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

Done	When the CFG_DONE signal goes High

Keep	Holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High

No Wait	Not synchronized to the startup clock; DLL synchronizes as soon as possible

Enable Internal Done Pipe

Select this option when the startup clock is running at high speeds. If you select this option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself. By default, this option is off.


Spartan2 Readback Tab

Security

Enable Readback and Reconfiguration

This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the RDATA pin. By default, this option is on.

Generate Readback Bitstream

Select this option to create a readback bitstream file. By default, this option is off.

Disable Readback

This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.

Disable Readback and Reconfiguration

This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.


Virtex Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


Virtex Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Map Options

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


Virtex Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


Virtex Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


Virtex Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


Virtex VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the Virtex device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
Virtex	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Note:  The following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


Virtex EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


Virtex Configuration Options Dialog Box

Click the Configuration, Startup, or Readback tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


Virtex Configuration Tab

Configuration Rate

Virtex devices use an internal configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate in megahertz (MHz) for this clock. The default is 4 MHz.

Configuration Pins

Configuration Clk

This pin is used to synchronize to an internal clock provided in the FPGA device. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the Configuration Clk pin.

PullUp

Select PullUp to enable a pull-up on the Configuration Clk pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the PROG pin.

PullUp

Select Pullup to enable a pull-up on the PROG pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

Active PullUp

Select Active PullUp to drive the DONE pin High with a CMOS driver.

JTAG Pins

For more information on the following pins, see the JTAG Programmer Guide.

TCK

This pin is the JTAG test clock.The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TCK pin.

PullUp

Select PullUp to enable a pull-up on the TCK pin.

PullDown

Select PullDown to enable a pull-down on the TCK pin.

TDI

This pin is the serial data input to all JTAG instructions and JTAG registers. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDI pin.

PullUp

Select PullUp to enable a pull-up on the TDI pin.

PullDown

Select PullDown to enable a pull-down on the TDI pin.

TDO

The TDO pin is the serial data output for all JTAG instruction and data registers. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

TMS

This pin is the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The default is PullUp.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TMS pin.

PullUp

Select PullUp to enable a pull-up on the TMS pin.

PullDown

Select PullDown to enable a pull-down on the TMS pin.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Enable the User ID Code

Use this option to assign a code in the User Identification Register. Enter an ID code in the Code field. This code comprises eight hexadecimal digits that are placed in the User ID Register. By default, this option is off.


Virtex Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP_VIRTEX symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

JTAG Clock

Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.

Output Events

There are five major output events which occur during a device startup.

•	Done (CFG_DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

•	Release Write Enable (Global Write Enable signal deasserted)

•	Release DLL (DLL allowed to synchronize)

Depending on the setting for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Virtex Output Events Options Matrix

	CCLK	User Clock	JTAG Clock
DONE	C1-C6	C1, U2-U6	C1, J2-J6
Enable Outputs	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Set/Reset	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release Write Enable	C1-C6, Done, Keep	C1, U2-U6, Done, Keep	C1, J2-J6, Done, Keep
Release DLL	C0-C6, No Wait	C0-C1, U2-U6, No Wait	C0-C1, J2-J6, No Wait
The definitions of the possible output events settings are as follows.

C0	Before the Cclk rising edge after the length count is met

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

C5	Fifth-Cclk rising edge after the length count is met

C6	Sixth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U5	Fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U6	Sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J2	Second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J3	Third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J4	Fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J5	Fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J6	Sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

Done	When the CFG_DONE signal goes High

Keep	Holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High

No Wait	Not synchronized to the startup clock; DLL synchronizes as soon as possible

Enable Internal Done Pipe

Select this option when the startup clock is running at high speeds. If you select this option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself. By default, this option is off.


Virtex Readback Tab

Security

Enable Readback and Reconfiguration

This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the RDATA pin. By default, this option is on.

Generate Readback Bitstream

Select this option to create a readback bitstream file. By default, this option is off.

Disable Readback

This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.

Disable Readback and Reconfiguration

This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.


XC3000 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab or to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC3000 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC3000 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC3000 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC3000 Simulation Template Dialog Box
XC3000 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist. If you select EDIF as your netlist format, this option is on by default.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC3000 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC3000 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC3000	GR	always	active-Low
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC3000 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC3000 Configuration Options Dialog Box

Click the Configuration, Startup/Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC3000 Configuration Tab

Threshold Level

Inputs

This option affects all input pins. You cannot set individual pins. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs except for the special purpose clocks, Tclkin, Bclkin, and Pwrdwn which always require CMOS input signals.

CMOS

Select CMOS to specify CMOS compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Configuration Pin Pullups

Done/Program

Select one of the following options. The default is Pullup.

Float

Select Float to disable an internal pull-up resistor on the Done/Program (D/P) pin. The D/P pin is an open-drain output that requires a pull-up resistor to indicate the end of the configuration. If this option is selected, an external pull-up resistor should be connected to the D/P pin.

Pullup

Select Pullup to enable an internal pull-up resistor on the Done/Program (D/P) pin. This resistor has a value of 2 to 8 kilohms. The D/P pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. Turn off this option only if you intend to connect an external pull-up resistor to this pin.

Crystal Oscillator

The XC3000 family of devices contains an internal high-speed inverting amplifier which you can use to implement an on-chip crystal oscillator. To use this feature, you must include either the GXTL or OSC library element in your design and connect the appropriate external R-C crystal circuit to the amplifier. See the Xilinx Libraries Guide and The Programmable Logic Data Book for more information.

Select one of the following options. The default is Disabled.

Disabled

Select Disabled to disable the crystal oscillator.

Enabled

Select Enabled to enable the crystal oscillator.

Enabled (Divide by 2)

Select Enabled (Divide by 2) to divide the crystal oscillator frequency by two to generate a symmetrical clock signal.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


XC3000 Startup/Readback Tab

Readback

Mode

After an FPGA is configured, data can be read back and compared with the original configuration data. For security reasons, it is sometimes desirable to disable or limit readback capability. The following options control readback. The default is On Command.

Never

Select Never to disable readback completely.

Once

Select Once to enable a one-time readback.

On Command

Select On Command to enable readback on command. This option generates a .ll file.

Output Events

Done

The DONE signal indicates the completion of the configuration sequence. You can program this signal to be asserted before or after I/Os go active. The default is Before I/Os Active.

Before I/Os Active

Select Before I/Os Active to release the DONE signal one Cclk period before the outputs go active.

After I/Os Active

Select After I/Os Active to release the DONE signal one Cclk period after the outputs go active.

Reset

A global reset signal is asserted while the device is configuring during the startup sequence. You can program the release of this signal to occur before or after I/Os go active. The default is After I/Os Active.

Before I/Os Active

Select Before I/Os Active to release the Internal Reset one Cclk period before the outputs go active.

After I/Os Active

Select After I/Os Active to release the Internal Reset one Cclk period after the outputs go active.


XC3000 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use this option, Design Rule Check (DRC) runs first. After DRC, this option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC4000 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC4000 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Pack CLB Registers for

This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the Development System Reference Guide. The default is Structure.

Structure

Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.

Minimum Area

Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.

Pack I/O Registers/Latches into IOBs for

This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.

Inputs Only

Select Inputs Only to pack flip-flops or latches into input I/O cells.

Outputs Only

Select Outputs Only to pack flip-flops or latches into output I/O cells.

Inputs and Outputs

Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.

Off

Select Off to pack flip-flops or latches as specified by your design entry method.

Use Generic Clock Buffers (BUFGs) in Place of BUFGPs and BUFGSs

Select this option to replace primary and secondary clock buffers with generic clock buffers before mapping occurs. This option is useful when working with design entry tools that generate only BUFGPs or BUFGSs. By default, this option is off.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC4000 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC4000 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC4000 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC4000 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC4000 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC4000	GSR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC4000 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC4000 Configuration Options Dialog Box

Click the Configuration, Startup, Readback, Tie or Advanced tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC4000 Configuration Tab

Configuration Rate

The XC4000 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (XC4000E and XC4000EX Only)

Note:  These options are supported for the XC4000E and XC4000EX subfamilies only.

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Outputs

Select one of the following output options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible outputs.

CMOS

Select CMOS to specify CMOS-compatible outputs.

Read from Design

Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

TDO

The TDO pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.

PullUp

Select PullUp to enable a pull-up on the TDO pin.

PullDown

Select PullDown to enable a pull-down on the TDO pin.

M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.

PullUp

Select PullUp to enable a pull-up on the M0 pin.

PullDown

Select PullDown to enable a pull-down on the M0 pin.

M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.

PullUp

Select PullUp to enable a pull-up on the M1 pin.

PullDown

Select PullDown to enable a pull-down on the M1 pin

M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.

Float

Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.

PullUp

Select PullUp to enable a pull-up on the M2 pin.

PullDown

Select PullDown to enable a pull-down on the M2 pin.

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.

XC4000XLA and XC4000XV Only

5V Tolerant I/Os

This option allows a 3.3 V device circuitry to tolerate 5 V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3 V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption. By default, this option is on.

Note:  Enabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3 V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.

Enable EXPRESS Mode

This option enables express mode configuration. In this mode, configuration data is presented to the device in parallel format, and each new byte is clocked into the target device with every rising edge of the CCLK. This mode is eight times as fast as other configuration modes because data is processed at the rate of one byte per CCLK rather than one bit per CCLK. By default, this option is off.

Enable Configuration Through the JTAG Port

This option allows BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring XLA devices by toggling the TCK/TMS/TDI/TDO lines. By default, this option is on.

Enable the Status Bits to be Read Through the JTAG Port

This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful. By default, this option is off.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.


XC4000 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. CCLK is the default.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the XC4000 can be synchronized with the signal on the DONE pin. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. Deselect this option to begin the sequence when the configuration memory is full. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Startup Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

XC4000 Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


XC4000 Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select this option to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select this option to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to activate or deactivate the readback capability of the configuration bitstream. To activate this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


XC4000 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC4000 Advanced Tab

XC4000EX/XL Only

Configuration Address Lines

Use this option to set the number of address lines that will be used by the FPGA during device configuration. Address lines are used to address data from a parallel PROM or flash memory device. Select either 18 or 22. If you choose 22, four extra device pins are activated as configuration address lines. The default is 18.

This option only applies to master parallel mode configuration. You must set this option in addition to setting the mode pins. Refer to The Programmable Logic Data Book for more information on address lines and master parallel mode configuration.


XC5200 Implementation Options Dialog Box

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC5200 Optimize and Map Tab

Logic Optimization Options

Trim Unconnected Logic

Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Replicate Logic to Allow Logic Level Reduction

Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.

Generate 5-Input Functions

Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.

Map Options

CLB Packing Strategy

This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop) pins on CLBs, and reducing the minimum signal combining requirements. The default is Fit Device.

Note:  Although this option makes a design denser, it can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option only if you are willing to trade performance for density.

Fit Device

Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.

Off

Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.

Ignore RLOC Constraints

Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.

Note:  To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

Create Detailed Map Report

Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.


XC5200 Place and Route Tab

Router Options

Run _ Routing Passes

Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At a Place & Route Effort Level closer to High Effort, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels closer to Fastest Runtime, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. See Options Dialog Box (FPGA) for more information. The default is Auto.

Run _ Delay-Based Cleanup Passes

Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.


XC5200 Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note:  When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

Produce Logic Level Timing Report

Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.

Produce Post Layout Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed, and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of the groups defined in the PCF file and all of the members defined within each group.

Limit Report to _ Paths per Timing Constraint

Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.

The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.

Report Paths Using Advanced Design Analysis

Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSET for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.

Report Paths in Timing Constraints

Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or user constraints (UCF) file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.

Report Paths Failing Timing Constraints

Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.

If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.

The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.


XC5200 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC5200 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC5200 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC5200	GR	per design or when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC5200 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


XC5200 Configuration Options Dialog Box

Click the Configuration, Startup, Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the configuration options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC5200 Configuration Tab

Configuration Rate

The XC5200 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 0.75 MHz (nominal).

Medium

Select Medium to set the configuration clock rate to 6 MHz (nominal).

Fast

Select Fast to set the configuration clock rate to 12 MHz (nominal).

Threshold Level

Inputs

Select one of the following input options. The default is Read from Design.

TTL

Select TTL to specify TTL-compatible inputs.

CMOS

Select CMOS to specify CMOS-compatible inputs.

Read from Design

Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.

Configuration Pins

Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the DONE pin. This resistor has a value of 2 to 8 kohm. Select this option only if you do not connect an external pull-up resistor to this pin.

Program

The PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The following options are available. The default is PullUp.

Float

Select Float to disable the pull-up resistor on the PROG pin.

PullUp

Select PullUp to enable an internal pull-up resistor on the PROG pin.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Oscillator Clock

This option determines whether the XC5200 oscillator will be driven by the internal clock or by a user clock. The default is CCLK.

CCLK

Select CCLK to drive the oscillator clock with the internal 16 MHz clock.

User Clock

Select User Clock to drive the oscillator with a user clock. If you specify User Clock, the clock must be connected to the OSC.CK pin of the device's OSC component.


XC5200 Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to synchronize to an internal clock provided in the FPGA device.

User Clock

Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.

Synchronize Start-up to DONE Input Pin

The startup sequence of the XC5200 can be synchronized with the signal on the DONE pin. Select this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is selected if the design configures a device connected in a daisy chain. Deselect this option to begin the startup sequence begins as soon as the configuration memory is full. By default, this option is off.

Output Events

There are three major output events which occur during a device startup.

•	Done (DONE pin going High)

•	Enable Outputs (device outputs no longer tristated)

•	Release Set/Reset (Global Set/Reset signal deasserted)

Depending on the settings for Startup Clock and Synchronize Start-up to DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

XC5200 Output Events Options Matrix

	CCLK Sync	CCLK No Sync	User Clock Sync	User Clock No Sync
DONE	C1-C3	C1-C4	C1, U2	C1, U2-U4
Enable Outputs	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
Release Set/Reset	C2, C3,  DI, DI+1	C2-C4	U2, DI, DI+1, DI+2	U2-U4
The definitions of the possible output events settings are as follows.

C1	First-Cclk rising edge after the length count is met

C2	Second-Cclk rising edge after the length count is met

C3	Third-Cclk rising edge after the length count is met

C4	Fourth-Cclk rising edge after the length count is met

U2	Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3	Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4	Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

DI	When the DoneIn signal goes High

DI+1	First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High

DI+2	Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High


XC5200 Readback Tab

Readback Clock

During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a User Clock. The default is CCLK.

CCLK

Select CCLK to clock out the readback data through an internal clock provided in the FPGA device.

User Clock

Select User Clock to clock out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.

Enable Bitstream Verification and In-Circuit Hardware Debugging

Use this option to enable or disable the readback capability of the configuration bitstream. To enable this feature, select this option and include the READBACK symbol in your design. Enabling this option generates a .ll file. By default, this option is on.

Abort Readback When TRIG Goes Inactive

Use this option to abort the readback sequence. Select this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol. By default, this option is off.


XC5200 Tie Tab

Tie Unused Interconnect

Select this option to cause all unused interconnect to be tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you use the Tie option, Design Rule Check (DRC) runs first. After DRC, the Tie option does the following.

•	Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)

•	Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical

•	Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs

By default, this option is off.

Tie Options

Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to complete the tiedown process if necessary. Use this option as a last resort after an attempt is made to use nets not marked critical. By default, this option is off.


XC9500 Implementation Options Dialog Box

Click the Translate, Basic, Advanced, Timing Reports, or Programming tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Fit, and Bitstream steps in the implementation flow. Use the different tabs of this dialog box to set the implementation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options which are optimized for speed, or click Help to obtain online help.

Note:  In addition to the Balanced optimization default options, there are two preset implementation option templates: Speed Optimization and Area optimization. The defaults described in the online Help only apply to the Balanced optimization options.


XC9500 Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with the FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top-level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the design is read incorrectly. By default, this option is off.

Note:  PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.


XC9500 Basic Tab

Use Global Clock(s)

Select this option to convert the p-term clock to a global clock. The global clock may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Output Enable(s)

Select this option to convert the p-term output enable to global output enable. Global output enable may allow you to meet your timing constraints more easily. By default, this option is on.

Use Global Set/Reset

Select this option to convert the p-term set/reset to global set/reset. Global set/reset may allow you to meet your timing constraints more easily. By default, this option is on.

Use Timing Constraints

Select this option to indicate that you want the software to use your timing constraints to perform timing-driven optimization in the fitting of your design. For this option to be useful, you must have previously created a timing constraints file or you must have included timing constraints in your design. By default, this option is on.

Use Design Location Constraints

Select this option to indicate that you want to use pinout and macrocell location information in the design file or constraint file. Deselect this option to allow the fitter to place pins and logic anywhere or as specified in the guide file. By default, this option is on.

Create Programmable Ground Pins on Unused I/O

Select this option to indicate that you want all unused I/O pads to be configured as ground pins. This can reduce ground bounce. By default, this option is off.

Macrocell Power Setting

Use this option to control device power consumption. Select Std (standard), Low, or Timing Driven to set the default power mode for the macrocells used to implement the design. The default is Std.

Note:  Any explicit power control statements in the design or constraints file have precedence over the Default Power Setting.

Std

Select Std to set the power mode for the macrocells to higher speed and higher power.

Low

Select Low to reduce power consumption and reduce speed.

Timing Driven

Select Timing Driven to set the power consumption based on your timing constraints.

Output Slew Rate

Use this option to modify the output slew rate. Limiting the slew rate reduces output switching surges in the device. You can control the transition time of device output pins by setting the slew rate to Fast, Slow, or Timing Driven. The default is Fast.

Note:  Any explicit slew rate control statements in the design or constraints file have precedence over the Output Slew Rate. This setting has no effect on third-party tools that create explicit slew rate statements.

Fast

Select Fast to use more current and enable faster logic responses.

Slow

Select Slow to use less current and avoid ground bounce.

Timing Driven

Select Timing Driven to control the transition time based on your timing constraints.


XC9500 Advanced Tab

Use Timing Optimization

Select this option to perform timing optimization. Timing optimization shortens the critical paths and allocates the fastest resources for a design, assuming that all paths are equally critical. In some cases, timing optimization trades density for speed. By default, this option is on.

Use Multi-Level Logic Optimization

This option simplifies the total number of logic expressions in a design, and then collapses the logic in order to meet user objectives such as density, speed and timing constraints. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of p-terms.

Multi-level Logic Optimization optimizes combinatorial logic from your design. Combinatorial logic includes the following types of logic.

•	Register-to-register logic

•	Pad-to-register logic

•	Register-to-pad logic

•	Pad-to-pad logic

Multi-level Logic Optimization operates on combinatorial logic according to the following rules.

•	If timing constraints are set, the program optimizes for speed to meet timing constraints.

•	If timing constraints are not set, the program optimizes either for speed or density, depending on the user setting for the Use Timing Optimization option.

•	If Use Timing Optimization is turned on, the combinatorial logic will be mapped for speed.

•	If Use Timing Optimization is turned off, the combinatorial logic will be mapped for density. The goal of optimization will then be to reduce the total number of p-terms.

•	Logic marked with the attribute MINIMIZE=OFF will not be extracted or optimized.

By default, this option is on.

Enable D <--> T Type Transform Optimization

Select this option to allow the software to convert D-type flip-flops to T-type flip-flops. This option allows the software to choose the implementation that requires the smaller amount of logic resources. By default, this option is on.

Collapsing Pterm Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of product terms in the resulting logic function does not exceed the p-term limit. If the path delay of a logic function is not acceptable, increase the p-term limit to allow the larger functions to be further flattened. Choose a number from 2 to 90. The default p-term limit for the XC9500 family is 25 p-terms.

XC9500 Only — Use Advanced Fitting

Select this option to enable an advanced fitting strategy that favors placing signals with common inputs in the same function block. This usually allows you to pack more logic into the same device. Disable this option if the software has trouble fitting a design that used to fit with an older version of software. By default, this option is on.

XC9500 Only — Use Local Macrocell Feedback

Select this option to enable the software to use local macrocell feedback whenever possible. The local feedback path (from a macrocell-output to an input of the same function block) takes less time than the global feedback path. Using local feedback can speed up your design but can also make it difficult to keep the same timing after a design change.

To take maximum advantage of local feedback, control the placement to group appropriate signals into the same function block. In order to fit a design, the software may require wire-ANDing in the interconnect which can prevent local feedback use. However, you can force a local feedback by applying a timespec and assigning the signals to the same function block. This method prevents wire-ANDing of local feedback signal and works even if you disable the Use Local Macrocell Feedback option. By default, this option is on.

Note:  The XC9536 device does not have local feedback.

XC9500 Only — Use Local Pin Feedback

Select this option to enable the software to use local I/O pin feedback whenever possible. The pin feedback path takes less time than the FastCONNECT path. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have 3-state control or Slow slew rate. By default, this option is on.

XC9500 Only and XC9500XL/XV Only — Collapsing Input Limit

This option controls the degree to which a design netlist is flattened. A logic gate can collapse forward into a subsequent gate only if the number of inputs in the resulting logic function does not exceed the input limit. If the path delay of a logic function is not acceptable, increase the input limit to allow the larger functions to be further flattened. For XC9500 devices, choose a number from 2 to 36. The default is 36. For XC9500XL and XC9500XV devices, choose a number from 2 to 54. The default is 54.


XC9500 Timing Reports Tab

Produce Post Fitting Timing Report

Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is fitted. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.

Note:  If you select this option, the report is automatically generated during the Fit step.

Timing Report Format

This option allows you to choose the level of detail given in your timing report. The default is Summary.

Summary

Select Summary to generate a report that contains summary information and design statistics.

Detailed

Select Detailed to generate a report that lists delay information for all nets and paths.


XC9500 Programming Tab

Signature/User Code

Select Use <design name> or enter a unique text string in the Specify As field to identify the configuration data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the JTAG Programmer to identify the configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is Use <design_name>.

Jedec Test Vector File

Use this option to include a TMV file in your JEDEC file. The TMV file is a test vector file generated when ABEL compiles a design containing user test vectors. Click Browse to look for a TMV file.


XC9500 Simulation Options Dialog Box

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the front and back-end simulation options.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.


XC9500 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

•	EDIF

•	VHDL

•	Verilog

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.


XC9500 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The following table shows the Global Set/Reset port information for the XC9500 device family.

Device Family	Port Name	When Top-Level Global Set/Reset Port Appears	Polarity
XC9500	PRLD	when option is used	active-High
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note:  This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note:  This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.


XC9500 EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

Move Pin-based Timing Properties to Instances

This option annotates all timing properties to instances.

Move External Delays to Buffers on Pins with Internal Delay

This option models certain delays using buffers.


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Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
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Glossary

asynchronous debugging

BIT file

bitstream (BIT file)

block

bottom-up design

BUFT

byte-wide PROM

CCLK pin

CLKI pin

CLKO pin

clock input path

clock skew

critical path

daisy chain

debugging

DIN pin

DONE pin

downloading

D/P pin

EDIF

EXORmacs (Motorola)

external clock

fitting

GND pin

group

guide file

HDL

HEX

hold time

INIT pin

instance

internal XChecker clock

IOB (input/output block)

.ll file

loading direction

logic icon

logic synthesis

mapping

MCS-86 (Intel)

net

number of clock cycles

one-to-one logic

optimization

pad

pin

place effort

placer

placing

primitive

probing

PROG pin

programming

PROM

PROM file

RBT file

RD pin

readback

route effort

router

routing

RPM

RST pin

RT pin

schematic

script

SDF

serial PROM

setup time

snapshot

states

static timing analysis

status bar

synchronous debugging

synthesis

TCK pin

TDI pin

TEKHEX (Tektronix)

timing

timing constraints

TMS pin

toolbar

toolbox

top-down design

TRIG pin

trigger

TTY

Universal Interconnect Matrix (UIM)

VCC pin

verification

Verilog

VHDL

waveform

WIR file

workspace


asynchronous debugging (definition)
asynchronous debugging

An FPGA debugging mode in which you capture data without controlling your system clock.


BIT file (definition)
BIT file

Synonym for a bitstream file.


bitstream (definition)
bitstream (BIT file)

A stream of data that contains location information for logic on a device, that is, the placement of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back.

A bitstream file has a .bit extension.


block (definition)
block

A group of one or more logic functions.


bottom-up design (definition)
bottom-up design

Design methodology where already defined HDL blocks are merged into one overall desired design behavior. The lowest level portion of your design is completed first. Only after the low-level building blocks are complete do you finish higher-level hierarchical blocks in your design. This methodology is typically used with schematic capture programs.


BUFT (definition)
BUFT

Tristate buffer.


byte-wide PROM (definition)
byte-wide PROM

A PROM that supplies data one byte at a time. It is used for master parallel mode configuration of FPGAs.


CCLK pin (definition)
CCLK pin

The XChecker pin that provides the configuration clock for the device or daisy chain of devices during a download. This is also the pin on an FPGA that receives the configuration clock.


CLKI pin (definition)
CLKI pin

XChecker clock input pin. CLKI provides an external clock to the Hardware Debugger so that in conjunction with the CLKO pin, the Debugger can control the application of the external clock to the device being debugged.


CLKO pin (definition)
CLKO pin

XChecker clock output pin. CLKO supplies the Hardware-Debugger-controlled clock to the device being debugged. The source of CLKO is one of the following: CLKI, logic 1, logic 0, or the internal XChecker clock.


clock input path (definition)
clock input path

A path starting at either an input of the chip or at the output of a flip-flop, latch, or RAM, and ending at any clock pin on a flip-flip or latch enable. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.


clock skew (definition)
clock skew

The maximum difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop. It is also referred to as clock delay.


critical path (definition)
critical path

A signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which may include I/O pads.


daisy chain (definition)
daisy chain

A series of bitstream files concatenated in one file. It can be used to program several FPGAs connected in a daisy chain board configuration.


debugging (definition)
debugging

The process of reading back or probing the states of a configured device to ensure that the device is behaving as expected while in circuit.


DIN pin (definition)
DIN pin

On an FPGA, the data pin that accepts a serial version of a bitstream. On the XChecker cable, it provides the bitstream data and connects to the DIN pin of the target FPGA.


DONE pin (definition)
DONE pin

Dual-function pin. As an input, it can be configured to delay the global logic initialization or the enabling of outputs. As an output, it indicates the completion of the configuration process.


downloading (definition)
downloading

Configuring or programming a device by sending bitstream data to the device.


D/P pin (definition)
D/P pin

Dual-function pin. As an input (PROGRAM), it initiates a reconfiguration of a configured device. As an output (DONE), signals the end of configuration.


EDIF (definition)
EDIF

Electronic Data Interchange Format, an industry standard file format for specifying a design netlist. It is generated by a third-party design-entry tool.


EXORmacs (definition)
EXORmacs (Motorola)

A PROM format supported by the Xilinx tools. Its maximum address is 16 777 216. This format supports PROM files of up to (8 x 16 777 216) = 134 217 728 bits.


external clock (definition)
external clock

The system clock that XChecker uses from the target board during synchronous mode debugging. To use an external clock, connect the system clock to the XChecker cable using the CLKI pin and the XChecker clock to the FPGA device using the CLKO pin.


fitting (definition)
fitting

The process of putting logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically, and because of the UIM architecture, all designs are routable.


GND pin (definition)
GND pin

Ground (0 volts).


group (definition)
group

A collection of common signals to form a bus. In the case of a counter, for example, the different signals that produce the actual counter values can be combined to form an alias, or group.


guide file (definition)
guide file

A previously placed and routed FPGA or fitted CPLD design file that can be used in a subsequent place and route or fitting operation.


HDL (definition)
HDL

Hardware Description Language. The most common HDLs in use today are Verilog and VHDL. They describe designs in a technology-independent manner using a high level of abstraction.


HEX (definition)
HEX

A simple text dump of the PROM data in HEX format. It has unlimited data capacity.


hold time (definition)
hold time

The time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


INIT pin (definition)
INIT pin

Device pin indicating when a device is ready to receive configuration data after power-up.


instance (definition)
instance

One specific gate or hierarchical element in a design or netlist. The term "symbol" often describes instances in a schematic drawing. Instances are interconnected by pins and nets. Pins are ports through which connections are made from an instance to a net. A design that is flattened to the lowest level constituents is described using primitive instances.


internal XChecker clock (definition)
internal XChecker clock

The clock internal to XChecker cable that can be applied by the XChecker CLKO pin to a device being debugged.


IOB (definition)
IOB (input/output block)

A collection or grouping of basic elements that implement the input and output functions of an FPGA device.


.ll file (definition)
.ll file

The logic allocation file, which indicates the bitstream position of storage elements such as latches, flip-flops, and IOB inputs and outputs. The Hardware Debugger uses this file to locate signal values inside a readback bitstream.


loading direction (definition)
loading direction

The direction of the addresses in which data is stored on your PROM. In the Up direction, the data is stored in ascending address order. In the Down direction, the data is stored in descending address order.


logic icon (definition)
logic icon

Graphical representation of a logic resource, such as a flip-flop, buffer, or register.


logic synthesis (definition)
logic synthesis

A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a netlist using a library containing primitives.


mapping (definition)
mapping

The process of assigning a design's logic elements to the specific physical elements, such as CLBs and IOBs, that actually implement logic functions in a device.


MCS-86 (definition)
MCS-86 (Intel)

A PROM format supported by the Xilinx tools. Its maximum address is 1 048 576. This format supports PROM files of up to (8 x 1 048 576) = 8 388 608 bits.


net (definition)
net

A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.


number of clock cycles (definition)
number of clock cycles

Number of clocks that occur between snapshots during synchronous mode debugging. When capturing multiple snapshots, the number of snapshots is used as a trigger for capturing each snapshot.


one-to-one logic (definition)
one-to-one logic

In the context of Xilinx FPGA devices, the exact correspondence between the logic specified in the design entry phase and the logic implemented in the device. For example, if you draw three inverters in your design, there are three corresponding inverters in the programmed device. This correspondence makes back-annotation of timing delays very straightforward and ensures that there are no differences between your original design and the finished device.


optimization (definition)
optimization

The process that decreases the area or increases the speed of a design.


pad (definition)
pad

The physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.


pin (definition)
pin

A symbol pin or package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.


place effort (definition)
place effort

User-controlled parameter that balances run-time with placement efficiency for the Flow Engine.


placer (definition)
placer

The utility that maps logic from your design into specific locations in the target FPGA chip.


placing (definition)
placing

The process of assigning physical device cell locations to the logic in a design.


primitive (definition)
primitive

A logic element that directly corresponds, or maps, to a basic silicon element.


probing (definition)
probing

The process of examining the states of an FPGA device.


PROG pin (definition)
PROG pin

An XChecker pin that provides a reprogram pulse to XC4000, XC5200, Spartan2, and Virtex devices when connected to the PROG pin of the device.


programming (definition)
programming

The process of configuring the programmable interconnect in the FPGA.


PROM (definition)
PROM

A programmable read-only memory.


PROM file (definition)
PROM file

A file consisting of one or more BIT files (bitstreams) formed into one or more datastreams. The file is formatted in one of four industry-standard formats: Intel MCS-86, Tektronics TEKHEX, Motorola EXORmacs or HEX. The PROM file includes headers that specify the length of the bitstreams, as well as all the framing and control information necessary to configure the FPGAs. It can be used to program one or more devices.


RBT file (definition)
RBT file

A raw BIT format file; the ASCII version of the BIT file.


RD pin (definition)
RD pin

XChecker readback data pin.


readback (definition)
readback

The process of reading the logic downloaded to an FPGA device. There are two types of readback.

•	A readback with a filter that extracts the configuration bits to verify that a design was downloaded in its entirety.

•	A readback with a filter that extracts the states of design storage elements, CLB outputs, and IOB outputs to ensure that the device is behaving as expected.


route effort (definition)
route effort

User-controlled parameter that balances run-time with routing efficiency for the Flow Engine.


router (definition)
router

The utility that determines which wires to use to connect logic.


routing (definition)
routing

The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.


RPM (definition)
RPM

Relationally placed macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.


RST pin (definition)
RST pin

An XChecker pin that can be driven Low after configuration to reset the target FPGA internal latches and flip-flops.


RT pin (definition)
RT pin

The XChecker readback trigger pin.


schematic (definition)
schematic

A hierarchical drawing representing a design in terms of user and library components.


script (definition)
script

A series of commands that automatically execute a complex operation such as the steps in a design flow.


SDF (definition)
SDF

Standard Delay Format, which is an industry-standard file format for specifying timing information. It is usually used for simulation.


serial PROM (definition)
serial PROM

A PROM that is read one bit at a time.


setup time (definition)
setup time

The time prior to a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.


snapshot (definition)
snapshot

Readback data that contains the values of all storage elements, CLB outputs, and IOB inputs and outputs of a design at a point in time.


states (definition)
states

A set of values stored in the memory elements of a device (flip-flops, latches, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback. To each state there corresponds a specific set of logical values.


static timing analysis (definition)
static timing analysis

A point-to-point delay analysis of a design network.


status bar (definition)
status bar

An area located at the bottom of a window that provides information about the commands that you are about to select or that are being processed.


synchronous debugging (definition)
synchronous debugging

A debug mode in which you use the XChecker cable to have full control of the clock.


synthesis (definition)
synthesis

A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a netlist using a library containing primitives.


TCK pin (definition)
TCK pin

A pin on the XChecker cable. This output supplies clocks for a boundary scan port on an XC9500 device. The JTAG software must be used to drive the boundary scan port on the Xchecker cable.


TDI pin (definition)
TDI pin

A pin on the XChecker cable. This input receives data from the boundary scan chain. The JTAG software must be used to drive the boundary scan port on the XChecker cable.


TEKHEX (definition)
TEKHEX (Tektronix)

A PROM format supported by Xilinx. Its maximum address is 65 536. This format supports PROM files of up to (8 x 65 536) = 524 288 bits.


timing (definition)
timing

A process that calculates the delays associated with each of the routed nets in a design.


timing constraints (definition)
timing constraints

A user specification of the maximum allowable delay on any given set of paths in a design. Timing constraints can be entered on a schematic or in a user constraints (UCF) file.


TMS pin (definition)
TMS pin

A pin on the XChecker cable. This output drives the mode of the boundary scan state machine. The JTAG software must be used to drive the boundary scan port on the XChecker cable.


toolbar (definition)
toolbar

A field located under the menu bar at the top of a window. It contains a series of buttons that you click on to execute some of the most commonly used commands. These buttons are an alternative to the menu commands.


toolbox (definition)
toolbox

The toolbox is a field located in the Design Manager main window. It contains a series of buttons that you click on to invoke tools such as the Flow Engine, Timing Analyzer, Floorplanner, PROM File Formatter, Hardware Debugger, FPGA Editor, Chip Viewer, and JTAG Programmer.


top-down design (definition)
top-down design

A process that starts a design with the highest level of abstraction and gradually designs underlying blocks until the complete design is implemented in the target technology. Top-down design is often technology-independent at the highest levels of design abstraction.


TRIG pin (definition)
TRIG pin

An XChecker external trigger pin that causes the Hardware Debugger to initiate a readback of the device being debugged.


trigger (definition)
trigger

An external signal that tells the Hardware Debugger to read a snapshot.


TTY (definition)
TTY

Textual command line interface.


Universal Interconnect Matrix (definition)
Universal Interconnect Matrix (UIM)

The routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing 100% routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.


VCC pin (definition)
VCC pin

Power (5 volts).


verification (definition)
verification

The process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.


Verilog (definition)
Verilog

Commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1364-1995. Verilog was originally developed by Cadence Design Systems and is now maintained by OVI.

A Verilog file has a .v extension.


VHDL (definition)
VHDL

An acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High-Speed Integrated Circuits). It can be used to describe the concurrent and sequential behavior of a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. VHDL is IEEE standard 1076-1993.

A VHDL file has a .vhd or .vhdl extension.


waveform (definition)
waveform

A graphical representation of a set of simulation transitions that depicts the digital or electrical values of a node on the schematic.


WIR file (definition)
WIR file

Viewlogic netlist files built by ViewDraw, PROcapture, or ViewSynthesis. A WIR file is an intermediate design file generated by the Viewlogic design tools.


workspace (definition)
workspace

In the PROM File Formatter, workspace is a frame and an empty data stream. When you add files into the data stream, the horizontal arrows indicate the concatenation of files.