Creating Readback Registers in VHDL

The following code shows how to create a readback register using VHDL:

process (clk) begin

if clk’event and clk=‘1’ then

if write_enable=‘1’ then

data_reg_int <= data_reg;

-- write data from I/O pin into register

end if;

end if;

end process;
data_reg <= data_reg_int when read_enable=‘1’ else ‘Z’;

-- Drive I/O pin when read_enable is high