Pipeline for Speed

• Use Synchronous Design

• Pipelining improves speed

  • Consider wherever latency is not an issue
  • Use for terminal counts, carry lookahead, etc.

• How to estimate the clock period

  Example for 50 MHz clock frequency in XC4000XL-3:
  
  Clock period 20 ns
  One level - 8 ns (tCO + tNET + tSU)
  Delay allowance 12 ns
  Each added level / 6 ns (tPD + tNET)
  Added levels of logic allowed 2 CLBs

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기