Foundation Series Quick Start Guide 1.5

Preface

About this Quick Start Guide

This Quick Start Guide is intended to give a description of the features and additions to Xilinx's newest product - Foundation 1.5. The primary focus of this guide is to show the relationship between the design entry tools and the design implementation tools.

This guide should be used as the initial learning tool for designers who are unfamiliar with the features of the Foundation software.

Quick Start Guide Contents

This guide covers the following topics.

• Chapter 1, “Features of Foundation Series 1.5,” introduces the new and enhanced features of the Foundation 1.5 software and provides information about both FPGA- and CPLD-specific features.
  
  
• Chapter 2, “Setting Up the Foundation Tools,” gives instructions for installing Foundation 1.5 and provides you with information about the type of computer you need to successfully implement your designs.
  
  
• Chapter 3, “Foundation Overview,” looks in-depth at the capability and flexibility of the Foundation software.
  
  
• Chapter 4, “In-Depth Tutorial - Schematic-Based Design,” explains many different facets of a schematic-based Foundation design flow using a design of a runner's stopwatch called “Watch”. This chapter also shows how to use Foundation accessories such as the State Editor, Project Manager, LogiBLOX, and the HDL Editor.
  
  
• Chapter 5, “In-Depth Tutorial - HDL-Based Design,” guides you through a typical HDL-based design procedure using a design of a runner's stopwatch called “Watch”.
  
  
• Chapter 6, “In-Depth Tutorial - Functional Simulation,” explains how to use the Logic Simulator to simulate a design before design implementation to verify that the logic that you have created is correct.
  
  
• Chapter 7, “In-Depth Tutorial - Design Implementation,” describes how to Translate, Map, Place, Route, (Fit for CPLDs) and generate a Bit file for designs.
  
  
• Chapter 8, “In-Depth Tutorial - Timing Simulation,” explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst-case conditions.
  
  
• Chapter 9, “In-Depth Tutorial - Hardware Verification,” demonstrates how to use the Hardware Debugger to download, verify, and debug a single design using a Xilinx demonstration board as your target device.
  
  
• Appendix A, “Glossary,” defines some of the commonly used terms in this Guide.
  
  

Conventions

Typographical

This manual uses the following conventions. An example illustrates each convention.

• Courier font indicates messages, prompts, and program files that the system displays.
  
  speed grade: -100
  
  
• Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].
  
  rpt_del_net=
  
  Courier bold also indicates commands that you select from a menu or buttons in dialog boxes that you click.
  
  File Open
  Click OK
  
  
• Italic font denotes the following items.
  
  
  • Variables in a syntax statement for which you must supply values
    
    edif2ngd design_name
    
    
  • References to other manuals
    
    See the Development System Reference Guide for more information.
    
    
    
    
  • Emphasis in text
    
    If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
    
    
• Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.
  
  edif2ngd [option_name] design_name
  
  Square brackets also enclose footnotes in tables that are printed out as hardcopy in DynaText^®.
  
  
• Braces “{ }” enclose a list of items from which you must choose one or more.
  
  lowpwr ={on|off}
  
  
• A vertical bar “|” separates items in a list of choices.
  
  lowpwr ={on|off}
  
  
• A vertical ellipsis indicates repetitive material that has been omitted.
  
  IOB #1: Name = QOUT'
  IOB #2: Name = CLKIN'
  .
  .
  .
  
  
• A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.
  
  allow block block_name loc1 loc2 ... locn;
  
  

Online Document

Xilinx has created several conventions for use within the DynaText online documents.

• Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
  
  
• Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.
  
  
• There are several types of icons.
  
  Iconized figures are identified by the figure icon.
  
  
  
  Iconized tables are identified by the table icon.
  
  
  
  The Copyright icon displays in the upper left corner on the first page of every Xilinx online document.
  
  
  
  The DynaText footnote icon displays next to the footnoted text.
  
  
  
  Double-click these icons to display figures, tables, copyright information, or footnotes in a separate window.
  
  
• Inline figures display within the text of a document. You can display these figures in a separate window by clicking the figure.