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 DIG                         VHDL / ASIC                       #2816/2820
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 제  목:Aldec's Active-HDL 3.5 Beta 2가 나왔군요
 보낸이:국일호  (GoodKook)    1999-04-30 02:25  조회:87  1/3
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 3.3 버젼 까지만 해도 Active-VHDL 이었는데 3,5가 나오면서 제품이름도 
 Active-HDL 3.5 라고. 현재 베타 2이고 VHDL/Verilog 그리고 EDIF 시뮬레이션
 가능 합니다.
 
 비쥬얼 툴들이 강화 되었는데 State Machine, Block Diagram 등이 비쥬얼로
 설계할수 있고 HDL Generation 이 가능 하다고...
 
 The new features include:

• Block Diagram Editor for fast graphical HDL design entry
• All new HDL Editor with auto-complete and HDL structure display
• Dataflow Debugger which graphically traces signal flow
• CallStack window for advanced procedure and variable tracing
• Netlist compilation mode for fast loading of large structural designs
• EDIF Netlist Support allows you to simulate synthesis and FPGA tools output netlist
• FPGA Booster accelerates Altera and Xilinx design simulation from 10 to 100 times
• TCL/TK Scripting for easy creation of interface programs
• Waveform Comparison graphically compares two waveform diagrams
• On-Line Documentation using HTML Help
• Batch mode support for simulation tasks without GUI

 현재 베타 2가 eval. 가능합니다 aldec 사 홈페이지에 가면 다운 받을수 있읍니다.
 
 http://www.aldec.com
 
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 GoodKook
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